1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineScheduler.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Transforms/IPO.h"
43 #include "llvm/Transforms/IPO/AlwaysInliner.h"
44 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
45 #include "llvm/Transforms/Scalar.h"
46 #include "llvm/Transforms/Scalar/GVN.h"
47 #include "llvm/Transforms/Utils.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 static cl::opt<bool> EnableDPPCombine(
109   "amdgpu-dpp-combine",
110   cl::desc("Enable DPP combiner"),
111   cl::init(true));
112 
113 // Enable address space based alias analysis
114 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
115   cl::desc("Enable AMDGPU Alias Analysis"),
116   cl::init(true));
117 
118 // Option to run late CFG structurizer
119 static cl::opt<bool, true> LateCFGStructurize(
120   "amdgpu-late-structurize",
121   cl::desc("Enable late CFG structurization"),
122   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
123   cl::Hidden);
124 
125 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
126   "amdgpu-function-calls",
127   cl::desc("Enable AMDGPU function call support"),
128   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
129   cl::init(true),
130   cl::Hidden);
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable amdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool> EnableLowerKernelArguments(
140   "amdgpu-ir-lower-kernel-arguments",
141   cl::desc("Lower kernel argument loads in IR pass"),
142   cl::init(true),
143   cl::Hidden);
144 
145 // Enable atomic optimization
146 static cl::opt<bool> EnableAtomicOptimizations(
147   "amdgpu-atomic-optimizations",
148   cl::desc("Enable atomic optimizations"),
149   cl::init(false),
150   cl::Hidden);
151 
152 // Enable Mode register optimization
153 static cl::opt<bool> EnableSIModeRegisterPass(
154   "amdgpu-mode-register",
155   cl::desc("Enable mode register pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 extern "C" void LLVMInitializeAMDGPUTarget() {
160   // Register the target
161   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
162   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
163 
164   PassRegistry *PR = PassRegistry::getPassRegistry();
165   initializeR600ClauseMergePassPass(*PR);
166   initializeR600ControlFlowFinalizerPass(*PR);
167   initializeR600PacketizerPass(*PR);
168   initializeR600ExpandSpecialInstrsPassPass(*PR);
169   initializeR600VectorRegMergerPass(*PR);
170   initializeGlobalISel(*PR);
171   initializeAMDGPUDAGToDAGISelPass(*PR);
172   initializeGCNDPPCombinePass(*PR);
173   initializeSILowerI1CopiesPass(*PR);
174   initializeSIFixSGPRCopiesPass(*PR);
175   initializeSIFixVGPRCopiesPass(*PR);
176   initializeSIFixupVectorISelPass(*PR);
177   initializeSIFoldOperandsPass(*PR);
178   initializeSIPeepholeSDWAPass(*PR);
179   initializeSIShrinkInstructionsPass(*PR);
180   initializeSIOptimizeExecMaskingPreRAPass(*PR);
181   initializeSILoadStoreOptimizerPass(*PR);
182   initializeAMDGPUFixFunctionBitcastsPass(*PR);
183   initializeAMDGPUAlwaysInlinePass(*PR);
184   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
185   initializeAMDGPUAnnotateUniformValuesPass(*PR);
186   initializeAMDGPUArgumentUsageInfoPass(*PR);
187   initializeAMDGPUAtomicOptimizerPass(*PR);
188   initializeAMDGPULowerKernelArgumentsPass(*PR);
189   initializeAMDGPULowerKernelAttributesPass(*PR);
190   initializeAMDGPULowerIntrinsicsPass(*PR);
191   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
192   initializeAMDGPUPromoteAllocaPass(*PR);
193   initializeAMDGPUCodeGenPreparePass(*PR);
194   initializeAMDGPURewriteOutArgumentsPass(*PR);
195   initializeAMDGPUUnifyMetadataPass(*PR);
196   initializeSIAnnotateControlFlowPass(*PR);
197   initializeSIInsertWaitcntsPass(*PR);
198   initializeSIModeRegisterPass(*PR);
199   initializeSIWholeQuadModePass(*PR);
200   initializeSILowerControlFlowPass(*PR);
201   initializeSIInsertSkipsPass(*PR);
202   initializeSIMemoryLegalizerPass(*PR);
203   initializeSIOptimizeExecMaskingPass(*PR);
204   initializeSIFixWWMLivenessPass(*PR);
205   initializeSIFormMemoryClausesPass(*PR);
206   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
207   initializeAMDGPUAAWrapperPassPass(*PR);
208   initializeAMDGPUExternalAAWrapperPass(*PR);
209   initializeAMDGPUUseNativeCallsPass(*PR);
210   initializeAMDGPUSimplifyLibCallsPass(*PR);
211   initializeAMDGPUInlinerPass(*PR);
212 }
213 
214 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
215   return llvm::make_unique<AMDGPUTargetObjectFile>();
216 }
217 
218 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
219   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
220 }
221 
222 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
223   return new SIScheduleDAGMI(C);
224 }
225 
226 static ScheduleDAGInstrs *
227 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
228   ScheduleDAGMILive *DAG =
229     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
230   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
231   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
232   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
233   return DAG;
234 }
235 
236 static ScheduleDAGInstrs *
237 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
238   auto DAG = new GCNIterativeScheduler(C,
239     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
240   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
241   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
242   return DAG;
243 }
244 
245 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
246   return new GCNIterativeScheduler(C,
247     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
248 }
249 
250 static ScheduleDAGInstrs *
251 createIterativeILPMachineScheduler(MachineSchedContext *C) {
252   auto DAG = new GCNIterativeScheduler(C,
253     GCNIterativeScheduler::SCHEDULE_ILP);
254   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
255   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
256   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
257   return DAG;
258 }
259 
260 static MachineSchedRegistry
261 R600SchedRegistry("r600", "Run R600's custom scheduler",
262                    createR600MachineScheduler);
263 
264 static MachineSchedRegistry
265 SISchedRegistry("si", "Run SI's custom scheduler",
266                 createSIMachineScheduler);
267 
268 static MachineSchedRegistry
269 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
270                              "Run GCN scheduler to maximize occupancy",
271                              createGCNMaxOccupancyMachineScheduler);
272 
273 static MachineSchedRegistry
274 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
275   "Run GCN scheduler to maximize occupancy (experimental)",
276   createIterativeGCNMaxOccupancyMachineScheduler);
277 
278 static MachineSchedRegistry
279 GCNMinRegSchedRegistry("gcn-minreg",
280   "Run GCN iterative scheduler for minimal register usage (experimental)",
281   createMinRegScheduler);
282 
283 static MachineSchedRegistry
284 GCNILPSchedRegistry("gcn-ilp",
285   "Run GCN iterative scheduler for ILP scheduling (experimental)",
286   createIterativeILPMachineScheduler);
287 
288 static StringRef computeDataLayout(const Triple &TT) {
289   if (TT.getArch() == Triple::r600) {
290     // 32-bit pointers.
291       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
292              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
293   }
294 
295   // 32-bit private, local, and region pointers. 64-bit global, constant and
296   // flat.
297     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
298          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
299          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
300 }
301 
302 LLVM_READNONE
303 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
304   if (!GPU.empty())
305     return GPU;
306 
307   if (TT.getArch() == Triple::amdgcn)
308     return "generic";
309 
310   return "r600";
311 }
312 
313 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
314   // The AMDGPU toolchain only supports generating shared objects, so we
315   // must always use PIC.
316   return Reloc::PIC_;
317 }
318 
319 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
320                                          StringRef CPU, StringRef FS,
321                                          TargetOptions Options,
322                                          Optional<Reloc::Model> RM,
323                                          Optional<CodeModel::Model> CM,
324                                          CodeGenOpt::Level OptLevel)
325     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
326                         FS, Options, getEffectiveRelocModel(RM),
327                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
328       TLOF(createTLOF(getTargetTriple())) {
329   initAsmInfo();
330 }
331 
332 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
333 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
334 
335 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
336 
337 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
338   Attribute GPUAttr = F.getFnAttribute("target-cpu");
339   return GPUAttr.hasAttribute(Attribute::None) ?
340     getTargetCPU() : GPUAttr.getValueAsString();
341 }
342 
343 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
344   Attribute FSAttr = F.getFnAttribute("target-features");
345 
346   return FSAttr.hasAttribute(Attribute::None) ?
347     getTargetFeatureString() :
348     FSAttr.getValueAsString();
349 }
350 
351 /// Predicate for Internalize pass.
352 static bool mustPreserveGV(const GlobalValue &GV) {
353   if (const Function *F = dyn_cast<Function>(&GV))
354     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
355 
356   return !GV.use_empty();
357 }
358 
359 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
360   Builder.DivergentTarget = true;
361 
362   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
363   bool Internalize = InternalizeSymbols;
364   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
365   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
366   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
367 
368   if (EnableFunctionCalls) {
369     delete Builder.Inliner;
370     Builder.Inliner = createAMDGPUFunctionInliningPass();
371   }
372 
373   Builder.addExtension(
374     PassManagerBuilder::EP_ModuleOptimizerEarly,
375     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
376                                          legacy::PassManagerBase &PM) {
377       if (AMDGPUAA) {
378         PM.add(createAMDGPUAAWrapperPass());
379         PM.add(createAMDGPUExternalAAWrapperPass());
380       }
381       PM.add(createAMDGPUUnifyMetadataPass());
382       if (Internalize) {
383         PM.add(createInternalizePass(mustPreserveGV));
384         PM.add(createGlobalDCEPass());
385       }
386       if (EarlyInline)
387         PM.add(createAMDGPUAlwaysInlinePass(false));
388   });
389 
390   const auto &Opt = Options;
391   Builder.addExtension(
392     PassManagerBuilder::EP_EarlyAsPossible,
393     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
394                                       legacy::PassManagerBase &PM) {
395       if (AMDGPUAA) {
396         PM.add(createAMDGPUAAWrapperPass());
397         PM.add(createAMDGPUExternalAAWrapperPass());
398       }
399       PM.add(llvm::createAMDGPUUseNativeCallsPass());
400       if (LibCallSimplify)
401         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
402   });
403 
404   Builder.addExtension(
405     PassManagerBuilder::EP_CGSCCOptimizerLate,
406     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
407       // Add infer address spaces pass to the opt pipeline after inlining
408       // but before SROA to increase SROA opportunities.
409       PM.add(createInferAddressSpacesPass());
410 
411       // This should run after inlining to have any chance of doing anything,
412       // and before other cleanup optimizations.
413       PM.add(createAMDGPULowerKernelAttributesPass());
414   });
415 }
416 
417 //===----------------------------------------------------------------------===//
418 // R600 Target Machine (R600 -> Cayman)
419 //===----------------------------------------------------------------------===//
420 
421 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
422                                      StringRef CPU, StringRef FS,
423                                      TargetOptions Options,
424                                      Optional<Reloc::Model> RM,
425                                      Optional<CodeModel::Model> CM,
426                                      CodeGenOpt::Level OL, bool JIT)
427     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
428   setRequiresStructuredCFG(true);
429 
430   // Override the default since calls aren't supported for r600.
431   if (EnableFunctionCalls &&
432       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
433     EnableFunctionCalls = false;
434 }
435 
436 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
437   const Function &F) const {
438   StringRef GPU = getGPUName(F);
439   StringRef FS = getFeatureString(F);
440 
441   SmallString<128> SubtargetKey(GPU);
442   SubtargetKey.append(FS);
443 
444   auto &I = SubtargetMap[SubtargetKey];
445   if (!I) {
446     // This needs to be done before we create a new subtarget since any
447     // creation will depend on the TM and the code generation flags on the
448     // function that reside in TargetOptions.
449     resetTargetOptions(F);
450     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
451   }
452 
453   return I.get();
454 }
455 
456 TargetTransformInfo
457 R600TargetMachine::getTargetTransformInfo(const Function &F) {
458   return TargetTransformInfo(R600TTIImpl(this, F));
459 }
460 
461 //===----------------------------------------------------------------------===//
462 // GCN Target Machine (SI+)
463 //===----------------------------------------------------------------------===//
464 
465 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
466                                    StringRef CPU, StringRef FS,
467                                    TargetOptions Options,
468                                    Optional<Reloc::Model> RM,
469                                    Optional<CodeModel::Model> CM,
470                                    CodeGenOpt::Level OL, bool JIT)
471     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
472 
473 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
474   StringRef GPU = getGPUName(F);
475   StringRef FS = getFeatureString(F);
476 
477   SmallString<128> SubtargetKey(GPU);
478   SubtargetKey.append(FS);
479 
480   auto &I = SubtargetMap[SubtargetKey];
481   if (!I) {
482     // This needs to be done before we create a new subtarget since any
483     // creation will depend on the TM and the code generation flags on the
484     // function that reside in TargetOptions.
485     resetTargetOptions(F);
486     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
487   }
488 
489   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
490 
491   return I.get();
492 }
493 
494 TargetTransformInfo
495 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
496   return TargetTransformInfo(GCNTTIImpl(this, F));
497 }
498 
499 //===----------------------------------------------------------------------===//
500 // AMDGPU Pass Setup
501 //===----------------------------------------------------------------------===//
502 
503 namespace {
504 
505 class AMDGPUPassConfig : public TargetPassConfig {
506 public:
507   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
508     : TargetPassConfig(TM, PM) {
509     // Exceptions and StackMaps are not supported, so these passes will never do
510     // anything.
511     disablePass(&StackMapLivenessID);
512     disablePass(&FuncletLayoutID);
513   }
514 
515   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
516     return getTM<AMDGPUTargetMachine>();
517   }
518 
519   ScheduleDAGInstrs *
520   createMachineScheduler(MachineSchedContext *C) const override {
521     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
522     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
523     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
524     return DAG;
525   }
526 
527   void addEarlyCSEOrGVNPass();
528   void addStraightLineScalarOptimizationPasses();
529   void addIRPasses() override;
530   void addCodeGenPrepare() override;
531   bool addPreISel() override;
532   bool addInstSelector() override;
533   bool addGCPasses() override;
534 };
535 
536 class R600PassConfig final : public AMDGPUPassConfig {
537 public:
538   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
539     : AMDGPUPassConfig(TM, PM) {}
540 
541   ScheduleDAGInstrs *createMachineScheduler(
542     MachineSchedContext *C) const override {
543     return createR600MachineScheduler(C);
544   }
545 
546   bool addPreISel() override;
547   bool addInstSelector() override;
548   void addPreRegAlloc() override;
549   void addPreSched2() override;
550   void addPreEmitPass() override;
551 };
552 
553 class GCNPassConfig final : public AMDGPUPassConfig {
554 public:
555   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
556     : AMDGPUPassConfig(TM, PM) {
557     // It is necessary to know the register usage of the entire call graph.  We
558     // allow calls without EnableAMDGPUFunctionCalls if they are marked
559     // noinline, so this is always required.
560     setRequiresCodeGenSCCOrder(true);
561   }
562 
563   GCNTargetMachine &getGCNTargetMachine() const {
564     return getTM<GCNTargetMachine>();
565   }
566 
567   ScheduleDAGInstrs *
568   createMachineScheduler(MachineSchedContext *C) const override;
569 
570   bool addPreISel() override;
571   void addMachineSSAOptimization() override;
572   bool addILPOpts() override;
573   bool addInstSelector() override;
574   bool addIRTranslator() override;
575   bool addLegalizeMachineIR() override;
576   bool addRegBankSelect() override;
577   bool addGlobalInstructionSelect() override;
578   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
579   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
580   void addPreRegAlloc() override;
581   void addPostRegAlloc() override;
582   void addPreSched2() override;
583   void addPreEmitPass() override;
584 };
585 
586 } // end anonymous namespace
587 
588 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
589   if (getOptLevel() == CodeGenOpt::Aggressive)
590     addPass(createGVNPass());
591   else
592     addPass(createEarlyCSEPass());
593 }
594 
595 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
596   addPass(createLICMPass());
597   addPass(createSeparateConstOffsetFromGEPPass());
598   addPass(createSpeculativeExecutionPass());
599   // ReassociateGEPs exposes more opportunites for SLSR. See
600   // the example in reassociate-geps-and-slsr.ll.
601   addPass(createStraightLineStrengthReducePass());
602   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
603   // EarlyCSE can reuse.
604   addEarlyCSEOrGVNPass();
605   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
606   addPass(createNaryReassociatePass());
607   // NaryReassociate on GEPs creates redundant common expressions, so run
608   // EarlyCSE after it.
609   addPass(createEarlyCSEPass());
610 }
611 
612 void AMDGPUPassConfig::addIRPasses() {
613   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
614 
615   // There is no reason to run these.
616   disablePass(&StackMapLivenessID);
617   disablePass(&FuncletLayoutID);
618   disablePass(&PatchableFunctionID);
619 
620   addPass(createAtomicExpandPass());
621 
622   // This must occur before inlining, as the inliner will not look through
623   // bitcast calls.
624   addPass(createAMDGPUFixFunctionBitcastsPass());
625 
626   addPass(createAMDGPULowerIntrinsicsPass());
627 
628   // Function calls are not supported, so make sure we inline everything.
629   addPass(createAMDGPUAlwaysInlinePass());
630   addPass(createAlwaysInlinerLegacyPass());
631   // We need to add the barrier noop pass, otherwise adding the function
632   // inlining pass will cause all of the PassConfigs passes to be run
633   // one function at a time, which means if we have a nodule with two
634   // functions, then we will generate code for the first function
635   // without ever running any passes on the second.
636   addPass(createBarrierNoopPass());
637 
638   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
639     // TODO: May want to move later or split into an early and late one.
640 
641     addPass(createAMDGPUCodeGenPreparePass());
642   }
643 
644   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
645   if (TM.getTargetTriple().getArch() == Triple::r600)
646     addPass(createR600OpenCLImageTypeLoweringPass());
647 
648   // Replace OpenCL enqueued block function pointers with global variables.
649   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
650 
651   if (TM.getOptLevel() > CodeGenOpt::None) {
652     addPass(createInferAddressSpacesPass());
653     addPass(createAMDGPUPromoteAlloca());
654 
655     if (EnableSROA)
656       addPass(createSROAPass());
657 
658     addStraightLineScalarOptimizationPasses();
659 
660     if (EnableAMDGPUAliasAnalysis) {
661       addPass(createAMDGPUAAWrapperPass());
662       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
663                                              AAResults &AAR) {
664         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
665           AAR.addAAResult(WrapperPass->getResult());
666         }));
667     }
668   }
669 
670   TargetPassConfig::addIRPasses();
671 
672   // EarlyCSE is not always strong enough to clean up what LSR produces. For
673   // example, GVN can combine
674   //
675   //   %0 = add %a, %b
676   //   %1 = add %b, %a
677   //
678   // and
679   //
680   //   %0 = shl nsw %a, 2
681   //   %1 = shl %a, 2
682   //
683   // but EarlyCSE can do neither of them.
684   if (getOptLevel() != CodeGenOpt::None)
685     addEarlyCSEOrGVNPass();
686 }
687 
688 void AMDGPUPassConfig::addCodeGenPrepare() {
689   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
690     addPass(createAMDGPUAnnotateKernelFeaturesPass());
691 
692   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
693       EnableLowerKernelArguments)
694     addPass(createAMDGPULowerKernelArgumentsPass());
695 
696   TargetPassConfig::addCodeGenPrepare();
697 
698   if (EnableLoadStoreVectorizer)
699     addPass(createLoadStoreVectorizerPass());
700 }
701 
702 bool AMDGPUPassConfig::addPreISel() {
703   addPass(createLowerSwitchPass());
704   addPass(createFlattenCFGPass());
705   return false;
706 }
707 
708 bool AMDGPUPassConfig::addInstSelector() {
709   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
710   return false;
711 }
712 
713 bool AMDGPUPassConfig::addGCPasses() {
714   // Do nothing. GC is not supported.
715   return false;
716 }
717 
718 //===----------------------------------------------------------------------===//
719 // R600 Pass Setup
720 //===----------------------------------------------------------------------===//
721 
722 bool R600PassConfig::addPreISel() {
723   AMDGPUPassConfig::addPreISel();
724 
725   if (EnableR600StructurizeCFG)
726     addPass(createStructurizeCFGPass());
727   return false;
728 }
729 
730 bool R600PassConfig::addInstSelector() {
731   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
732   return false;
733 }
734 
735 void R600PassConfig::addPreRegAlloc() {
736   addPass(createR600VectorRegMerger());
737 }
738 
739 void R600PassConfig::addPreSched2() {
740   addPass(createR600EmitClauseMarkers(), false);
741   if (EnableR600IfConvert)
742     addPass(&IfConverterID, false);
743   addPass(createR600ClauseMergePass(), false);
744 }
745 
746 void R600PassConfig::addPreEmitPass() {
747   addPass(createAMDGPUCFGStructurizerPass(), false);
748   addPass(createR600ExpandSpecialInstrsPass(), false);
749   addPass(&FinalizeMachineBundlesID, false);
750   addPass(createR600Packetizer(), false);
751   addPass(createR600ControlFlowFinalizer(), false);
752 }
753 
754 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
755   return new R600PassConfig(*this, PM);
756 }
757 
758 //===----------------------------------------------------------------------===//
759 // GCN Pass Setup
760 //===----------------------------------------------------------------------===//
761 
762 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
763   MachineSchedContext *C) const {
764   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
765   if (ST.enableSIScheduler())
766     return createSIMachineScheduler(C);
767   return createGCNMaxOccupancyMachineScheduler(C);
768 }
769 
770 bool GCNPassConfig::addPreISel() {
771   AMDGPUPassConfig::addPreISel();
772 
773   if (EnableAtomicOptimizations) {
774     addPass(createAMDGPUAtomicOptimizerPass());
775   }
776 
777   // FIXME: We need to run a pass to propagate the attributes when calls are
778   // supported.
779 
780   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
781   // regions formed by them.
782   addPass(&AMDGPUUnifyDivergentExitNodesID);
783   if (!LateCFGStructurize) {
784     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
785   }
786   addPass(createSinkingPass());
787   addPass(createAMDGPUAnnotateUniformValues());
788   if (!LateCFGStructurize) {
789     addPass(createSIAnnotateControlFlowPass());
790   }
791 
792   return false;
793 }
794 
795 void GCNPassConfig::addMachineSSAOptimization() {
796   TargetPassConfig::addMachineSSAOptimization();
797 
798   // We want to fold operands after PeepholeOptimizer has run (or as part of
799   // it), because it will eliminate extra copies making it easier to fold the
800   // real source operand. We want to eliminate dead instructions after, so that
801   // we see fewer uses of the copies. We then need to clean up the dead
802   // instructions leftover after the operands are folded as well.
803   //
804   // XXX - Can we get away without running DeadMachineInstructionElim again?
805   addPass(&SIFoldOperandsID);
806   if (EnableDPPCombine)
807     addPass(&GCNDPPCombineID);
808   addPass(&DeadMachineInstructionElimID);
809   addPass(&SILoadStoreOptimizerID);
810   if (EnableSDWAPeephole) {
811     addPass(&SIPeepholeSDWAID);
812     addPass(&EarlyMachineLICMID);
813     addPass(&MachineCSEID);
814     addPass(&SIFoldOperandsID);
815     addPass(&DeadMachineInstructionElimID);
816   }
817   addPass(createSIShrinkInstructionsPass());
818 }
819 
820 bool GCNPassConfig::addILPOpts() {
821   if (EnableEarlyIfConversion)
822     addPass(&EarlyIfConverterID);
823 
824   TargetPassConfig::addILPOpts();
825   return false;
826 }
827 
828 bool GCNPassConfig::addInstSelector() {
829   AMDGPUPassConfig::addInstSelector();
830   addPass(&SIFixSGPRCopiesID);
831   addPass(createSILowerI1CopiesPass());
832   addPass(createSIFixupVectorISelPass());
833   addPass(createSIAddIMGInitPass());
834   return false;
835 }
836 
837 bool GCNPassConfig::addIRTranslator() {
838   addPass(new IRTranslator());
839   return false;
840 }
841 
842 bool GCNPassConfig::addLegalizeMachineIR() {
843   addPass(new Legalizer());
844   return false;
845 }
846 
847 bool GCNPassConfig::addRegBankSelect() {
848   addPass(new RegBankSelect());
849   return false;
850 }
851 
852 bool GCNPassConfig::addGlobalInstructionSelect() {
853   addPass(new InstructionSelect());
854   return false;
855 }
856 
857 void GCNPassConfig::addPreRegAlloc() {
858   if (LateCFGStructurize) {
859     addPass(createAMDGPUMachineCFGStructurizerPass());
860   }
861   addPass(createSIWholeQuadModePass());
862 }
863 
864 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
865   // FIXME: We have to disable the verifier here because of PHIElimination +
866   // TwoAddressInstructions disabling it.
867 
868   // This must be run immediately after phi elimination and before
869   // TwoAddressInstructions, otherwise the processing of the tied operand of
870   // SI_ELSE will introduce a copy of the tied operand source after the else.
871   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
872 
873   // This must be run after SILowerControlFlow, since it needs to use the
874   // machine-level CFG, but before register allocation.
875   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
876 
877   TargetPassConfig::addFastRegAlloc(RegAllocPass);
878 }
879 
880 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
881   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
882 
883   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
884 
885   // This must be run immediately after phi elimination and before
886   // TwoAddressInstructions, otherwise the processing of the tied operand of
887   // SI_ELSE will introduce a copy of the tied operand source after the else.
888   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
889 
890   // This must be run after SILowerControlFlow, since it needs to use the
891   // machine-level CFG, but before register allocation.
892   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
893 
894   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
895 }
896 
897 void GCNPassConfig::addPostRegAlloc() {
898   addPass(&SIFixVGPRCopiesID);
899   if (getOptLevel() > CodeGenOpt::None)
900     addPass(&SIOptimizeExecMaskingID);
901   TargetPassConfig::addPostRegAlloc();
902 }
903 
904 void GCNPassConfig::addPreSched2() {
905 }
906 
907 void GCNPassConfig::addPreEmitPass() {
908   addPass(createSIMemoryLegalizerPass());
909   addPass(createSIInsertWaitcntsPass());
910   addPass(createSIShrinkInstructionsPass());
911   addPass(createSIModeRegisterPass());
912 
913   // The hazard recognizer that runs as part of the post-ra scheduler does not
914   // guarantee to be able handle all hazards correctly. This is because if there
915   // are multiple scheduling regions in a basic block, the regions are scheduled
916   // bottom up, so when we begin to schedule a region we don't know what
917   // instructions were emitted directly before it.
918   //
919   // Here we add a stand-alone hazard recognizer pass which can handle all
920   // cases.
921   //
922   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
923   // be better for it to emit S_NOP <N> when possible.
924   addPass(&PostRAHazardRecognizerID);
925 
926   addPass(&SIInsertSkipsPassID);
927   addPass(&BranchRelaxationPassID);
928 }
929 
930 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
931   return new GCNPassConfig(*this, PM);
932 }
933