1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "TargetInfo/AMDGPUTargetInfo.h"
30 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
31 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
32 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
33 #include "llvm/CodeGen/GlobalISel/Localizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MIRParser/MIParser.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/LegacyPassManager.h"
41 #include "llvm/InitializePasses.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Transforms/IPO.h"
48 #include "llvm/Transforms/IPO/AlwaysInliner.h"
49 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
50 #include "llvm/Transforms/Scalar.h"
51 #include "llvm/Transforms/Scalar/GVN.h"
52 #include "llvm/Transforms/Utils.h"
53 #include "llvm/Transforms/Vectorize.h"
54 #include <memory>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool> EnableR600StructurizeCFG(
59   "r600-ir-structurize",
60   cl::desc("Use StructurizeCFG IR pass"),
61   cl::init(true));
62 
63 static cl::opt<bool> EnableSROA(
64   "amdgpu-sroa",
65   cl::desc("Run SROA after promote alloca pass"),
66   cl::ReallyHidden,
67   cl::init(true));
68 
69 static cl::opt<bool>
70 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
71                         cl::desc("Run early if-conversion"),
72                         cl::init(false));
73 
74 static cl::opt<bool>
75 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
76             cl::desc("Run pre-RA exec mask optimizations"),
77             cl::init(true));
78 
79 static cl::opt<bool> EnableR600IfConvert(
80   "r600-if-convert",
81   cl::desc("Use if conversion pass"),
82   cl::ReallyHidden,
83   cl::init(true));
84 
85 // Option to disable vectorizer for tests.
86 static cl::opt<bool> EnableLoadStoreVectorizer(
87   "amdgpu-load-store-vectorizer",
88   cl::desc("Enable load store vectorizer"),
89   cl::init(true),
90   cl::Hidden);
91 
92 // Option to control global loads scalarization
93 static cl::opt<bool> ScalarizeGlobal(
94   "amdgpu-scalarize-global-loads",
95   cl::desc("Enable global load scalarization"),
96   cl::init(true),
97   cl::Hidden);
98 
99 // Option to run internalize pass.
100 static cl::opt<bool> InternalizeSymbols(
101   "amdgpu-internalize-symbols",
102   cl::desc("Enable elimination of non-kernel functions and unused globals"),
103   cl::init(false),
104   cl::Hidden);
105 
106 // Option to inline all early.
107 static cl::opt<bool> EarlyInlineAll(
108   "amdgpu-early-inline-all",
109   cl::desc("Inline all functions early"),
110   cl::init(false),
111   cl::Hidden);
112 
113 static cl::opt<bool> EnableSDWAPeephole(
114   "amdgpu-sdwa-peephole",
115   cl::desc("Enable SDWA peepholer"),
116   cl::init(true));
117 
118 static cl::opt<bool> EnableDPPCombine(
119   "amdgpu-dpp-combine",
120   cl::desc("Enable DPP combiner"),
121   cl::init(true));
122 
123 // Enable address space based alias analysis
124 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
125   cl::desc("Enable AMDGPU Alias Analysis"),
126   cl::init(true));
127 
128 // Option to run late CFG structurizer
129 static cl::opt<bool, true> LateCFGStructurize(
130   "amdgpu-late-structurize",
131   cl::desc("Enable late CFG structurization"),
132   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
133   cl::Hidden);
134 
135 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
136   "amdgpu-function-calls",
137   cl::desc("Enable AMDGPU function call support"),
138   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
139   cl::init(true),
140   cl::Hidden);
141 
142 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
143   "amdgpu-fixed-function-abi",
144   cl::desc("Enable all implicit function arguments"),
145   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
146   cl::init(false),
147   cl::Hidden);
148 
149 // Enable lib calls simplifications
150 static cl::opt<bool> EnableLibCallSimplify(
151   "amdgpu-simplify-libcall",
152   cl::desc("Enable amdgpu library simplifications"),
153   cl::init(true),
154   cl::Hidden);
155 
156 static cl::opt<bool> EnableLowerKernelArguments(
157   "amdgpu-ir-lower-kernel-arguments",
158   cl::desc("Lower kernel argument loads in IR pass"),
159   cl::init(true),
160   cl::Hidden);
161 
162 static cl::opt<bool> EnableRegReassign(
163   "amdgpu-reassign-regs",
164   cl::desc("Enable register reassign optimizations on gfx10+"),
165   cl::init(true),
166   cl::Hidden);
167 
168 // Enable atomic optimization
169 static cl::opt<bool> EnableAtomicOptimizations(
170   "amdgpu-atomic-optimizations",
171   cl::desc("Enable atomic optimizations"),
172   cl::init(false),
173   cl::Hidden);
174 
175 // Enable Mode register optimization
176 static cl::opt<bool> EnableSIModeRegisterPass(
177   "amdgpu-mode-register",
178   cl::desc("Enable mode register pass"),
179   cl::init(true),
180   cl::Hidden);
181 
182 // Option is used in lit tests to prevent deadcoding of patterns inspected.
183 static cl::opt<bool>
184 EnableDCEInRA("amdgpu-dce-in-ra",
185     cl::init(true), cl::Hidden,
186     cl::desc("Enable machine DCE inside regalloc"));
187 
188 static cl::opt<bool> EnableScalarIRPasses(
189   "amdgpu-scalar-ir-passes",
190   cl::desc("Enable scalar IR passes"),
191   cl::init(true),
192   cl::Hidden);
193 
194 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
195   // Register the target
196   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
197   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
198 
199   PassRegistry *PR = PassRegistry::getPassRegistry();
200   initializeR600ClauseMergePassPass(*PR);
201   initializeR600ControlFlowFinalizerPass(*PR);
202   initializeR600PacketizerPass(*PR);
203   initializeR600ExpandSpecialInstrsPassPass(*PR);
204   initializeR600VectorRegMergerPass(*PR);
205   initializeGlobalISel(*PR);
206   initializeAMDGPUDAGToDAGISelPass(*PR);
207   initializeGCNDPPCombinePass(*PR);
208   initializeSILowerI1CopiesPass(*PR);
209   initializeSILowerSGPRSpillsPass(*PR);
210   initializeSIFixSGPRCopiesPass(*PR);
211   initializeSIFixVGPRCopiesPass(*PR);
212   initializeSIFixupVectorISelPass(*PR);
213   initializeSIFoldOperandsPass(*PR);
214   initializeSIPeepholeSDWAPass(*PR);
215   initializeSIShrinkInstructionsPass(*PR);
216   initializeSIOptimizeExecMaskingPreRAPass(*PR);
217   initializeSILoadStoreOptimizerPass(*PR);
218   initializeAMDGPUFixFunctionBitcastsPass(*PR);
219   initializeAMDGPUAlwaysInlinePass(*PR);
220   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
221   initializeAMDGPUAnnotateUniformValuesPass(*PR);
222   initializeAMDGPUArgumentUsageInfoPass(*PR);
223   initializeAMDGPUAtomicOptimizerPass(*PR);
224   initializeAMDGPULowerKernelArgumentsPass(*PR);
225   initializeAMDGPULowerKernelAttributesPass(*PR);
226   initializeAMDGPULowerIntrinsicsPass(*PR);
227   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
228   initializeAMDGPUPostLegalizerCombinerPass(*PR);
229   initializeAMDGPUPreLegalizerCombinerPass(*PR);
230   initializeAMDGPUPromoteAllocaPass(*PR);
231   initializeAMDGPUCodeGenPreparePass(*PR);
232   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
233   initializeAMDGPUPropagateAttributesLatePass(*PR);
234   initializeAMDGPURewriteOutArgumentsPass(*PR);
235   initializeAMDGPUUnifyMetadataPass(*PR);
236   initializeSIAnnotateControlFlowPass(*PR);
237   initializeSIInsertWaitcntsPass(*PR);
238   initializeSIModeRegisterPass(*PR);
239   initializeSIWholeQuadModePass(*PR);
240   initializeSILowerControlFlowPass(*PR);
241   initializeSIRemoveShortExecBranchesPass(*PR);
242   initializeSIInsertSkipsPass(*PR);
243   initializeSIMemoryLegalizerPass(*PR);
244   initializeSIOptimizeExecMaskingPass(*PR);
245   initializeSIPreAllocateWWMRegsPass(*PR);
246   initializeSIFormMemoryClausesPass(*PR);
247   initializeSIPostRABundlerPass(*PR);
248   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
249   initializeAMDGPUAAWrapperPassPass(*PR);
250   initializeAMDGPUExternalAAWrapperPass(*PR);
251   initializeAMDGPUUseNativeCallsPass(*PR);
252   initializeAMDGPUSimplifyLibCallsPass(*PR);
253   initializeAMDGPUInlinerPass(*PR);
254   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
255   initializeGCNRegBankReassignPass(*PR);
256   initializeGCNNSAReassignPass(*PR);
257   initializeSIAddIMGInitPass(*PR);
258 }
259 
260 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
261   return std::make_unique<AMDGPUTargetObjectFile>();
262 }
263 
264 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
265   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
266 }
267 
268 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
269   return new SIScheduleDAGMI(C);
270 }
271 
272 static ScheduleDAGInstrs *
273 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
274   ScheduleDAGMILive *DAG =
275     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
276   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
277   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
278   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
279   return DAG;
280 }
281 
282 static ScheduleDAGInstrs *
283 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
284   auto DAG = new GCNIterativeScheduler(C,
285     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
288   return DAG;
289 }
290 
291 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
292   return new GCNIterativeScheduler(C,
293     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
294 }
295 
296 static ScheduleDAGInstrs *
297 createIterativeILPMachineScheduler(MachineSchedContext *C) {
298   auto DAG = new GCNIterativeScheduler(C,
299     GCNIterativeScheduler::SCHEDULE_ILP);
300   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
301   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
302   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
303   return DAG;
304 }
305 
306 static MachineSchedRegistry
307 R600SchedRegistry("r600", "Run R600's custom scheduler",
308                    createR600MachineScheduler);
309 
310 static MachineSchedRegistry
311 SISchedRegistry("si", "Run SI's custom scheduler",
312                 createSIMachineScheduler);
313 
314 static MachineSchedRegistry
315 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
316                              "Run GCN scheduler to maximize occupancy",
317                              createGCNMaxOccupancyMachineScheduler);
318 
319 static MachineSchedRegistry
320 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
321   "Run GCN scheduler to maximize occupancy (experimental)",
322   createIterativeGCNMaxOccupancyMachineScheduler);
323 
324 static MachineSchedRegistry
325 GCNMinRegSchedRegistry("gcn-minreg",
326   "Run GCN iterative scheduler for minimal register usage (experimental)",
327   createMinRegScheduler);
328 
329 static MachineSchedRegistry
330 GCNILPSchedRegistry("gcn-ilp",
331   "Run GCN iterative scheduler for ILP scheduling (experimental)",
332   createIterativeILPMachineScheduler);
333 
334 static StringRef computeDataLayout(const Triple &TT) {
335   if (TT.getArch() == Triple::r600) {
336     // 32-bit pointers.
337       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
338              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
339   }
340 
341   // 32-bit private, local, and region pointers. 64-bit global, constant and
342   // flat, non-integral buffer fat pointers.
343     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
344          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
346          "-ni:7";
347 }
348 
349 LLVM_READNONE
350 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
351   if (!GPU.empty())
352     return GPU;
353 
354   // Need to default to a target with flat support for HSA.
355   if (TT.getArch() == Triple::amdgcn)
356     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
357 
358   return "r600";
359 }
360 
361 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
362   // The AMDGPU toolchain only supports generating shared objects, so we
363   // must always use PIC.
364   return Reloc::PIC_;
365 }
366 
367 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
368                                          StringRef CPU, StringRef FS,
369                                          TargetOptions Options,
370                                          Optional<Reloc::Model> RM,
371                                          Optional<CodeModel::Model> CM,
372                                          CodeGenOpt::Level OptLevel)
373     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
374                         FS, Options, getEffectiveRelocModel(RM),
375                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
376       TLOF(createTLOF(getTargetTriple())) {
377   initAsmInfo();
378 }
379 
380 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
381 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
382 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
383 
384 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
385 
386 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
387   Attribute GPUAttr = F.getFnAttribute("target-cpu");
388   return GPUAttr.hasAttribute(Attribute::None) ?
389     getTargetCPU() : GPUAttr.getValueAsString();
390 }
391 
392 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
393   Attribute FSAttr = F.getFnAttribute("target-features");
394 
395   return FSAttr.hasAttribute(Attribute::None) ?
396     getTargetFeatureString() :
397     FSAttr.getValueAsString();
398 }
399 
400 /// Predicate for Internalize pass.
401 static bool mustPreserveGV(const GlobalValue &GV) {
402   if (const Function *F = dyn_cast<Function>(&GV))
403     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
404 
405   return !GV.use_empty();
406 }
407 
408 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
409   Builder.DivergentTarget = true;
410 
411   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
412   bool Internalize = InternalizeSymbols;
413   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
414   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
415   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
416 
417   if (EnableFunctionCalls) {
418     delete Builder.Inliner;
419     Builder.Inliner = createAMDGPUFunctionInliningPass();
420   }
421 
422   Builder.addExtension(
423     PassManagerBuilder::EP_ModuleOptimizerEarly,
424     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
425                                                legacy::PassManagerBase &PM) {
426       if (AMDGPUAA) {
427         PM.add(createAMDGPUAAWrapperPass());
428         PM.add(createAMDGPUExternalAAWrapperPass());
429       }
430       PM.add(createAMDGPUUnifyMetadataPass());
431       PM.add(createAMDGPUPrintfRuntimeBinding());
432       PM.add(createAMDGPUPropagateAttributesLatePass(this));
433       if (Internalize) {
434         PM.add(createInternalizePass(mustPreserveGV));
435         PM.add(createGlobalDCEPass());
436       }
437       if (EarlyInline)
438         PM.add(createAMDGPUAlwaysInlinePass(false));
439   });
440 
441   const auto &Opt = Options;
442   Builder.addExtension(
443     PassManagerBuilder::EP_EarlyAsPossible,
444     [AMDGPUAA, LibCallSimplify, &Opt, this](const PassManagerBuilder &,
445                                             legacy::PassManagerBase &PM) {
446       if (AMDGPUAA) {
447         PM.add(createAMDGPUAAWrapperPass());
448         PM.add(createAMDGPUExternalAAWrapperPass());
449       }
450       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
451       PM.add(llvm::createAMDGPUUseNativeCallsPass());
452       if (LibCallSimplify)
453         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt, this));
454   });
455 
456   Builder.addExtension(
457     PassManagerBuilder::EP_CGSCCOptimizerLate,
458     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
459       // Add infer address spaces pass to the opt pipeline after inlining
460       // but before SROA to increase SROA opportunities.
461       PM.add(createInferAddressSpacesPass());
462 
463       // This should run after inlining to have any chance of doing anything,
464       // and before other cleanup optimizations.
465       PM.add(createAMDGPULowerKernelAttributesPass());
466   });
467 }
468 
469 //===----------------------------------------------------------------------===//
470 // R600 Target Machine (R600 -> Cayman)
471 //===----------------------------------------------------------------------===//
472 
473 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
474                                      StringRef CPU, StringRef FS,
475                                      TargetOptions Options,
476                                      Optional<Reloc::Model> RM,
477                                      Optional<CodeModel::Model> CM,
478                                      CodeGenOpt::Level OL, bool JIT)
479     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
480   setRequiresStructuredCFG(true);
481 
482   // Override the default since calls aren't supported for r600.
483   if (EnableFunctionCalls &&
484       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
485     EnableFunctionCalls = false;
486 }
487 
488 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
489   const Function &F) const {
490   StringRef GPU = getGPUName(F);
491   StringRef FS = getFeatureString(F);
492 
493   SmallString<128> SubtargetKey(GPU);
494   SubtargetKey.append(FS);
495 
496   auto &I = SubtargetMap[SubtargetKey];
497   if (!I) {
498     // This needs to be done before we create a new subtarget since any
499     // creation will depend on the TM and the code generation flags on the
500     // function that reside in TargetOptions.
501     resetTargetOptions(F);
502     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
503   }
504 
505   return I.get();
506 }
507 
508 TargetTransformInfo
509 R600TargetMachine::getTargetTransformInfo(const Function &F) {
510   return TargetTransformInfo(R600TTIImpl(this, F));
511 }
512 
513 //===----------------------------------------------------------------------===//
514 // GCN Target Machine (SI+)
515 //===----------------------------------------------------------------------===//
516 
517 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
518                                    StringRef CPU, StringRef FS,
519                                    TargetOptions Options,
520                                    Optional<Reloc::Model> RM,
521                                    Optional<CodeModel::Model> CM,
522                                    CodeGenOpt::Level OL, bool JIT)
523     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
524 
525 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
526   StringRef GPU = getGPUName(F);
527   StringRef FS = getFeatureString(F);
528 
529   SmallString<128> SubtargetKey(GPU);
530   SubtargetKey.append(FS);
531 
532   auto &I = SubtargetMap[SubtargetKey];
533   if (!I) {
534     // This needs to be done before we create a new subtarget since any
535     // creation will depend on the TM and the code generation flags on the
536     // function that reside in TargetOptions.
537     resetTargetOptions(F);
538     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
539   }
540 
541   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
542 
543   return I.get();
544 }
545 
546 TargetTransformInfo
547 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
548   return TargetTransformInfo(GCNTTIImpl(this, F));
549 }
550 
551 //===----------------------------------------------------------------------===//
552 // AMDGPU Pass Setup
553 //===----------------------------------------------------------------------===//
554 
555 namespace {
556 
557 class AMDGPUPassConfig : public TargetPassConfig {
558 public:
559   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
560     : TargetPassConfig(TM, PM) {
561     // Exceptions and StackMaps are not supported, so these passes will never do
562     // anything.
563     disablePass(&StackMapLivenessID);
564     disablePass(&FuncletLayoutID);
565   }
566 
567   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
568     return getTM<AMDGPUTargetMachine>();
569   }
570 
571   ScheduleDAGInstrs *
572   createMachineScheduler(MachineSchedContext *C) const override {
573     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
574     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
575     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
576     return DAG;
577   }
578 
579   void addEarlyCSEOrGVNPass();
580   void addStraightLineScalarOptimizationPasses();
581   void addIRPasses() override;
582   void addCodeGenPrepare() override;
583   bool addPreISel() override;
584   bool addInstSelector() override;
585   bool addGCPasses() override;
586 
587   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
588 };
589 
590 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
591   return getStandardCSEConfigForOpt(TM->getOptLevel());
592 }
593 
594 class R600PassConfig final : public AMDGPUPassConfig {
595 public:
596   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
597     : AMDGPUPassConfig(TM, PM) {}
598 
599   ScheduleDAGInstrs *createMachineScheduler(
600     MachineSchedContext *C) const override {
601     return createR600MachineScheduler(C);
602   }
603 
604   bool addPreISel() override;
605   bool addInstSelector() override;
606   void addPreRegAlloc() override;
607   void addPreSched2() override;
608   void addPreEmitPass() override;
609 };
610 
611 class GCNPassConfig final : public AMDGPUPassConfig {
612 public:
613   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
614     : AMDGPUPassConfig(TM, PM) {
615     // It is necessary to know the register usage of the entire call graph.  We
616     // allow calls without EnableAMDGPUFunctionCalls if they are marked
617     // noinline, so this is always required.
618     setRequiresCodeGenSCCOrder(true);
619   }
620 
621   GCNTargetMachine &getGCNTargetMachine() const {
622     return getTM<GCNTargetMachine>();
623   }
624 
625   ScheduleDAGInstrs *
626   createMachineScheduler(MachineSchedContext *C) const override;
627 
628   bool addPreISel() override;
629   void addMachineSSAOptimization() override;
630   bool addILPOpts() override;
631   bool addInstSelector() override;
632   bool addIRTranslator() override;
633   void addPreLegalizeMachineIR() override;
634   bool addLegalizeMachineIR() override;
635   void addPreRegBankSelect() override;
636   bool addRegBankSelect() override;
637   bool addGlobalInstructionSelect() override;
638   void addFastRegAlloc() override;
639   void addOptimizedRegAlloc() override;
640   void addPreRegAlloc() override;
641   bool addPreRewrite() override;
642   void addPostRegAlloc() override;
643   void addPreSched2() override;
644   void addPreEmitPass() override;
645 };
646 
647 } // end anonymous namespace
648 
649 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
650   if (getOptLevel() == CodeGenOpt::Aggressive)
651     addPass(createGVNPass());
652   else
653     addPass(createEarlyCSEPass());
654 }
655 
656 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
657   addPass(createLICMPass());
658   addPass(createSeparateConstOffsetFromGEPPass());
659   addPass(createSpeculativeExecutionPass());
660   // ReassociateGEPs exposes more opportunites for SLSR. See
661   // the example in reassociate-geps-and-slsr.ll.
662   addPass(createStraightLineStrengthReducePass());
663   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
664   // EarlyCSE can reuse.
665   addEarlyCSEOrGVNPass();
666   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
667   addPass(createNaryReassociatePass());
668   // NaryReassociate on GEPs creates redundant common expressions, so run
669   // EarlyCSE after it.
670   addPass(createEarlyCSEPass());
671 }
672 
673 void AMDGPUPassConfig::addIRPasses() {
674   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
675 
676   // There is no reason to run these.
677   disablePass(&StackMapLivenessID);
678   disablePass(&FuncletLayoutID);
679   disablePass(&PatchableFunctionID);
680 
681   addPass(createAMDGPUPrintfRuntimeBinding());
682 
683   // This must occur before inlining, as the inliner will not look through
684   // bitcast calls.
685   addPass(createAMDGPUFixFunctionBitcastsPass());
686 
687   // A call to propagate attributes pass in the backend in case opt was not run.
688   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
689 
690   addPass(createAtomicExpandPass());
691 
692 
693   addPass(createAMDGPULowerIntrinsicsPass());
694 
695   // Function calls are not supported, so make sure we inline everything.
696   addPass(createAMDGPUAlwaysInlinePass());
697   addPass(createAlwaysInlinerLegacyPass());
698   // We need to add the barrier noop pass, otherwise adding the function
699   // inlining pass will cause all of the PassConfigs passes to be run
700   // one function at a time, which means if we have a nodule with two
701   // functions, then we will generate code for the first function
702   // without ever running any passes on the second.
703   addPass(createBarrierNoopPass());
704 
705   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
706   if (TM.getTargetTriple().getArch() == Triple::r600)
707     addPass(createR600OpenCLImageTypeLoweringPass());
708 
709   // Replace OpenCL enqueued block function pointers with global variables.
710   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
711 
712   if (TM.getOptLevel() > CodeGenOpt::None) {
713     addPass(createInferAddressSpacesPass());
714     addPass(createAMDGPUPromoteAlloca());
715 
716     if (EnableSROA)
717       addPass(createSROAPass());
718 
719     if (EnableScalarIRPasses)
720       addStraightLineScalarOptimizationPasses();
721 
722     if (EnableAMDGPUAliasAnalysis) {
723       addPass(createAMDGPUAAWrapperPass());
724       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
725                                              AAResults &AAR) {
726         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
727           AAR.addAAResult(WrapperPass->getResult());
728         }));
729     }
730   }
731 
732   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
733     // TODO: May want to move later or split into an early and late one.
734     addPass(createAMDGPUCodeGenPreparePass());
735   }
736 
737   TargetPassConfig::addIRPasses();
738 
739   // EarlyCSE is not always strong enough to clean up what LSR produces. For
740   // example, GVN can combine
741   //
742   //   %0 = add %a, %b
743   //   %1 = add %b, %a
744   //
745   // and
746   //
747   //   %0 = shl nsw %a, 2
748   //   %1 = shl %a, 2
749   //
750   // but EarlyCSE can do neither of them.
751   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
752     addEarlyCSEOrGVNPass();
753 }
754 
755 void AMDGPUPassConfig::addCodeGenPrepare() {
756   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
757     addPass(createAMDGPUAnnotateKernelFeaturesPass());
758 
759   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
760       EnableLowerKernelArguments)
761     addPass(createAMDGPULowerKernelArgumentsPass());
762 
763   addPass(&AMDGPUPerfHintAnalysisID);
764 
765   TargetPassConfig::addCodeGenPrepare();
766 
767   if (EnableLoadStoreVectorizer)
768     addPass(createLoadStoreVectorizerPass());
769 }
770 
771 bool AMDGPUPassConfig::addPreISel() {
772   addPass(createLowerSwitchPass());
773   addPass(createFlattenCFGPass());
774   return false;
775 }
776 
777 bool AMDGPUPassConfig::addInstSelector() {
778   // Defer the verifier until FinalizeISel.
779   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
780   return false;
781 }
782 
783 bool AMDGPUPassConfig::addGCPasses() {
784   // Do nothing. GC is not supported.
785   return false;
786 }
787 
788 //===----------------------------------------------------------------------===//
789 // R600 Pass Setup
790 //===----------------------------------------------------------------------===//
791 
792 bool R600PassConfig::addPreISel() {
793   AMDGPUPassConfig::addPreISel();
794 
795   if (EnableR600StructurizeCFG)
796     addPass(createStructurizeCFGPass());
797   return false;
798 }
799 
800 bool R600PassConfig::addInstSelector() {
801   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
802   return false;
803 }
804 
805 void R600PassConfig::addPreRegAlloc() {
806   addPass(createR600VectorRegMerger());
807 }
808 
809 void R600PassConfig::addPreSched2() {
810   addPass(createR600EmitClauseMarkers(), false);
811   if (EnableR600IfConvert)
812     addPass(&IfConverterID, false);
813   addPass(createR600ClauseMergePass(), false);
814 }
815 
816 void R600PassConfig::addPreEmitPass() {
817   addPass(createAMDGPUCFGStructurizerPass(), false);
818   addPass(createR600ExpandSpecialInstrsPass(), false);
819   addPass(&FinalizeMachineBundlesID, false);
820   addPass(createR600Packetizer(), false);
821   addPass(createR600ControlFlowFinalizer(), false);
822 }
823 
824 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
825   return new R600PassConfig(*this, PM);
826 }
827 
828 //===----------------------------------------------------------------------===//
829 // GCN Pass Setup
830 //===----------------------------------------------------------------------===//
831 
832 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
833   MachineSchedContext *C) const {
834   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
835   if (ST.enableSIScheduler())
836     return createSIMachineScheduler(C);
837   return createGCNMaxOccupancyMachineScheduler(C);
838 }
839 
840 bool GCNPassConfig::addPreISel() {
841   AMDGPUPassConfig::addPreISel();
842 
843   if (EnableAtomicOptimizations) {
844     addPass(createAMDGPUAtomicOptimizerPass());
845   }
846 
847   // FIXME: We need to run a pass to propagate the attributes when calls are
848   // supported.
849 
850   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
851   // regions formed by them.
852   addPass(&AMDGPUUnifyDivergentExitNodesID);
853   if (!LateCFGStructurize) {
854     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
855   }
856   addPass(createSinkingPass());
857   addPass(createAMDGPUAnnotateUniformValues());
858   if (!LateCFGStructurize) {
859     addPass(createSIAnnotateControlFlowPass());
860   }
861   addPass(createLCSSAPass());
862 
863   return false;
864 }
865 
866 void GCNPassConfig::addMachineSSAOptimization() {
867   TargetPassConfig::addMachineSSAOptimization();
868 
869   // We want to fold operands after PeepholeOptimizer has run (or as part of
870   // it), because it will eliminate extra copies making it easier to fold the
871   // real source operand. We want to eliminate dead instructions after, so that
872   // we see fewer uses of the copies. We then need to clean up the dead
873   // instructions leftover after the operands are folded as well.
874   //
875   // XXX - Can we get away without running DeadMachineInstructionElim again?
876   addPass(&SIFoldOperandsID);
877   if (EnableDPPCombine)
878     addPass(&GCNDPPCombineID);
879   addPass(&DeadMachineInstructionElimID);
880   addPass(&SILoadStoreOptimizerID);
881   if (EnableSDWAPeephole) {
882     addPass(&SIPeepholeSDWAID);
883     addPass(&EarlyMachineLICMID);
884     addPass(&MachineCSEID);
885     addPass(&SIFoldOperandsID);
886     addPass(&DeadMachineInstructionElimID);
887   }
888   addPass(createSIShrinkInstructionsPass());
889 }
890 
891 bool GCNPassConfig::addILPOpts() {
892   if (EnableEarlyIfConversion)
893     addPass(&EarlyIfConverterID);
894 
895   TargetPassConfig::addILPOpts();
896   return false;
897 }
898 
899 bool GCNPassConfig::addInstSelector() {
900   AMDGPUPassConfig::addInstSelector();
901   addPass(&SIFixSGPRCopiesID);
902   addPass(createSILowerI1CopiesPass());
903   addPass(createSIFixupVectorISelPass());
904   addPass(createSIAddIMGInitPass());
905   return false;
906 }
907 
908 bool GCNPassConfig::addIRTranslator() {
909   addPass(new IRTranslator());
910   return false;
911 }
912 
913 void GCNPassConfig::addPreLegalizeMachineIR() {
914   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
915   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
916   addPass(new Localizer());
917 }
918 
919 bool GCNPassConfig::addLegalizeMachineIR() {
920   addPass(new Legalizer());
921   return false;
922 }
923 
924 void GCNPassConfig::addPreRegBankSelect() {
925   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
926   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
927 }
928 
929 bool GCNPassConfig::addRegBankSelect() {
930   addPass(new RegBankSelect());
931   return false;
932 }
933 
934 bool GCNPassConfig::addGlobalInstructionSelect() {
935   addPass(new InstructionSelect());
936   return false;
937 }
938 
939 void GCNPassConfig::addPreRegAlloc() {
940   if (LateCFGStructurize) {
941     addPass(createAMDGPUMachineCFGStructurizerPass());
942   }
943   addPass(createSIWholeQuadModePass());
944 }
945 
946 void GCNPassConfig::addFastRegAlloc() {
947   // FIXME: We have to disable the verifier here because of PHIElimination +
948   // TwoAddressInstructions disabling it.
949 
950   // This must be run immediately after phi elimination and before
951   // TwoAddressInstructions, otherwise the processing of the tied operand of
952   // SI_ELSE will introduce a copy of the tied operand source after the else.
953   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
954 
955   // This must be run just after RegisterCoalescing.
956   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
957 
958   TargetPassConfig::addFastRegAlloc();
959 }
960 
961 void GCNPassConfig::addOptimizedRegAlloc() {
962   if (OptExecMaskPreRA) {
963     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
964     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
965   } else {
966     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
967   }
968 
969   // This must be run immediately after phi elimination and before
970   // TwoAddressInstructions, otherwise the processing of the tied operand of
971   // SI_ELSE will introduce a copy of the tied operand source after the else.
972   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
973 
974   // This must be run just after RegisterCoalescing.
975   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
976 
977   if (EnableDCEInRA)
978     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
979 
980   TargetPassConfig::addOptimizedRegAlloc();
981 }
982 
983 bool GCNPassConfig::addPreRewrite() {
984   if (EnableRegReassign) {
985     addPass(&GCNNSAReassignID);
986     addPass(&GCNRegBankReassignID);
987   }
988   return true;
989 }
990 
991 void GCNPassConfig::addPostRegAlloc() {
992   addPass(&SIFixVGPRCopiesID);
993   if (getOptLevel() > CodeGenOpt::None)
994     addPass(&SIOptimizeExecMaskingID);
995   TargetPassConfig::addPostRegAlloc();
996 
997   // Equivalent of PEI for SGPRs.
998   addPass(&SILowerSGPRSpillsID);
999 }
1000 
1001 void GCNPassConfig::addPreSched2() {
1002   addPass(&SIPostRABundlerID);
1003 }
1004 
1005 void GCNPassConfig::addPreEmitPass() {
1006   addPass(createSIMemoryLegalizerPass());
1007   addPass(createSIInsertWaitcntsPass());
1008   addPass(createSIShrinkInstructionsPass());
1009   addPass(createSIModeRegisterPass());
1010 
1011   // The hazard recognizer that runs as part of the post-ra scheduler does not
1012   // guarantee to be able handle all hazards correctly. This is because if there
1013   // are multiple scheduling regions in a basic block, the regions are scheduled
1014   // bottom up, so when we begin to schedule a region we don't know what
1015   // instructions were emitted directly before it.
1016   //
1017   // Here we add a stand-alone hazard recognizer pass which can handle all
1018   // cases.
1019   //
1020   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1021   // be better for it to emit S_NOP <N> when possible.
1022   addPass(&PostRAHazardRecognizerID);
1023 
1024   addPass(&SIRemoveShortExecBranchesID);
1025   addPass(&SIInsertSkipsPassID);
1026   addPass(&BranchRelaxationPassID);
1027 }
1028 
1029 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1030   return new GCNPassConfig(*this, PM);
1031 }
1032 
1033 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1034   return new yaml::SIMachineFunctionInfo();
1035 }
1036 
1037 yaml::MachineFunctionInfo *
1038 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1039   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1040   return new yaml::SIMachineFunctionInfo(*MFI,
1041                                          *MF.getSubtarget().getRegisterInfo());
1042 }
1043 
1044 bool GCNTargetMachine::parseMachineFunctionInfo(
1045     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1046     SMDiagnostic &Error, SMRange &SourceRange) const {
1047   const yaml::SIMachineFunctionInfo &YamlMFI =
1048       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1049   MachineFunction &MF = PFS.MF;
1050   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1051 
1052   MFI->initializeBaseYamlFields(YamlMFI);
1053 
1054   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1055     // FIXME: Update parseNamedRegsiterReference to take a Register.
1056     unsigned TempReg;
1057     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1058       SourceRange = RegName.SourceRange;
1059       return true;
1060     }
1061     RegVal = TempReg;
1062 
1063     return false;
1064   };
1065 
1066   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1067     // Create a diagnostic for a the register string literal.
1068     const MemoryBuffer &Buffer =
1069         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1070     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1071                          RegName.Value.size(), SourceMgr::DK_Error,
1072                          "incorrect register class for field", RegName.Value,
1073                          None, None);
1074     SourceRange = RegName.SourceRange;
1075     return true;
1076   };
1077 
1078   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1079       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1080       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1081     return true;
1082 
1083   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1084       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1085     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1086   }
1087 
1088   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1089       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1090     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1091   }
1092 
1093   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1094       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1095     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1096   }
1097 
1098   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1099                                    const TargetRegisterClass &RC,
1100                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1101                                    unsigned SystemSGPRs) {
1102     // Skip parsing if it's not present.
1103     if (!A)
1104       return false;
1105 
1106     if (A->IsRegister) {
1107       unsigned Reg;
1108       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1109         SourceRange = A->RegisterName.SourceRange;
1110         return true;
1111       }
1112       if (!RC.contains(Reg))
1113         return diagnoseRegisterClass(A->RegisterName);
1114       Arg = ArgDescriptor::createRegister(Reg);
1115     } else
1116       Arg = ArgDescriptor::createStack(A->StackOffset);
1117     // Check and apply the optional mask.
1118     if (A->Mask)
1119       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1120 
1121     MFI->NumUserSGPRs += UserSGPRs;
1122     MFI->NumSystemSGPRs += SystemSGPRs;
1123     return false;
1124   };
1125 
1126   if (YamlMFI.ArgInfo &&
1127       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1128                              AMDGPU::SGPR_128RegClass,
1129                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1130        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1131                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1132                              2, 0) ||
1133        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1134                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1135        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1136                              AMDGPU::SReg_64RegClass,
1137                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1138        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1139                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1140                              2, 0) ||
1141        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1142                              AMDGPU::SReg_64RegClass,
1143                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1144        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1145                              AMDGPU::SGPR_32RegClass,
1146                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1147        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1148                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1149                              0, 1) ||
1150        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1151                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1152                              0, 1) ||
1153        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1154                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1155                              0, 1) ||
1156        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1157                              AMDGPU::SGPR_32RegClass,
1158                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1159        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1160                              AMDGPU::SGPR_32RegClass,
1161                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1162        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1163                              AMDGPU::SReg_64RegClass,
1164                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1165        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1166                              AMDGPU::SReg_64RegClass,
1167                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1168        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1169                              AMDGPU::VGPR_32RegClass,
1170                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1171        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1172                              AMDGPU::VGPR_32RegClass,
1173                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1174        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1175                              AMDGPU::VGPR_32RegClass,
1176                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1177     return true;
1178 
1179   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1180   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1181   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1182   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1183   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1184   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1185 
1186   return false;
1187 }
1188