1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #ifdef LLVM_BUILD_GLOBAL_ISEL
23 #include "AMDGPURegisterBankInfo.h"
24 #endif
25 #include "AMDGPUTargetObjectFile.h"
26 #include "AMDGPUTargetTransformInfo.h"
27 #include "GCNIterativeScheduler.h"
28 #include "GCNSchedStrategy.h"
29 #include "R600MachineScheduler.h"
30 #include "SIMachineScheduler.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/LegacyPassManager.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Target/TargetLoweringObjectFile.h"
45 #include "llvm/Transforms/IPO.h"
46 #include "llvm/Transforms/IPO/AlwaysInliner.h"
47 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
48 #include "llvm/Transforms/Scalar.h"
49 #include "llvm/Transforms/Scalar/GVN.h"
50 #include "llvm/Transforms/Vectorize.h"
51 #include <memory>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool> EnableR600IfConvert(
72   "r600-if-convert",
73   cl::desc("Use if conversion pass"),
74   cl::ReallyHidden,
75   cl::init(true));
76 
77 // Option to disable vectorizer for tests.
78 static cl::opt<bool> EnableLoadStoreVectorizer(
79   "amdgpu-load-store-vectorizer",
80   cl::desc("Enable load store vectorizer"),
81   cl::init(true),
82   cl::Hidden);
83 
84 // Option to to control global loads scalarization
85 static cl::opt<bool> ScalarizeGlobal(
86   "amdgpu-scalarize-global-loads",
87   cl::desc("Enable global load scalarization"),
88   cl::init(false),
89   cl::Hidden);
90 
91 // Option to run internalize pass.
92 static cl::opt<bool> InternalizeSymbols(
93   "amdgpu-internalize-symbols",
94   cl::desc("Enable elimination of non-kernel functions and unused globals"),
95   cl::init(false),
96   cl::Hidden);
97 
98 // Option to inline all early.
99 static cl::opt<bool> EarlyInlineAll(
100   "amdgpu-early-inline-all",
101   cl::desc("Inline all functions early"),
102   cl::init(false),
103   cl::Hidden);
104 
105 static cl::opt<bool> EnableSDWAPeephole(
106   "amdgpu-sdwa-peephole",
107   cl::desc("Enable SDWA peepholer"),
108   cl::init(true));
109 
110 // Enable address space based alias analysis
111 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
112   cl::desc("Enable AMDGPU Alias Analysis"),
113   cl::init(true));
114 
115 // Option to enable new waitcnt insertion pass.
116 static cl::opt<bool> EnableSIInsertWaitcntsPass(
117   "enable-si-insert-waitcnts",
118   cl::desc("Use new waitcnt insertion pass"),
119   cl::init(true));
120 
121 // Option to run late CFG structurizer
122 static cl::opt<bool> LateCFGStructurize(
123   "amdgpu-late-structurize",
124   cl::desc("Enable late CFG structurization"),
125   cl::init(false),
126   cl::Hidden);
127 
128 extern "C" void LLVMInitializeAMDGPUTarget() {
129   // Register the target
130   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
131   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
132 
133   PassRegistry *PR = PassRegistry::getPassRegistry();
134   initializeSILowerI1CopiesPass(*PR);
135   initializeSIFixSGPRCopiesPass(*PR);
136   initializeSIFixVGPRCopiesPass(*PR);
137   initializeSIFoldOperandsPass(*PR);
138   initializeSIPeepholeSDWAPass(*PR);
139   initializeSIShrinkInstructionsPass(*PR);
140   initializeSIFixControlFlowLiveIntervalsPass(*PR);
141   initializeSILoadStoreOptimizerPass(*PR);
142   initializeAMDGPUAlwaysInlinePass(*PR);
143   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
144   initializeAMDGPUAnnotateUniformValuesPass(*PR);
145   initializeAMDGPULowerIntrinsicsPass(*PR);
146   initializeAMDGPUPromoteAllocaPass(*PR);
147   initializeAMDGPUCodeGenPreparePass(*PR);
148   initializeAMDGPUUnifyMetadataPass(*PR);
149   initializeSIAnnotateControlFlowPass(*PR);
150   initializeSIInsertWaitsPass(*PR);
151   initializeSIInsertWaitcntsPass(*PR);
152   initializeSIWholeQuadModePass(*PR);
153   initializeSILowerControlFlowPass(*PR);
154   initializeSIInsertSkipsPass(*PR);
155   initializeSIDebuggerInsertNopsPass(*PR);
156   initializeSIOptimizeExecMaskingPass(*PR);
157   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
158   initializeAMDGPUAAWrapperPassPass(*PR);
159 }
160 
161 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
162   return llvm::make_unique<AMDGPUTargetObjectFile>();
163 }
164 
165 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
166   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
167 }
168 
169 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
170   return new SIScheduleDAGMI(C);
171 }
172 
173 static ScheduleDAGInstrs *
174 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
175   ScheduleDAGMILive *DAG =
176     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
177   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
178   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
179   return DAG;
180 }
181 
182 static ScheduleDAGInstrs *
183 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
184   auto DAG = new GCNIterativeScheduler(C,
185     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
186   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
187   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
188   return DAG;
189 }
190 
191 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
192   return new GCNIterativeScheduler(C,
193     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
194 }
195 
196 static MachineSchedRegistry
197 R600SchedRegistry("r600", "Run R600's custom scheduler",
198                    createR600MachineScheduler);
199 
200 static MachineSchedRegistry
201 SISchedRegistry("si", "Run SI's custom scheduler",
202                 createSIMachineScheduler);
203 
204 static MachineSchedRegistry
205 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
206                              "Run GCN scheduler to maximize occupancy",
207                              createGCNMaxOccupancyMachineScheduler);
208 
209 static MachineSchedRegistry
210 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
211   "Run GCN scheduler to maximize occupancy (experimental)",
212   createIterativeGCNMaxOccupancyMachineScheduler);
213 
214 static MachineSchedRegistry
215 GCNMinRegSchedRegistry("gcn-minreg",
216   "Run GCN iterative scheduler for minimal register usage (experimental)",
217   createMinRegScheduler);
218 
219 static StringRef computeDataLayout(const Triple &TT) {
220   if (TT.getArch() == Triple::r600) {
221     // 32-bit pointers.
222     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
223             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
224   }
225 
226   // 32-bit private, local, and region pointers. 64-bit global, constant and
227   // flat.
228   if (TT.getEnvironmentName() == "amdgiz" ||
229       TT.getEnvironmentName() == "amdgizcl")
230     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
231          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
232          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
233   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
234       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
235       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
236 }
237 
238 LLVM_READNONE
239 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
240   if (!GPU.empty())
241     return GPU;
242 
243   // HSA only supports CI+, so change the default GPU to a CI for HSA.
244   if (TT.getArch() == Triple::amdgcn)
245     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
246 
247   return "r600";
248 }
249 
250 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
251   // The AMDGPU toolchain only supports generating shared objects, so we
252   // must always use PIC.
253   return Reloc::PIC_;
254 }
255 
256 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
257                                          StringRef CPU, StringRef FS,
258                                          TargetOptions Options,
259                                          Optional<Reloc::Model> RM,
260                                          CodeModel::Model CM,
261                                          CodeGenOpt::Level OptLevel)
262   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
263                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
264     TLOF(createTLOF(getTargetTriple())) {
265   AS = AMDGPU::getAMDGPUAS(TT);
266   initAsmInfo();
267 }
268 
269 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
270 
271 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
272   Attribute GPUAttr = F.getFnAttribute("target-cpu");
273   return GPUAttr.hasAttribute(Attribute::None) ?
274     getTargetCPU() : GPUAttr.getValueAsString();
275 }
276 
277 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
278   Attribute FSAttr = F.getFnAttribute("target-features");
279 
280   return FSAttr.hasAttribute(Attribute::None) ?
281     getTargetFeatureString() :
282     FSAttr.getValueAsString();
283 }
284 
285 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
286   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
287       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
288         AAR.addAAResult(WrapperPass->getResult());
289       });
290 }
291 
292 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
293   Builder.DivergentTarget = true;
294 
295   bool Internalize = InternalizeSymbols &&
296                      (getOptLevel() > CodeGenOpt::None) &&
297                      (getTargetTriple().getArch() == Triple::amdgcn);
298   bool EarlyInline = EarlyInlineAll &&
299                      (getOptLevel() > CodeGenOpt::None);
300   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && getOptLevel() > CodeGenOpt::None;
301 
302   Builder.addExtension(
303     PassManagerBuilder::EP_ModuleOptimizerEarly,
304     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
305                                          legacy::PassManagerBase &PM) {
306       if (AMDGPUAA) {
307         PM.add(createAMDGPUAAWrapperPass());
308         PM.add(createAMDGPUExternalAAWrapperPass());
309       }
310       PM.add(createAMDGPUUnifyMetadataPass());
311       if (Internalize) {
312         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
313           if (const Function *F = dyn_cast<Function>(&GV)) {
314             if (F->isDeclaration())
315                 return true;
316             switch (F->getCallingConv()) {
317             default:
318               return false;
319             case CallingConv::AMDGPU_VS:
320             case CallingConv::AMDGPU_HS:
321             case CallingConv::AMDGPU_GS:
322             case CallingConv::AMDGPU_PS:
323             case CallingConv::AMDGPU_CS:
324             case CallingConv::AMDGPU_KERNEL:
325             case CallingConv::SPIR_KERNEL:
326               return true;
327             }
328           }
329           return !GV.use_empty();
330         }));
331         PM.add(createGlobalDCEPass());
332       }
333       if (EarlyInline)
334         PM.add(createAMDGPUAlwaysInlinePass(false));
335   });
336 
337   Builder.addExtension(
338     PassManagerBuilder::EP_EarlyAsPossible,
339     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
340       if (AMDGPUAA) {
341         PM.add(createAMDGPUAAWrapperPass());
342         PM.add(createAMDGPUExternalAAWrapperPass());
343       }
344   });
345 }
346 
347 //===----------------------------------------------------------------------===//
348 // R600 Target Machine (R600 -> Cayman)
349 //===----------------------------------------------------------------------===//
350 
351 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
352                                      StringRef CPU, StringRef FS,
353                                      TargetOptions Options,
354                                      Optional<Reloc::Model> RM,
355                                      CodeModel::Model CM, CodeGenOpt::Level OL)
356   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
357   setRequiresStructuredCFG(true);
358 }
359 
360 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
361   const Function &F) const {
362   StringRef GPU = getGPUName(F);
363   StringRef FS = getFeatureString(F);
364 
365   SmallString<128> SubtargetKey(GPU);
366   SubtargetKey.append(FS);
367 
368   auto &I = SubtargetMap[SubtargetKey];
369   if (!I) {
370     // This needs to be done before we create a new subtarget since any
371     // creation will depend on the TM and the code generation flags on the
372     // function that reside in TargetOptions.
373     resetTargetOptions(F);
374     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
375   }
376 
377   return I.get();
378 }
379 
380 //===----------------------------------------------------------------------===//
381 // GCN Target Machine (SI+)
382 //===----------------------------------------------------------------------===//
383 
384 #ifdef LLVM_BUILD_GLOBAL_ISEL
385 namespace {
386 
387 struct SIGISelActualAccessor : public GISelAccessor {
388   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
389   std::unique_ptr<InstructionSelector> InstSelector;
390   std::unique_ptr<LegalizerInfo> Legalizer;
391   std::unique_ptr<RegisterBankInfo> RegBankInfo;
392   const AMDGPUCallLowering *getCallLowering() const override {
393     return CallLoweringInfo.get();
394   }
395   const InstructionSelector *getInstructionSelector() const override {
396     return InstSelector.get();
397   }
398   const LegalizerInfo *getLegalizerInfo() const override {
399     return Legalizer.get();
400   }
401   const RegisterBankInfo *getRegBankInfo() const override {
402     return RegBankInfo.get();
403   }
404 };
405 
406 } // end anonymous namespace
407 #endif
408 
409 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
410                                    StringRef CPU, StringRef FS,
411                                    TargetOptions Options,
412                                    Optional<Reloc::Model> RM,
413                                    CodeModel::Model CM, CodeGenOpt::Level OL)
414   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
415 
416 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
417   StringRef GPU = getGPUName(F);
418   StringRef FS = getFeatureString(F);
419 
420   SmallString<128> SubtargetKey(GPU);
421   SubtargetKey.append(FS);
422 
423   auto &I = SubtargetMap[SubtargetKey];
424   if (!I) {
425     // This needs to be done before we create a new subtarget since any
426     // creation will depend on the TM and the code generation flags on the
427     // function that reside in TargetOptions.
428     resetTargetOptions(F);
429     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
430 
431 #ifndef LLVM_BUILD_GLOBAL_ISEL
432     GISelAccessor *GISel = new GISelAccessor();
433 #else
434     SIGISelActualAccessor *GISel = new SIGISelActualAccessor();
435     GISel->CallLoweringInfo.reset(
436       new AMDGPUCallLowering(*I->getTargetLowering()));
437     GISel->Legalizer.reset(new AMDGPULegalizerInfo());
438 
439     GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*I->getRegisterInfo()));
440     GISel->InstSelector.reset(new AMDGPUInstructionSelector(*I,
441 				*static_cast<AMDGPURegisterBankInfo*>(GISel->RegBankInfo.get())));
442 #endif
443 
444     I->setGISelAccessor(*GISel);
445   }
446 
447   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
448 
449   return I.get();
450 }
451 
452 //===----------------------------------------------------------------------===//
453 // AMDGPU Pass Setup
454 //===----------------------------------------------------------------------===//
455 
456 namespace {
457 
458 class AMDGPUPassConfig : public TargetPassConfig {
459 public:
460   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
461     : TargetPassConfig(TM, PM) {
462     // Exceptions and StackMaps are not supported, so these passes will never do
463     // anything.
464     disablePass(&StackMapLivenessID);
465     disablePass(&FuncletLayoutID);
466   }
467 
468   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
469     return getTM<AMDGPUTargetMachine>();
470   }
471 
472   ScheduleDAGInstrs *
473   createMachineScheduler(MachineSchedContext *C) const override {
474     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
475     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
476     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
477     return DAG;
478   }
479 
480   void addEarlyCSEOrGVNPass();
481   void addStraightLineScalarOptimizationPasses();
482   void addIRPasses() override;
483   void addCodeGenPrepare() override;
484   bool addPreISel() override;
485   bool addInstSelector() override;
486   bool addGCPasses() override;
487 };
488 
489 class R600PassConfig final : public AMDGPUPassConfig {
490 public:
491   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
492     : AMDGPUPassConfig(TM, PM) {}
493 
494   ScheduleDAGInstrs *createMachineScheduler(
495     MachineSchedContext *C) const override {
496     return createR600MachineScheduler(C);
497   }
498 
499   bool addPreISel() override;
500   void addPreRegAlloc() override;
501   void addPreSched2() override;
502   void addPreEmitPass() override;
503 };
504 
505 class GCNPassConfig final : public AMDGPUPassConfig {
506 public:
507   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
508     : AMDGPUPassConfig(TM, PM) {}
509 
510   GCNTargetMachine &getGCNTargetMachine() const {
511     return getTM<GCNTargetMachine>();
512   }
513 
514   ScheduleDAGInstrs *
515   createMachineScheduler(MachineSchedContext *C) const override;
516 
517   bool addPreISel() override;
518   void addMachineSSAOptimization() override;
519   bool addILPOpts() override;
520   bool addInstSelector() override;
521 #ifdef LLVM_BUILD_GLOBAL_ISEL
522   bool addIRTranslator() override;
523   bool addLegalizeMachineIR() override;
524   bool addRegBankSelect() override;
525   bool addGlobalInstructionSelect() override;
526 #endif
527   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
528   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
529   void addPreRegAlloc() override;
530   void addPostRegAlloc() override;
531   void addPreSched2() override;
532   void addPreEmitPass() override;
533 };
534 
535 } // end anonymous namespace
536 
537 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
538   return TargetIRAnalysis([this](const Function &F) {
539     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
540   });
541 }
542 
543 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
544   if (getOptLevel() == CodeGenOpt::Aggressive)
545     addPass(createGVNPass());
546   else
547     addPass(createEarlyCSEPass());
548 }
549 
550 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
551   addPass(createSeparateConstOffsetFromGEPPass());
552   addPass(createSpeculativeExecutionPass());
553   // ReassociateGEPs exposes more opportunites for SLSR. See
554   // the example in reassociate-geps-and-slsr.ll.
555   addPass(createStraightLineStrengthReducePass());
556   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
557   // EarlyCSE can reuse.
558   addEarlyCSEOrGVNPass();
559   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
560   addPass(createNaryReassociatePass());
561   // NaryReassociate on GEPs creates redundant common expressions, so run
562   // EarlyCSE after it.
563   addPass(createEarlyCSEPass());
564 }
565 
566 void AMDGPUPassConfig::addIRPasses() {
567   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
568 
569   // There is no reason to run these.
570   disablePass(&StackMapLivenessID);
571   disablePass(&FuncletLayoutID);
572   disablePass(&PatchableFunctionID);
573 
574   addPass(createAMDGPULowerIntrinsicsPass());
575 
576   // Function calls are not supported, so make sure we inline everything.
577   addPass(createAMDGPUAlwaysInlinePass());
578   addPass(createAlwaysInlinerLegacyPass());
579   // We need to add the barrier noop pass, otherwise adding the function
580   // inlining pass will cause all of the PassConfigs passes to be run
581   // one function at a time, which means if we have a nodule with two
582   // functions, then we will generate code for the first function
583   // without ever running any passes on the second.
584   addPass(createBarrierNoopPass());
585 
586   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
587     // TODO: May want to move later or split into an early and late one.
588 
589     addPass(createAMDGPUCodeGenPreparePass());
590   }
591 
592   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
593   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
594 
595   if (TM.getOptLevel() > CodeGenOpt::None) {
596     addPass(createInferAddressSpacesPass());
597     addPass(createAMDGPUPromoteAlloca());
598 
599     if (EnableSROA)
600       addPass(createSROAPass());
601 
602     addStraightLineScalarOptimizationPasses();
603 
604     if (EnableAMDGPUAliasAnalysis) {
605       addPass(createAMDGPUAAWrapperPass());
606       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
607                                              AAResults &AAR) {
608         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
609           AAR.addAAResult(WrapperPass->getResult());
610         }));
611     }
612   }
613 
614   TargetPassConfig::addIRPasses();
615 
616   // EarlyCSE is not always strong enough to clean up what LSR produces. For
617   // example, GVN can combine
618   //
619   //   %0 = add %a, %b
620   //   %1 = add %b, %a
621   //
622   // and
623   //
624   //   %0 = shl nsw %a, 2
625   //   %1 = shl %a, 2
626   //
627   // but EarlyCSE can do neither of them.
628   if (getOptLevel() != CodeGenOpt::None)
629     addEarlyCSEOrGVNPass();
630 }
631 
632 void AMDGPUPassConfig::addCodeGenPrepare() {
633   TargetPassConfig::addCodeGenPrepare();
634 
635   if (EnableLoadStoreVectorizer)
636     addPass(createLoadStoreVectorizerPass());
637 }
638 
639 bool AMDGPUPassConfig::addPreISel() {
640   addPass(createFlattenCFGPass());
641   return false;
642 }
643 
644 bool AMDGPUPassConfig::addInstSelector() {
645   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
646   return false;
647 }
648 
649 bool AMDGPUPassConfig::addGCPasses() {
650   // Do nothing. GC is not supported.
651   return false;
652 }
653 
654 //===----------------------------------------------------------------------===//
655 // R600 Pass Setup
656 //===----------------------------------------------------------------------===//
657 
658 bool R600PassConfig::addPreISel() {
659   AMDGPUPassConfig::addPreISel();
660 
661   if (EnableR600StructurizeCFG)
662     addPass(createStructurizeCFGPass());
663   return false;
664 }
665 
666 void R600PassConfig::addPreRegAlloc() {
667   addPass(createR600VectorRegMerger());
668 }
669 
670 void R600PassConfig::addPreSched2() {
671   addPass(createR600EmitClauseMarkers(), false);
672   if (EnableR600IfConvert)
673     addPass(&IfConverterID, false);
674   addPass(createR600ClauseMergePass(), false);
675 }
676 
677 void R600PassConfig::addPreEmitPass() {
678   addPass(createAMDGPUCFGStructurizerPass(), false);
679   addPass(createR600ExpandSpecialInstrsPass(), false);
680   addPass(&FinalizeMachineBundlesID, false);
681   addPass(createR600Packetizer(), false);
682   addPass(createR600ControlFlowFinalizer(), false);
683 }
684 
685 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
686   return new R600PassConfig(*this, PM);
687 }
688 
689 //===----------------------------------------------------------------------===//
690 // GCN Pass Setup
691 //===----------------------------------------------------------------------===//
692 
693 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
694   MachineSchedContext *C) const {
695   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
696   if (ST.enableSIScheduler())
697     return createSIMachineScheduler(C);
698   return createGCNMaxOccupancyMachineScheduler(C);
699 }
700 
701 bool GCNPassConfig::addPreISel() {
702   AMDGPUPassConfig::addPreISel();
703 
704   // FIXME: We need to run a pass to propagate the attributes when calls are
705   // supported.
706   addPass(createAMDGPUAnnotateKernelFeaturesPass());
707 
708   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
709   // regions formed by them.
710   addPass(&AMDGPUUnifyDivergentExitNodesID);
711   if (!LateCFGStructurize) {
712     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
713   }
714   addPass(createSinkingPass());
715   addPass(createSITypeRewriter());
716   addPass(createAMDGPUAnnotateUniformValues());
717   if (!LateCFGStructurize) {
718     addPass(createSIAnnotateControlFlowPass());
719   }
720 
721   return false;
722 }
723 
724 void GCNPassConfig::addMachineSSAOptimization() {
725   TargetPassConfig::addMachineSSAOptimization();
726 
727   // We want to fold operands after PeepholeOptimizer has run (or as part of
728   // it), because it will eliminate extra copies making it easier to fold the
729   // real source operand. We want to eliminate dead instructions after, so that
730   // we see fewer uses of the copies. We then need to clean up the dead
731   // instructions leftover after the operands are folded as well.
732   //
733   // XXX - Can we get away without running DeadMachineInstructionElim again?
734   addPass(&SIFoldOperandsID);
735   addPass(&DeadMachineInstructionElimID);
736   addPass(&SILoadStoreOptimizerID);
737   if (EnableSDWAPeephole) {
738     addPass(&SIPeepholeSDWAID);
739     addPass(&MachineLICMID);
740     addPass(&MachineCSEID);
741     addPass(&SIFoldOperandsID);
742     addPass(&DeadMachineInstructionElimID);
743   }
744   addPass(createSIShrinkInstructionsPass());
745 }
746 
747 bool GCNPassConfig::addILPOpts() {
748   if (EnableEarlyIfConversion)
749     addPass(&EarlyIfConverterID);
750 
751   TargetPassConfig::addILPOpts();
752   return false;
753 }
754 
755 bool GCNPassConfig::addInstSelector() {
756   AMDGPUPassConfig::addInstSelector();
757   addPass(createSILowerI1CopiesPass());
758   addPass(&SIFixSGPRCopiesID);
759   return false;
760 }
761 
762 #ifdef LLVM_BUILD_GLOBAL_ISEL
763 bool GCNPassConfig::addIRTranslator() {
764   addPass(new IRTranslator());
765   return false;
766 }
767 
768 bool GCNPassConfig::addLegalizeMachineIR() {
769   addPass(new Legalizer());
770   return false;
771 }
772 
773 bool GCNPassConfig::addRegBankSelect() {
774   addPass(new RegBankSelect());
775   return false;
776 }
777 
778 bool GCNPassConfig::addGlobalInstructionSelect() {
779   addPass(new InstructionSelect());
780   return false;
781 }
782 
783 #endif
784 
785 void GCNPassConfig::addPreRegAlloc() {
786   if (LateCFGStructurize) {
787     addPass(createAMDGPUMachineCFGStructurizerPass());
788   }
789   addPass(createSIWholeQuadModePass());
790 }
791 
792 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
793   // FIXME: We have to disable the verifier here because of PHIElimination +
794   // TwoAddressInstructions disabling it.
795 
796   // This must be run immediately after phi elimination and before
797   // TwoAddressInstructions, otherwise the processing of the tied operand of
798   // SI_ELSE will introduce a copy of the tied operand source after the else.
799   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
800 
801   TargetPassConfig::addFastRegAlloc(RegAllocPass);
802 }
803 
804 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
805   // This needs to be run directly before register allocation because earlier
806   // passes might recompute live intervals.
807   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
808 
809   // This must be run immediately after phi elimination and before
810   // TwoAddressInstructions, otherwise the processing of the tied operand of
811   // SI_ELSE will introduce a copy of the tied operand source after the else.
812   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
813 
814   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
815 }
816 
817 void GCNPassConfig::addPostRegAlloc() {
818   addPass(&SIFixVGPRCopiesID);
819   addPass(&SIOptimizeExecMaskingID);
820   TargetPassConfig::addPostRegAlloc();
821 }
822 
823 void GCNPassConfig::addPreSched2() {
824 }
825 
826 void GCNPassConfig::addPreEmitPass() {
827   // The hazard recognizer that runs as part of the post-ra scheduler does not
828   // guarantee to be able handle all hazards correctly. This is because if there
829   // are multiple scheduling regions in a basic block, the regions are scheduled
830   // bottom up, so when we begin to schedule a region we don't know what
831   // instructions were emitted directly before it.
832   //
833   // Here we add a stand-alone hazard recognizer pass which can handle all
834   // cases.
835   addPass(&PostRAHazardRecognizerID);
836 
837   if (EnableSIInsertWaitcntsPass)
838     addPass(createSIInsertWaitcntsPass());
839   else
840     addPass(createSIInsertWaitsPass());
841   addPass(createSIShrinkInstructionsPass());
842   addPass(&SIInsertSkipsPassID);
843   addPass(createSIDebuggerInsertNopsPass());
844   addPass(&BranchRelaxationPassID);
845 }
846 
847 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
848   return new GCNPassConfig(*this, PM);
849 }
850 
851