1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "llvm/Analysis/CGSCCPassManager.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/Localizer.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MIRParser/MIParser.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/LegacyPassManager.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/Passes/PassBuilder.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Transforms/IPO.h"
42 #include "llvm/Transforms/IPO/AlwaysInliner.h"
43 #include "llvm/Transforms/IPO/GlobalDCE.h"
44 #include "llvm/Transforms/IPO/Internalize.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
51 #include "llvm/Transforms/Vectorize.h"
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
140   "amdgpu-fixed-function-abi",
141   cl::desc("Enable all implicit function arguments"),
142   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
143   cl::init(false),
144   cl::Hidden);
145 
146 // Enable lib calls simplifications
147 static cl::opt<bool> EnableLibCallSimplify(
148   "amdgpu-simplify-libcall",
149   cl::desc("Enable amdgpu library simplifications"),
150   cl::init(true),
151   cl::Hidden);
152 
153 static cl::opt<bool> EnableLowerKernelArguments(
154   "amdgpu-ir-lower-kernel-arguments",
155   cl::desc("Lower kernel argument loads in IR pass"),
156   cl::init(true),
157   cl::Hidden);
158 
159 static cl::opt<bool> EnableRegReassign(
160   "amdgpu-reassign-regs",
161   cl::desc("Enable register reassign optimizations on gfx10+"),
162   cl::init(true),
163   cl::Hidden);
164 
165 // Enable atomic optimization
166 static cl::opt<bool> EnableAtomicOptimizations(
167   "amdgpu-atomic-optimizations",
168   cl::desc("Enable atomic optimizations"),
169   cl::init(false),
170   cl::Hidden);
171 
172 // Enable Mode register optimization
173 static cl::opt<bool> EnableSIModeRegisterPass(
174   "amdgpu-mode-register",
175   cl::desc("Enable mode register pass"),
176   cl::init(true),
177   cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182     cl::init(true), cl::Hidden,
183     cl::desc("Enable machine DCE inside regalloc"));
184 
185 static cl::opt<bool> EnableScalarIRPasses(
186   "amdgpu-scalar-ir-passes",
187   cl::desc("Enable scalar IR passes"),
188   cl::init(true),
189   cl::Hidden);
190 
191 static cl::opt<bool> EnableStructurizerWorkarounds(
192     "amdgpu-enable-structurizer-workarounds",
193     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194     cl::Hidden);
195 
196 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
197   // Register the target
198   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
199   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
200 
201   PassRegistry *PR = PassRegistry::getPassRegistry();
202   initializeR600ClauseMergePassPass(*PR);
203   initializeR600ControlFlowFinalizerPass(*PR);
204   initializeR600PacketizerPass(*PR);
205   initializeR600ExpandSpecialInstrsPassPass(*PR);
206   initializeR600VectorRegMergerPass(*PR);
207   initializeGlobalISel(*PR);
208   initializeAMDGPUDAGToDAGISelPass(*PR);
209   initializeGCNDPPCombinePass(*PR);
210   initializeSILowerI1CopiesPass(*PR);
211   initializeSILowerSGPRSpillsPass(*PR);
212   initializeSIFixSGPRCopiesPass(*PR);
213   initializeSIFixVGPRCopiesPass(*PR);
214   initializeSIFoldOperandsPass(*PR);
215   initializeSIPeepholeSDWAPass(*PR);
216   initializeSIShrinkInstructionsPass(*PR);
217   initializeSIOptimizeExecMaskingPreRAPass(*PR);
218   initializeSILoadStoreOptimizerPass(*PR);
219   initializeAMDGPUFixFunctionBitcastsPass(*PR);
220   initializeAMDGPUAlwaysInlinePass(*PR);
221   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
222   initializeAMDGPUAnnotateUniformValuesPass(*PR);
223   initializeAMDGPUArgumentUsageInfoPass(*PR);
224   initializeAMDGPUAtomicOptimizerPass(*PR);
225   initializeAMDGPULowerKernelArgumentsPass(*PR);
226   initializeAMDGPULowerKernelAttributesPass(*PR);
227   initializeAMDGPULowerIntrinsicsPass(*PR);
228   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
229   initializeAMDGPUPostLegalizerCombinerPass(*PR);
230   initializeAMDGPUPreLegalizerCombinerPass(*PR);
231   initializeAMDGPUPromoteAllocaPass(*PR);
232   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
233   initializeAMDGPUCodeGenPreparePass(*PR);
234   initializeAMDGPULateCodeGenPreparePass(*PR);
235   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
236   initializeAMDGPUPropagateAttributesLatePass(*PR);
237   initializeAMDGPURewriteOutArgumentsPass(*PR);
238   initializeAMDGPUUnifyMetadataPass(*PR);
239   initializeSIAnnotateControlFlowPass(*PR);
240   initializeSIInsertHardClausesPass(*PR);
241   initializeSIInsertWaitcntsPass(*PR);
242   initializeSIModeRegisterPass(*PR);
243   initializeSIWholeQuadModePass(*PR);
244   initializeSILowerControlFlowPass(*PR);
245   initializeSIRemoveShortExecBranchesPass(*PR);
246   initializeSIPreEmitPeepholePass(*PR);
247   initializeSIInsertSkipsPass(*PR);
248   initializeSIMemoryLegalizerPass(*PR);
249   initializeSIOptimizeExecMaskingPass(*PR);
250   initializeSIPreAllocateWWMRegsPass(*PR);
251   initializeSIFormMemoryClausesPass(*PR);
252   initializeSIPostRABundlerPass(*PR);
253   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
254   initializeAMDGPUAAWrapperPassPass(*PR);
255   initializeAMDGPUExternalAAWrapperPass(*PR);
256   initializeAMDGPUUseNativeCallsPass(*PR);
257   initializeAMDGPUSimplifyLibCallsPass(*PR);
258   initializeAMDGPUInlinerPass(*PR);
259   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
260   initializeGCNRegBankReassignPass(*PR);
261   initializeGCNNSAReassignPass(*PR);
262   initializeSIAddIMGInitPass(*PR);
263 }
264 
265 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
266   return std::make_unique<AMDGPUTargetObjectFile>();
267 }
268 
269 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
270   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
271 }
272 
273 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
274   return new SIScheduleDAGMI(C);
275 }
276 
277 static ScheduleDAGInstrs *
278 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
279   ScheduleDAGMILive *DAG =
280     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
281   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
282   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
283   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
284   return DAG;
285 }
286 
287 static ScheduleDAGInstrs *
288 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
289   auto DAG = new GCNIterativeScheduler(C,
290     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
291   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
292   return DAG;
293 }
294 
295 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
296   return new GCNIterativeScheduler(C,
297     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
298 }
299 
300 static ScheduleDAGInstrs *
301 createIterativeILPMachineScheduler(MachineSchedContext *C) {
302   auto DAG = new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_ILP);
304   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
305   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
306   return DAG;
307 }
308 
309 static MachineSchedRegistry
310 R600SchedRegistry("r600", "Run R600's custom scheduler",
311                    createR600MachineScheduler);
312 
313 static MachineSchedRegistry
314 SISchedRegistry("si", "Run SI's custom scheduler",
315                 createSIMachineScheduler);
316 
317 static MachineSchedRegistry
318 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
319                              "Run GCN scheduler to maximize occupancy",
320                              createGCNMaxOccupancyMachineScheduler);
321 
322 static MachineSchedRegistry
323 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
324   "Run GCN scheduler to maximize occupancy (experimental)",
325   createIterativeGCNMaxOccupancyMachineScheduler);
326 
327 static MachineSchedRegistry
328 GCNMinRegSchedRegistry("gcn-minreg",
329   "Run GCN iterative scheduler for minimal register usage (experimental)",
330   createMinRegScheduler);
331 
332 static MachineSchedRegistry
333 GCNILPSchedRegistry("gcn-ilp",
334   "Run GCN iterative scheduler for ILP scheduling (experimental)",
335   createIterativeILPMachineScheduler);
336 
337 static StringRef computeDataLayout(const Triple &TT) {
338   if (TT.getArch() == Triple::r600) {
339     // 32-bit pointers.
340     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
341            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
342   }
343 
344   // 32-bit private, local, and region pointers. 64-bit global, constant and
345   // flat, non-integral buffer fat pointers.
346   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
347          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
348          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
349          "-ni:7";
350 }
351 
352 LLVM_READNONE
353 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
354   if (!GPU.empty())
355     return GPU;
356 
357   // Need to default to a target with flat support for HSA.
358   if (TT.getArch() == Triple::amdgcn)
359     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
360 
361   return "r600";
362 }
363 
364 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
365   // The AMDGPU toolchain only supports generating shared objects, so we
366   // must always use PIC.
367   return Reloc::PIC_;
368 }
369 
370 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
371                                          StringRef CPU, StringRef FS,
372                                          TargetOptions Options,
373                                          Optional<Reloc::Model> RM,
374                                          Optional<CodeModel::Model> CM,
375                                          CodeGenOpt::Level OptLevel)
376     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
377                         FS, Options, getEffectiveRelocModel(RM),
378                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
379       TLOF(createTLOF(getTargetTriple())) {
380   initAsmInfo();
381   if (TT.getArch() == Triple::amdgcn) {
382     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
383       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
384     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
385       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
386   }
387 }
388 
389 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
390 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
391 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
392 
393 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
394 
395 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
396   Attribute GPUAttr = F.getFnAttribute("target-cpu");
397   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
398 }
399 
400 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
401   Attribute FSAttr = F.getFnAttribute("target-features");
402 
403   return FSAttr.isValid() ? FSAttr.getValueAsString()
404                           : getTargetFeatureString();
405 }
406 
407 /// Predicate for Internalize pass.
408 static bool mustPreserveGV(const GlobalValue &GV) {
409   if (const Function *F = dyn_cast<Function>(&GV))
410     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
411 
412   return !GV.use_empty();
413 }
414 
415 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
416   Builder.DivergentTarget = true;
417 
418   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
419   bool Internalize = InternalizeSymbols;
420   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
421   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
422   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
423 
424   if (EnableFunctionCalls) {
425     delete Builder.Inliner;
426     Builder.Inliner = createAMDGPUFunctionInliningPass();
427   }
428 
429   Builder.addExtension(
430     PassManagerBuilder::EP_ModuleOptimizerEarly,
431     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
432                                                legacy::PassManagerBase &PM) {
433       if (AMDGPUAA) {
434         PM.add(createAMDGPUAAWrapperPass());
435         PM.add(createAMDGPUExternalAAWrapperPass());
436       }
437       PM.add(createAMDGPUUnifyMetadataPass());
438       PM.add(createAMDGPUPrintfRuntimeBinding());
439       if (Internalize)
440         PM.add(createInternalizePass(mustPreserveGV));
441       PM.add(createAMDGPUPropagateAttributesLatePass(this));
442       if (Internalize)
443         PM.add(createGlobalDCEPass());
444       if (EarlyInline)
445         PM.add(createAMDGPUAlwaysInlinePass(false));
446   });
447 
448   Builder.addExtension(
449     PassManagerBuilder::EP_EarlyAsPossible,
450     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
451                                       legacy::PassManagerBase &PM) {
452       if (AMDGPUAA) {
453         PM.add(createAMDGPUAAWrapperPass());
454         PM.add(createAMDGPUExternalAAWrapperPass());
455       }
456       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
457       PM.add(llvm::createAMDGPUUseNativeCallsPass());
458       if (LibCallSimplify)
459         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
460   });
461 
462   Builder.addExtension(
463     PassManagerBuilder::EP_CGSCCOptimizerLate,
464     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
465       // Add infer address spaces pass to the opt pipeline after inlining
466       // but before SROA to increase SROA opportunities.
467       PM.add(createInferAddressSpacesPass());
468 
469       // This should run after inlining to have any chance of doing anything,
470       // and before other cleanup optimizations.
471       PM.add(createAMDGPULowerKernelAttributesPass());
472 
473       // Promote alloca to vector before SROA and loop unroll. If we manage
474       // to eliminate allocas before unroll we may choose to unroll less.
475       if (EnableOpt)
476         PM.add(createAMDGPUPromoteAllocaToVector());
477   });
478 }
479 
480 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
481   AAM.registerFunctionAnalysis<AMDGPUAA>();
482 }
483 
484 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
485                                                        bool DebugPassManager) {
486   PB.registerPipelineParsingCallback(
487       [this](StringRef PassName, ModulePassManager &PM,
488              ArrayRef<PassBuilder::PipelineElement>) {
489         if (PassName == "amdgpu-propagate-attributes-late") {
490           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
491           return true;
492         }
493         if (PassName == "amdgpu-unify-metadata") {
494           PM.addPass(AMDGPUUnifyMetadataPass());
495           return true;
496         }
497         if (PassName == "amdgpu-printf-runtime-binding") {
498           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
499           return true;
500         }
501         if (PassName == "amdgpu-always-inline") {
502           PM.addPass(AMDGPUAlwaysInlinePass());
503           return true;
504         }
505         return false;
506       });
507   PB.registerPipelineParsingCallback(
508       [this](StringRef PassName, FunctionPassManager &PM,
509              ArrayRef<PassBuilder::PipelineElement>) {
510         if (PassName == "amdgpu-simplifylib") {
511           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
512           return true;
513         }
514         if (PassName == "amdgpu-usenative") {
515           PM.addPass(AMDGPUUseNativeCallsPass());
516           return true;
517         }
518         if (PassName == "amdgpu-promote-alloca") {
519           PM.addPass(AMDGPUPromoteAllocaPass(*this));
520           return true;
521         }
522         if (PassName == "amdgpu-promote-alloca-to-vector") {
523           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
524           return true;
525         }
526         if (PassName == "amdgpu-lower-kernel-attributes") {
527           PM.addPass(AMDGPULowerKernelAttributesPass());
528           return true;
529         }
530         if (PassName == "amdgpu-propagate-attributes-early") {
531           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
532           return true;
533         }
534 
535         return false;
536       });
537 
538   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
539     FAM.registerPass([&] { return AMDGPUAA(); });
540   });
541 
542   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
543     if (AAName == "amdgpu-aa") {
544       AAM.registerFunctionAnalysis<AMDGPUAA>();
545       return true;
546     }
547     return false;
548   });
549 
550   PB.registerPipelineStartEPCallback([this, DebugPassManager](
551                                          ModulePassManager &PM,
552                                          PassBuilder::OptimizationLevel Level) {
553     FunctionPassManager FPM(DebugPassManager);
554     FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
555     FPM.addPass(AMDGPUUseNativeCallsPass());
556     if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
557       FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
558     PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
559   });
560 
561   PB.registerPipelineEarlySimplificationEPCallback(
562       [this](ModulePassManager &PM, PassBuilder::OptimizationLevel Level) {
563         if (Level == PassBuilder::OptimizationLevel::O0)
564           return;
565 
566         PM.addPass(AMDGPUUnifyMetadataPass());
567         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
568 
569         if (InternalizeSymbols) {
570           PM.addPass(InternalizePass(mustPreserveGV));
571         }
572         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
573         if (InternalizeSymbols) {
574           PM.addPass(GlobalDCEPass());
575         }
576         if (EarlyInlineAll && !EnableFunctionCalls)
577           PM.addPass(AMDGPUAlwaysInlinePass());
578       });
579 
580   PB.registerCGSCCOptimizerLateEPCallback(
581       [this, DebugPassManager](CGSCCPassManager &PM,
582                                PassBuilder::OptimizationLevel Level) {
583           FunctionPassManager FPM(DebugPassManager);
584 
585           // Add infer address spaces pass to the opt pipeline after inlining
586           // but before SROA to increase SROA opportunities.
587           FPM.addPass(InferAddressSpacesPass());
588 
589           // This should run after inlining to have any chance of doing
590           // anything, and before other cleanup optimizations.
591           FPM.addPass(AMDGPULowerKernelAttributesPass());
592 
593           if (Level != PassBuilder::OptimizationLevel::O0) {
594             // Promote alloca to vector before SROA and loop unroll. If we
595             // manage to eliminate allocas before unroll we may choose to unroll
596             // less.
597             FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
598           }
599 
600           PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
601       });
602 }
603 
604 //===----------------------------------------------------------------------===//
605 // R600 Target Machine (R600 -> Cayman)
606 //===----------------------------------------------------------------------===//
607 
608 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
609                                      StringRef CPU, StringRef FS,
610                                      TargetOptions Options,
611                                      Optional<Reloc::Model> RM,
612                                      Optional<CodeModel::Model> CM,
613                                      CodeGenOpt::Level OL, bool JIT)
614     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
615   setRequiresStructuredCFG(true);
616 
617   // Override the default since calls aren't supported for r600.
618   if (EnableFunctionCalls &&
619       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
620     EnableFunctionCalls = false;
621 }
622 
623 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
624   const Function &F) const {
625   StringRef GPU = getGPUName(F);
626   StringRef FS = getFeatureString(F);
627 
628   SmallString<128> SubtargetKey(GPU);
629   SubtargetKey.append(FS);
630 
631   auto &I = SubtargetMap[SubtargetKey];
632   if (!I) {
633     // This needs to be done before we create a new subtarget since any
634     // creation will depend on the TM and the code generation flags on the
635     // function that reside in TargetOptions.
636     resetTargetOptions(F);
637     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
638   }
639 
640   return I.get();
641 }
642 
643 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
644   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
645           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
646           AddrSpace == AMDGPUAS::REGION_ADDRESS)
647              ? -1
648              : 0;
649 }
650 
651 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
652                                               unsigned DestAS) const {
653   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
654          AMDGPU::isFlatGlobalAddrSpace(DestAS);
655 }
656 
657 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
658   const auto *LD = dyn_cast<LoadInst>(V);
659   if (!LD)
660     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
661 
662   // It must be a generic pointer loaded.
663   assert(V->getType()->isPointerTy() &&
664          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
665 
666   const auto *Ptr = LD->getPointerOperand();
667   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
668     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
669   // For a generic pointer loaded from the constant memory, it could be assumed
670   // as a global pointer since the constant memory is only populated on the
671   // host side. As implied by the offload programming model, only global
672   // pointers could be referenced on the host side.
673   return AMDGPUAS::GLOBAL_ADDRESS;
674 }
675 
676 TargetTransformInfo
677 R600TargetMachine::getTargetTransformInfo(const Function &F) {
678   return TargetTransformInfo(R600TTIImpl(this, F));
679 }
680 
681 //===----------------------------------------------------------------------===//
682 // GCN Target Machine (SI+)
683 //===----------------------------------------------------------------------===//
684 
685 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
686                                    StringRef CPU, StringRef FS,
687                                    TargetOptions Options,
688                                    Optional<Reloc::Model> RM,
689                                    Optional<CodeModel::Model> CM,
690                                    CodeGenOpt::Level OL, bool JIT)
691     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
692 
693 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
694   StringRef GPU = getGPUName(F);
695   StringRef FS = getFeatureString(F);
696 
697   SmallString<128> SubtargetKey(GPU);
698   SubtargetKey.append(FS);
699 
700   auto &I = SubtargetMap[SubtargetKey];
701   if (!I) {
702     // This needs to be done before we create a new subtarget since any
703     // creation will depend on the TM and the code generation flags on the
704     // function that reside in TargetOptions.
705     resetTargetOptions(F);
706     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
707   }
708 
709   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
710 
711   return I.get();
712 }
713 
714 TargetTransformInfo
715 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
716   return TargetTransformInfo(GCNTTIImpl(this, F));
717 }
718 
719 //===----------------------------------------------------------------------===//
720 // AMDGPU Pass Setup
721 //===----------------------------------------------------------------------===//
722 
723 namespace {
724 
725 class AMDGPUPassConfig : public TargetPassConfig {
726 public:
727   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
728     : TargetPassConfig(TM, PM) {
729     // Exceptions and StackMaps are not supported, so these passes will never do
730     // anything.
731     disablePass(&StackMapLivenessID);
732     disablePass(&FuncletLayoutID);
733   }
734 
735   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
736     return getTM<AMDGPUTargetMachine>();
737   }
738 
739   ScheduleDAGInstrs *
740   createMachineScheduler(MachineSchedContext *C) const override {
741     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
742     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
743     return DAG;
744   }
745 
746   void addEarlyCSEOrGVNPass();
747   void addStraightLineScalarOptimizationPasses();
748   void addIRPasses() override;
749   void addCodeGenPrepare() override;
750   bool addPreISel() override;
751   bool addInstSelector() override;
752   bool addGCPasses() override;
753 
754   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
755 };
756 
757 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
758   return getStandardCSEConfigForOpt(TM->getOptLevel());
759 }
760 
761 class R600PassConfig final : public AMDGPUPassConfig {
762 public:
763   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
764     : AMDGPUPassConfig(TM, PM) {}
765 
766   ScheduleDAGInstrs *createMachineScheduler(
767     MachineSchedContext *C) const override {
768     return createR600MachineScheduler(C);
769   }
770 
771   bool addPreISel() override;
772   bool addInstSelector() override;
773   void addPreRegAlloc() override;
774   void addPreSched2() override;
775   void addPreEmitPass() override;
776 };
777 
778 class GCNPassConfig final : public AMDGPUPassConfig {
779 public:
780   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
781     : AMDGPUPassConfig(TM, PM) {
782     // It is necessary to know the register usage of the entire call graph.  We
783     // allow calls without EnableAMDGPUFunctionCalls if they are marked
784     // noinline, so this is always required.
785     setRequiresCodeGenSCCOrder(true);
786   }
787 
788   GCNTargetMachine &getGCNTargetMachine() const {
789     return getTM<GCNTargetMachine>();
790   }
791 
792   ScheduleDAGInstrs *
793   createMachineScheduler(MachineSchedContext *C) const override;
794 
795   bool addPreISel() override;
796   void addMachineSSAOptimization() override;
797   bool addILPOpts() override;
798   bool addInstSelector() override;
799   bool addIRTranslator() override;
800   void addPreLegalizeMachineIR() override;
801   bool addLegalizeMachineIR() override;
802   void addPreRegBankSelect() override;
803   bool addRegBankSelect() override;
804   bool addGlobalInstructionSelect() override;
805   void addFastRegAlloc() override;
806   void addOptimizedRegAlloc() override;
807   void addPreRegAlloc() override;
808   bool addPreRewrite() override;
809   void addPostRegAlloc() override;
810   void addPreSched2() override;
811   void addPreEmitPass() override;
812 };
813 
814 } // end anonymous namespace
815 
816 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
817   if (getOptLevel() == CodeGenOpt::Aggressive)
818     addPass(createGVNPass());
819   else
820     addPass(createEarlyCSEPass());
821 }
822 
823 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
824   addPass(createLICMPass());
825   addPass(createSeparateConstOffsetFromGEPPass());
826   addPass(createSpeculativeExecutionPass());
827   // ReassociateGEPs exposes more opportunites for SLSR. See
828   // the example in reassociate-geps-and-slsr.ll.
829   addPass(createStraightLineStrengthReducePass());
830   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
831   // EarlyCSE can reuse.
832   addEarlyCSEOrGVNPass();
833   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
834   addPass(createNaryReassociatePass());
835   // NaryReassociate on GEPs creates redundant common expressions, so run
836   // EarlyCSE after it.
837   addPass(createEarlyCSEPass());
838 }
839 
840 void AMDGPUPassConfig::addIRPasses() {
841   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
842 
843   // There is no reason to run these.
844   disablePass(&StackMapLivenessID);
845   disablePass(&FuncletLayoutID);
846   disablePass(&PatchableFunctionID);
847 
848   addPass(createAMDGPUPrintfRuntimeBinding());
849 
850   // This must occur before inlining, as the inliner will not look through
851   // bitcast calls.
852   addPass(createAMDGPUFixFunctionBitcastsPass());
853 
854   // A call to propagate attributes pass in the backend in case opt was not run.
855   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
856 
857   addPass(createAtomicExpandPass());
858 
859 
860   addPass(createAMDGPULowerIntrinsicsPass());
861 
862   // Function calls are not supported, so make sure we inline everything.
863   addPass(createAMDGPUAlwaysInlinePass());
864   addPass(createAlwaysInlinerLegacyPass());
865   // We need to add the barrier noop pass, otherwise adding the function
866   // inlining pass will cause all of the PassConfigs passes to be run
867   // one function at a time, which means if we have a nodule with two
868   // functions, then we will generate code for the first function
869   // without ever running any passes on the second.
870   addPass(createBarrierNoopPass());
871 
872   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
873   if (TM.getTargetTriple().getArch() == Triple::r600)
874     addPass(createR600OpenCLImageTypeLoweringPass());
875 
876   // Replace OpenCL enqueued block function pointers with global variables.
877   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
878 
879   if (TM.getOptLevel() > CodeGenOpt::None) {
880     addPass(createInferAddressSpacesPass());
881     addPass(createAMDGPUPromoteAlloca());
882 
883     if (EnableSROA)
884       addPass(createSROAPass());
885 
886     if (EnableScalarIRPasses)
887       addStraightLineScalarOptimizationPasses();
888 
889     if (EnableAMDGPUAliasAnalysis) {
890       addPass(createAMDGPUAAWrapperPass());
891       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
892                                              AAResults &AAR) {
893         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
894           AAR.addAAResult(WrapperPass->getResult());
895         }));
896     }
897   }
898 
899   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
900     // TODO: May want to move later or split into an early and late one.
901     addPass(createAMDGPUCodeGenPreparePass());
902   }
903 
904   TargetPassConfig::addIRPasses();
905 
906   // EarlyCSE is not always strong enough to clean up what LSR produces. For
907   // example, GVN can combine
908   //
909   //   %0 = add %a, %b
910   //   %1 = add %b, %a
911   //
912   // and
913   //
914   //   %0 = shl nsw %a, 2
915   //   %1 = shl %a, 2
916   //
917   // but EarlyCSE can do neither of them.
918   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
919     addEarlyCSEOrGVNPass();
920 }
921 
922 void AMDGPUPassConfig::addCodeGenPrepare() {
923   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
924     addPass(createAMDGPUAnnotateKernelFeaturesPass());
925 
926   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
927       EnableLowerKernelArguments)
928     addPass(createAMDGPULowerKernelArgumentsPass());
929 
930   addPass(&AMDGPUPerfHintAnalysisID);
931 
932   TargetPassConfig::addCodeGenPrepare();
933 
934   if (EnableLoadStoreVectorizer)
935     addPass(createLoadStoreVectorizerPass());
936 
937   // LowerSwitch pass may introduce unreachable blocks that can
938   // cause unexpected behavior for subsequent passes. Placing it
939   // here seems better that these blocks would get cleaned up by
940   // UnreachableBlockElim inserted next in the pass flow.
941   addPass(createLowerSwitchPass());
942 }
943 
944 bool AMDGPUPassConfig::addPreISel() {
945   addPass(createFlattenCFGPass());
946   return false;
947 }
948 
949 bool AMDGPUPassConfig::addInstSelector() {
950   // Defer the verifier until FinalizeISel.
951   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
952   return false;
953 }
954 
955 bool AMDGPUPassConfig::addGCPasses() {
956   // Do nothing. GC is not supported.
957   return false;
958 }
959 
960 //===----------------------------------------------------------------------===//
961 // R600 Pass Setup
962 //===----------------------------------------------------------------------===//
963 
964 bool R600PassConfig::addPreISel() {
965   AMDGPUPassConfig::addPreISel();
966 
967   if (EnableR600StructurizeCFG)
968     addPass(createStructurizeCFGPass());
969   return false;
970 }
971 
972 bool R600PassConfig::addInstSelector() {
973   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
974   return false;
975 }
976 
977 void R600PassConfig::addPreRegAlloc() {
978   addPass(createR600VectorRegMerger());
979 }
980 
981 void R600PassConfig::addPreSched2() {
982   addPass(createR600EmitClauseMarkers(), false);
983   if (EnableR600IfConvert)
984     addPass(&IfConverterID, false);
985   addPass(createR600ClauseMergePass(), false);
986 }
987 
988 void R600PassConfig::addPreEmitPass() {
989   addPass(createAMDGPUCFGStructurizerPass(), false);
990   addPass(createR600ExpandSpecialInstrsPass(), false);
991   addPass(&FinalizeMachineBundlesID, false);
992   addPass(createR600Packetizer(), false);
993   addPass(createR600ControlFlowFinalizer(), false);
994 }
995 
996 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
997   return new R600PassConfig(*this, PM);
998 }
999 
1000 //===----------------------------------------------------------------------===//
1001 // GCN Pass Setup
1002 //===----------------------------------------------------------------------===//
1003 
1004 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1005   MachineSchedContext *C) const {
1006   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1007   if (ST.enableSIScheduler())
1008     return createSIMachineScheduler(C);
1009   return createGCNMaxOccupancyMachineScheduler(C);
1010 }
1011 
1012 bool GCNPassConfig::addPreISel() {
1013   AMDGPUPassConfig::addPreISel();
1014 
1015   addPass(createAMDGPULateCodeGenPreparePass());
1016   if (EnableAtomicOptimizations) {
1017     addPass(createAMDGPUAtomicOptimizerPass());
1018   }
1019 
1020   // FIXME: We need to run a pass to propagate the attributes when calls are
1021   // supported.
1022 
1023   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1024   // regions formed by them.
1025   addPass(&AMDGPUUnifyDivergentExitNodesID);
1026   if (!LateCFGStructurize) {
1027     if (EnableStructurizerWorkarounds) {
1028       addPass(createFixIrreduciblePass());
1029       addPass(createUnifyLoopExitsPass());
1030     }
1031     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1032   }
1033   addPass(createSinkingPass());
1034   addPass(createAMDGPUAnnotateUniformValues());
1035   if (!LateCFGStructurize) {
1036     addPass(createSIAnnotateControlFlowPass());
1037   }
1038   addPass(createLCSSAPass());
1039 
1040   return false;
1041 }
1042 
1043 void GCNPassConfig::addMachineSSAOptimization() {
1044   TargetPassConfig::addMachineSSAOptimization();
1045 
1046   // We want to fold operands after PeepholeOptimizer has run (or as part of
1047   // it), because it will eliminate extra copies making it easier to fold the
1048   // real source operand. We want to eliminate dead instructions after, so that
1049   // we see fewer uses of the copies. We then need to clean up the dead
1050   // instructions leftover after the operands are folded as well.
1051   //
1052   // XXX - Can we get away without running DeadMachineInstructionElim again?
1053   addPass(&SIFoldOperandsID);
1054   if (EnableDPPCombine)
1055     addPass(&GCNDPPCombineID);
1056   addPass(&DeadMachineInstructionElimID);
1057   addPass(&SILoadStoreOptimizerID);
1058   if (EnableSDWAPeephole) {
1059     addPass(&SIPeepholeSDWAID);
1060     addPass(&EarlyMachineLICMID);
1061     addPass(&MachineCSEID);
1062     addPass(&SIFoldOperandsID);
1063     addPass(&DeadMachineInstructionElimID);
1064   }
1065   addPass(createSIShrinkInstructionsPass());
1066 }
1067 
1068 bool GCNPassConfig::addILPOpts() {
1069   if (EnableEarlyIfConversion)
1070     addPass(&EarlyIfConverterID);
1071 
1072   TargetPassConfig::addILPOpts();
1073   return false;
1074 }
1075 
1076 bool GCNPassConfig::addInstSelector() {
1077   AMDGPUPassConfig::addInstSelector();
1078   addPass(&SIFixSGPRCopiesID);
1079   addPass(createSILowerI1CopiesPass());
1080   addPass(createSIAddIMGInitPass());
1081   return false;
1082 }
1083 
1084 bool GCNPassConfig::addIRTranslator() {
1085   addPass(new IRTranslator(getOptLevel()));
1086   return false;
1087 }
1088 
1089 void GCNPassConfig::addPreLegalizeMachineIR() {
1090   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1091   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1092   addPass(new Localizer());
1093 }
1094 
1095 bool GCNPassConfig::addLegalizeMachineIR() {
1096   addPass(new Legalizer());
1097   return false;
1098 }
1099 
1100 void GCNPassConfig::addPreRegBankSelect() {
1101   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1102   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1103 }
1104 
1105 bool GCNPassConfig::addRegBankSelect() {
1106   addPass(new RegBankSelect());
1107   return false;
1108 }
1109 
1110 bool GCNPassConfig::addGlobalInstructionSelect() {
1111   addPass(new InstructionSelect());
1112   return false;
1113 }
1114 
1115 void GCNPassConfig::addPreRegAlloc() {
1116   if (LateCFGStructurize) {
1117     addPass(createAMDGPUMachineCFGStructurizerPass());
1118   }
1119 }
1120 
1121 void GCNPassConfig::addFastRegAlloc() {
1122   // FIXME: We have to disable the verifier here because of PHIElimination +
1123   // TwoAddressInstructions disabling it.
1124 
1125   // This must be run immediately after phi elimination and before
1126   // TwoAddressInstructions, otherwise the processing of the tied operand of
1127   // SI_ELSE will introduce a copy of the tied operand source after the else.
1128   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1129 
1130   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1131   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1132 
1133   TargetPassConfig::addFastRegAlloc();
1134 }
1135 
1136 void GCNPassConfig::addOptimizedRegAlloc() {
1137   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1138   // instructions that cause scheduling barriers.
1139   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1140   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1141 
1142   if (OptExecMaskPreRA)
1143     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1144   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1145 
1146   // This must be run immediately after phi elimination and before
1147   // TwoAddressInstructions, otherwise the processing of the tied operand of
1148   // SI_ELSE will introduce a copy of the tied operand source after the else.
1149   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1150 
1151   if (EnableDCEInRA)
1152     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1153 
1154   TargetPassConfig::addOptimizedRegAlloc();
1155 }
1156 
1157 bool GCNPassConfig::addPreRewrite() {
1158   if (EnableRegReassign) {
1159     addPass(&GCNNSAReassignID);
1160     addPass(&GCNRegBankReassignID);
1161   }
1162   return true;
1163 }
1164 
1165 void GCNPassConfig::addPostRegAlloc() {
1166   addPass(&SIFixVGPRCopiesID);
1167   if (getOptLevel() > CodeGenOpt::None)
1168     addPass(&SIOptimizeExecMaskingID);
1169   TargetPassConfig::addPostRegAlloc();
1170 
1171   // Equivalent of PEI for SGPRs.
1172   addPass(&SILowerSGPRSpillsID);
1173 }
1174 
1175 void GCNPassConfig::addPreSched2() {
1176   addPass(&SIPostRABundlerID);
1177 }
1178 
1179 void GCNPassConfig::addPreEmitPass() {
1180   addPass(createSIMemoryLegalizerPass());
1181   addPass(createSIInsertWaitcntsPass());
1182   addPass(createSIShrinkInstructionsPass());
1183   addPass(createSIModeRegisterPass());
1184 
1185   if (getOptLevel() > CodeGenOpt::None)
1186     addPass(&SIInsertHardClausesID);
1187 
1188   addPass(&SIRemoveShortExecBranchesID);
1189   addPass(&SIInsertSkipsPassID);
1190   addPass(&SIPreEmitPeepholeID);
1191   // The hazard recognizer that runs as part of the post-ra scheduler does not
1192   // guarantee to be able handle all hazards correctly. This is because if there
1193   // are multiple scheduling regions in a basic block, the regions are scheduled
1194   // bottom up, so when we begin to schedule a region we don't know what
1195   // instructions were emitted directly before it.
1196   //
1197   // Here we add a stand-alone hazard recognizer pass which can handle all
1198   // cases.
1199   addPass(&PostRAHazardRecognizerID);
1200   addPass(&BranchRelaxationPassID);
1201 }
1202 
1203 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1204   return new GCNPassConfig(*this, PM);
1205 }
1206 
1207 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1208   return new yaml::SIMachineFunctionInfo();
1209 }
1210 
1211 yaml::MachineFunctionInfo *
1212 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1213   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1214   return new yaml::SIMachineFunctionInfo(*MFI,
1215                                          *MF.getSubtarget().getRegisterInfo());
1216 }
1217 
1218 bool GCNTargetMachine::parseMachineFunctionInfo(
1219     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1220     SMDiagnostic &Error, SMRange &SourceRange) const {
1221   const yaml::SIMachineFunctionInfo &YamlMFI =
1222       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1223   MachineFunction &MF = PFS.MF;
1224   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1225 
1226   MFI->initializeBaseYamlFields(YamlMFI);
1227 
1228   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1229     Register TempReg;
1230     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1231       SourceRange = RegName.SourceRange;
1232       return true;
1233     }
1234     RegVal = TempReg;
1235 
1236     return false;
1237   };
1238 
1239   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1240     // Create a diagnostic for a the register string literal.
1241     const MemoryBuffer &Buffer =
1242         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1243     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1244                          RegName.Value.size(), SourceMgr::DK_Error,
1245                          "incorrect register class for field", RegName.Value,
1246                          None, None);
1247     SourceRange = RegName.SourceRange;
1248     return true;
1249   };
1250 
1251   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1252       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1253       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1254     return true;
1255 
1256   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1257       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1258     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1259   }
1260 
1261   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1262       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1263     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1264   }
1265 
1266   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1267       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1268     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1269   }
1270 
1271   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1272                                    const TargetRegisterClass &RC,
1273                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1274                                    unsigned SystemSGPRs) {
1275     // Skip parsing if it's not present.
1276     if (!A)
1277       return false;
1278 
1279     if (A->IsRegister) {
1280       Register Reg;
1281       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1282         SourceRange = A->RegisterName.SourceRange;
1283         return true;
1284       }
1285       if (!RC.contains(Reg))
1286         return diagnoseRegisterClass(A->RegisterName);
1287       Arg = ArgDescriptor::createRegister(Reg);
1288     } else
1289       Arg = ArgDescriptor::createStack(A->StackOffset);
1290     // Check and apply the optional mask.
1291     if (A->Mask)
1292       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1293 
1294     MFI->NumUserSGPRs += UserSGPRs;
1295     MFI->NumSystemSGPRs += SystemSGPRs;
1296     return false;
1297   };
1298 
1299   if (YamlMFI.ArgInfo &&
1300       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1301                              AMDGPU::SGPR_128RegClass,
1302                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1303        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1304                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1305                              2, 0) ||
1306        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1307                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1308        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1309                              AMDGPU::SReg_64RegClass,
1310                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1311        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1312                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1313                              2, 0) ||
1314        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1315                              AMDGPU::SReg_64RegClass,
1316                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1317        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1318                              AMDGPU::SGPR_32RegClass,
1319                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1320        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1321                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1322                              0, 1) ||
1323        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1324                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1325                              0, 1) ||
1326        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1327                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1328                              0, 1) ||
1329        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1330                              AMDGPU::SGPR_32RegClass,
1331                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1332        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1333                              AMDGPU::SGPR_32RegClass,
1334                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1335        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1336                              AMDGPU::SReg_64RegClass,
1337                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1338        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1339                              AMDGPU::SReg_64RegClass,
1340                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1341        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1342                              AMDGPU::VGPR_32RegClass,
1343                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1344        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1345                              AMDGPU::VGPR_32RegClass,
1346                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1347        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1348                              AMDGPU::VGPR_32RegClass,
1349                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1350     return true;
1351 
1352   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1353   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1354   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1355   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1356   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1357   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1358 
1359   return false;
1360 }
1361