1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUExportClustering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
28 #include "R600MachineScheduler.h"
29 #include "SIMachineFunctionInfo.h"
30 #include "SIMachineScheduler.h"
31 #include "TargetInfo/AMDGPUTargetInfo.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
35 #include "llvm/CodeGen/GlobalISel/Localizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MIRParser/MIParser.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/LegacyPassManager.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Pass.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Transforms/IPO.h"
50 #include "llvm/Transforms/IPO/AlwaysInliner.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Utils.h"
55 #include "llvm/Transforms/Vectorize.h"
56 #include <memory>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool> EnableR600StructurizeCFG(
61   "r600-ir-structurize",
62   cl::desc("Use StructurizeCFG IR pass"),
63   cl::init(true));
64 
65 static cl::opt<bool> EnableSROA(
66   "amdgpu-sroa",
67   cl::desc("Run SROA after promote alloca pass"),
68   cl::ReallyHidden,
69   cl::init(true));
70 
71 static cl::opt<bool>
72 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
73                         cl::desc("Run early if-conversion"),
74                         cl::init(false));
75 
76 static cl::opt<bool>
77 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
78             cl::desc("Run pre-RA exec mask optimizations"),
79             cl::init(true));
80 
81 static cl::opt<bool> EnableR600IfConvert(
82   "r600-if-convert",
83   cl::desc("Use if conversion pass"),
84   cl::ReallyHidden,
85   cl::init(true));
86 
87 // Option to disable vectorizer for tests.
88 static cl::opt<bool> EnableLoadStoreVectorizer(
89   "amdgpu-load-store-vectorizer",
90   cl::desc("Enable load store vectorizer"),
91   cl::init(true),
92   cl::Hidden);
93 
94 // Option to control global loads scalarization
95 static cl::opt<bool> ScalarizeGlobal(
96   "amdgpu-scalarize-global-loads",
97   cl::desc("Enable global load scalarization"),
98   cl::init(true),
99   cl::Hidden);
100 
101 // Option to run internalize pass.
102 static cl::opt<bool> InternalizeSymbols(
103   "amdgpu-internalize-symbols",
104   cl::desc("Enable elimination of non-kernel functions and unused globals"),
105   cl::init(false),
106   cl::Hidden);
107 
108 // Option to inline all early.
109 static cl::opt<bool> EarlyInlineAll(
110   "amdgpu-early-inline-all",
111   cl::desc("Inline all functions early"),
112   cl::init(false),
113   cl::Hidden);
114 
115 static cl::opt<bool> EnableSDWAPeephole(
116   "amdgpu-sdwa-peephole",
117   cl::desc("Enable SDWA peepholer"),
118   cl::init(true));
119 
120 static cl::opt<bool> EnableDPPCombine(
121   "amdgpu-dpp-combine",
122   cl::desc("Enable DPP combiner"),
123   cl::init(true));
124 
125 // Enable address space based alias analysis
126 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
127   cl::desc("Enable AMDGPU Alias Analysis"),
128   cl::init(true));
129 
130 // Option to run late CFG structurizer
131 static cl::opt<bool, true> LateCFGStructurize(
132   "amdgpu-late-structurize",
133   cl::desc("Enable late CFG structurization"),
134   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
135   cl::Hidden);
136 
137 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
138   "amdgpu-function-calls",
139   cl::desc("Enable AMDGPU function call support"),
140   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
141   cl::init(true),
142   cl::Hidden);
143 
144 static cl::opt<bool, true> EnableAMDGPUFixedFunctionABIOpt(
145   "amdgpu-fixed-function-abi",
146   cl::desc("Enable all implicit function arguments"),
147   cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI),
148   cl::init(false),
149   cl::Hidden);
150 
151 // Enable lib calls simplifications
152 static cl::opt<bool> EnableLibCallSimplify(
153   "amdgpu-simplify-libcall",
154   cl::desc("Enable amdgpu library simplifications"),
155   cl::init(true),
156   cl::Hidden);
157 
158 static cl::opt<bool> EnableLowerKernelArguments(
159   "amdgpu-ir-lower-kernel-arguments",
160   cl::desc("Lower kernel argument loads in IR pass"),
161   cl::init(true),
162   cl::Hidden);
163 
164 static cl::opt<bool> EnableRegReassign(
165   "amdgpu-reassign-regs",
166   cl::desc("Enable register reassign optimizations on gfx10+"),
167   cl::init(true),
168   cl::Hidden);
169 
170 // Enable atomic optimization
171 static cl::opt<bool> EnableAtomicOptimizations(
172   "amdgpu-atomic-optimizations",
173   cl::desc("Enable atomic optimizations"),
174   cl::init(false),
175   cl::Hidden);
176 
177 // Enable Mode register optimization
178 static cl::opt<bool> EnableSIModeRegisterPass(
179   "amdgpu-mode-register",
180   cl::desc("Enable mode register pass"),
181   cl::init(true),
182   cl::Hidden);
183 
184 // Option is used in lit tests to prevent deadcoding of patterns inspected.
185 static cl::opt<bool>
186 EnableDCEInRA("amdgpu-dce-in-ra",
187     cl::init(true), cl::Hidden,
188     cl::desc("Enable machine DCE inside regalloc"));
189 
190 static cl::opt<bool> EnableScalarIRPasses(
191   "amdgpu-scalar-ir-passes",
192   cl::desc("Enable scalar IR passes"),
193   cl::init(true),
194   cl::Hidden);
195 
196 static cl::opt<bool> EnableStructurizerWorkarounds(
197     "amdgpu-enable-structurizer-workarounds",
198     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
199     cl::Hidden);
200 
201 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
202   // Register the target
203   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
204   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
205 
206   PassRegistry *PR = PassRegistry::getPassRegistry();
207   initializeR600ClauseMergePassPass(*PR);
208   initializeR600ControlFlowFinalizerPass(*PR);
209   initializeR600PacketizerPass(*PR);
210   initializeR600ExpandSpecialInstrsPassPass(*PR);
211   initializeR600VectorRegMergerPass(*PR);
212   initializeGlobalISel(*PR);
213   initializeAMDGPUDAGToDAGISelPass(*PR);
214   initializeGCNDPPCombinePass(*PR);
215   initializeSILowerI1CopiesPass(*PR);
216   initializeSILowerSGPRSpillsPass(*PR);
217   initializeSIFixSGPRCopiesPass(*PR);
218   initializeSIFixVGPRCopiesPass(*PR);
219   initializeSIFoldOperandsPass(*PR);
220   initializeSIPeepholeSDWAPass(*PR);
221   initializeSIShrinkInstructionsPass(*PR);
222   initializeSIOptimizeExecMaskingPreRAPass(*PR);
223   initializeSILoadStoreOptimizerPass(*PR);
224   initializeAMDGPUFixFunctionBitcastsPass(*PR);
225   initializeAMDGPUAlwaysInlinePass(*PR);
226   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
227   initializeAMDGPUAnnotateUniformValuesPass(*PR);
228   initializeAMDGPUArgumentUsageInfoPass(*PR);
229   initializeAMDGPUAtomicOptimizerPass(*PR);
230   initializeAMDGPULowerKernelArgumentsPass(*PR);
231   initializeAMDGPULowerKernelAttributesPass(*PR);
232   initializeAMDGPULowerIntrinsicsPass(*PR);
233   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
234   initializeAMDGPUPostLegalizerCombinerPass(*PR);
235   initializeAMDGPUPreLegalizerCombinerPass(*PR);
236   initializeAMDGPUPromoteAllocaPass(*PR);
237   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
238   initializeAMDGPUCodeGenPreparePass(*PR);
239   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
240   initializeAMDGPUPropagateAttributesLatePass(*PR);
241   initializeAMDGPURewriteOutArgumentsPass(*PR);
242   initializeAMDGPUUnifyMetadataPass(*PR);
243   initializeSIAnnotateControlFlowPass(*PR);
244   initializeSIInsertHardClausesPass(*PR);
245   initializeSIInsertWaitcntsPass(*PR);
246   initializeSIModeRegisterPass(*PR);
247   initializeSIWholeQuadModePass(*PR);
248   initializeSILowerControlFlowPass(*PR);
249   initializeSIRemoveShortExecBranchesPass(*PR);
250   initializeSIPreEmitPeepholePass(*PR);
251   initializeSIInsertSkipsPass(*PR);
252   initializeSIMemoryLegalizerPass(*PR);
253   initializeSIOptimizeExecMaskingPass(*PR);
254   initializeSIPreAllocateWWMRegsPass(*PR);
255   initializeSIFormMemoryClausesPass(*PR);
256   initializeSIPostRABundlerPass(*PR);
257   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
258   initializeAMDGPUAAWrapperPassPass(*PR);
259   initializeAMDGPUExternalAAWrapperPass(*PR);
260   initializeAMDGPUUseNativeCallsPass(*PR);
261   initializeAMDGPUSimplifyLibCallsPass(*PR);
262   initializeAMDGPUInlinerPass(*PR);
263   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
264   initializeGCNRegBankReassignPass(*PR);
265   initializeGCNNSAReassignPass(*PR);
266   initializeSIAddIMGInitPass(*PR);
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270   return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
273 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
274   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
277 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
278   return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
282 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
283   ScheduleDAGMILive *DAG =
284     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
285   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
286   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
287   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
288   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
289   return DAG;
290 }
291 
292 static ScheduleDAGInstrs *
293 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
294   auto DAG = new GCNIterativeScheduler(C,
295     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
296   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
297   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
298   return DAG;
299 }
300 
301 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
302   return new GCNIterativeScheduler(C,
303     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
304 }
305 
306 static ScheduleDAGInstrs *
307 createIterativeILPMachineScheduler(MachineSchedContext *C) {
308   auto DAG = new GCNIterativeScheduler(C,
309     GCNIterativeScheduler::SCHEDULE_ILP);
310   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
311   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
312   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
313   return DAG;
314 }
315 
316 static MachineSchedRegistry
317 R600SchedRegistry("r600", "Run R600's custom scheduler",
318                    createR600MachineScheduler);
319 
320 static MachineSchedRegistry
321 SISchedRegistry("si", "Run SI's custom scheduler",
322                 createSIMachineScheduler);
323 
324 static MachineSchedRegistry
325 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
326                              "Run GCN scheduler to maximize occupancy",
327                              createGCNMaxOccupancyMachineScheduler);
328 
329 static MachineSchedRegistry
330 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
331   "Run GCN scheduler to maximize occupancy (experimental)",
332   createIterativeGCNMaxOccupancyMachineScheduler);
333 
334 static MachineSchedRegistry
335 GCNMinRegSchedRegistry("gcn-minreg",
336   "Run GCN iterative scheduler for minimal register usage (experimental)",
337   createMinRegScheduler);
338 
339 static MachineSchedRegistry
340 GCNILPSchedRegistry("gcn-ilp",
341   "Run GCN iterative scheduler for ILP scheduling (experimental)",
342   createIterativeILPMachineScheduler);
343 
344 static StringRef computeDataLayout(const Triple &TT) {
345   if (TT.getArch() == Triple::r600) {
346     // 32-bit pointers.
347       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
348              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
349   }
350 
351   // 32-bit private, local, and region pointers. 64-bit global, constant and
352   // flat, non-integral buffer fat pointers.
353     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
354          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
355          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
356          "-ni:7";
357 }
358 
359 LLVM_READNONE
360 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
361   if (!GPU.empty())
362     return GPU;
363 
364   // Need to default to a target with flat support for HSA.
365   if (TT.getArch() == Triple::amdgcn)
366     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
367 
368   return "r600";
369 }
370 
371 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
372   // The AMDGPU toolchain only supports generating shared objects, so we
373   // must always use PIC.
374   return Reloc::PIC_;
375 }
376 
377 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
378                                          StringRef CPU, StringRef FS,
379                                          TargetOptions Options,
380                                          Optional<Reloc::Model> RM,
381                                          Optional<CodeModel::Model> CM,
382                                          CodeGenOpt::Level OptLevel)
383     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
384                         FS, Options, getEffectiveRelocModel(RM),
385                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
386       TLOF(createTLOF(getTargetTriple())) {
387   initAsmInfo();
388   if (TT.getArch() == Triple::amdgcn) {
389     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
390       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
391     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
392       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
393   }
394 }
395 
396 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
397 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
398 bool AMDGPUTargetMachine::EnableFixedFunctionABI = false;
399 
400 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
401 
402 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
403   Attribute GPUAttr = F.getFnAttribute("target-cpu");
404   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
405 }
406 
407 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
408   Attribute FSAttr = F.getFnAttribute("target-features");
409 
410   return FSAttr.isValid() ? FSAttr.getValueAsString()
411                           : getTargetFeatureString();
412 }
413 
414 /// Predicate for Internalize pass.
415 static bool mustPreserveGV(const GlobalValue &GV) {
416   if (const Function *F = dyn_cast<Function>(&GV))
417     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
418 
419   return !GV.use_empty();
420 }
421 
422 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
423   Builder.DivergentTarget = true;
424 
425   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
426   bool Internalize = InternalizeSymbols;
427   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
428   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
429   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
430 
431   if (EnableFunctionCalls) {
432     delete Builder.Inliner;
433     Builder.Inliner = createAMDGPUFunctionInliningPass();
434   }
435 
436   Builder.addExtension(
437     PassManagerBuilder::EP_ModuleOptimizerEarly,
438     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
439                                                legacy::PassManagerBase &PM) {
440       if (AMDGPUAA) {
441         PM.add(createAMDGPUAAWrapperPass());
442         PM.add(createAMDGPUExternalAAWrapperPass());
443       }
444       PM.add(createAMDGPUUnifyMetadataPass());
445       PM.add(createAMDGPUPrintfRuntimeBinding());
446       if (Internalize)
447         PM.add(createInternalizePass(mustPreserveGV));
448       PM.add(createAMDGPUPropagateAttributesLatePass(this));
449       if (Internalize)
450         PM.add(createGlobalDCEPass());
451       if (EarlyInline)
452         PM.add(createAMDGPUAlwaysInlinePass(false));
453   });
454 
455   Builder.addExtension(
456     PassManagerBuilder::EP_EarlyAsPossible,
457     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
458                                       legacy::PassManagerBase &PM) {
459       if (AMDGPUAA) {
460         PM.add(createAMDGPUAAWrapperPass());
461         PM.add(createAMDGPUExternalAAWrapperPass());
462       }
463       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
464       PM.add(llvm::createAMDGPUUseNativeCallsPass());
465       if (LibCallSimplify)
466         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
467   });
468 
469   Builder.addExtension(
470     PassManagerBuilder::EP_CGSCCOptimizerLate,
471     [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
472       // Add infer address spaces pass to the opt pipeline after inlining
473       // but before SROA to increase SROA opportunities.
474       PM.add(createInferAddressSpacesPass());
475 
476       // This should run after inlining to have any chance of doing anything,
477       // and before other cleanup optimizations.
478       PM.add(createAMDGPULowerKernelAttributesPass());
479 
480       // Promote alloca to vector before SROA and loop unroll. If we manage
481       // to eliminate allocas before unroll we may choose to unroll less.
482       if (EnableOpt)
483         PM.add(createAMDGPUPromoteAllocaToVector());
484   });
485 }
486 
487 //===----------------------------------------------------------------------===//
488 // R600 Target Machine (R600 -> Cayman)
489 //===----------------------------------------------------------------------===//
490 
491 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
492                                      StringRef CPU, StringRef FS,
493                                      TargetOptions Options,
494                                      Optional<Reloc::Model> RM,
495                                      Optional<CodeModel::Model> CM,
496                                      CodeGenOpt::Level OL, bool JIT)
497     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
498   setRequiresStructuredCFG(true);
499 
500   // Override the default since calls aren't supported for r600.
501   if (EnableFunctionCalls &&
502       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
503     EnableFunctionCalls = false;
504 }
505 
506 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
507   const Function &F) const {
508   StringRef GPU = getGPUName(F);
509   StringRef FS = getFeatureString(F);
510 
511   SmallString<128> SubtargetKey(GPU);
512   SubtargetKey.append(FS);
513 
514   auto &I = SubtargetMap[SubtargetKey];
515   if (!I) {
516     // This needs to be done before we create a new subtarget since any
517     // creation will depend on the TM and the code generation flags on the
518     // function that reside in TargetOptions.
519     resetTargetOptions(F);
520     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
521   }
522 
523   return I.get();
524 }
525 
526 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
527                                               unsigned DestAS) const {
528   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
529          AMDGPU::isFlatGlobalAddrSpace(DestAS);
530 }
531 
532 TargetTransformInfo
533 R600TargetMachine::getTargetTransformInfo(const Function &F) {
534   return TargetTransformInfo(R600TTIImpl(this, F));
535 }
536 
537 //===----------------------------------------------------------------------===//
538 // GCN Target Machine (SI+)
539 //===----------------------------------------------------------------------===//
540 
541 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
542                                    StringRef CPU, StringRef FS,
543                                    TargetOptions Options,
544                                    Optional<Reloc::Model> RM,
545                                    Optional<CodeModel::Model> CM,
546                                    CodeGenOpt::Level OL, bool JIT)
547     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
548 
549 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
550   StringRef GPU = getGPUName(F);
551   StringRef FS = getFeatureString(F);
552 
553   SmallString<128> SubtargetKey(GPU);
554   SubtargetKey.append(FS);
555 
556   auto &I = SubtargetMap[SubtargetKey];
557   if (!I) {
558     // This needs to be done before we create a new subtarget since any
559     // creation will depend on the TM and the code generation flags on the
560     // function that reside in TargetOptions.
561     resetTargetOptions(F);
562     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
563   }
564 
565   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
566 
567   return I.get();
568 }
569 
570 TargetTransformInfo
571 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
572   return TargetTransformInfo(GCNTTIImpl(this, F));
573 }
574 
575 //===----------------------------------------------------------------------===//
576 // AMDGPU Pass Setup
577 //===----------------------------------------------------------------------===//
578 
579 namespace {
580 
581 class AMDGPUPassConfig : public TargetPassConfig {
582 public:
583   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
584     : TargetPassConfig(TM, PM) {
585     // Exceptions and StackMaps are not supported, so these passes will never do
586     // anything.
587     disablePass(&StackMapLivenessID);
588     disablePass(&FuncletLayoutID);
589   }
590 
591   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
592     return getTM<AMDGPUTargetMachine>();
593   }
594 
595   ScheduleDAGInstrs *
596   createMachineScheduler(MachineSchedContext *C) const override {
597     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
598     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
599     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
600     return DAG;
601   }
602 
603   void addEarlyCSEOrGVNPass();
604   void addStraightLineScalarOptimizationPasses();
605   void addIRPasses() override;
606   void addCodeGenPrepare() override;
607   bool addPreISel() override;
608   bool addInstSelector() override;
609   bool addGCPasses() override;
610 
611   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
612 };
613 
614 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
615   return getStandardCSEConfigForOpt(TM->getOptLevel());
616 }
617 
618 class R600PassConfig final : public AMDGPUPassConfig {
619 public:
620   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
621     : AMDGPUPassConfig(TM, PM) {}
622 
623   ScheduleDAGInstrs *createMachineScheduler(
624     MachineSchedContext *C) const override {
625     return createR600MachineScheduler(C);
626   }
627 
628   bool addPreISel() override;
629   bool addInstSelector() override;
630   void addPreRegAlloc() override;
631   void addPreSched2() override;
632   void addPreEmitPass() override;
633 };
634 
635 class GCNPassConfig final : public AMDGPUPassConfig {
636 public:
637   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
638     : AMDGPUPassConfig(TM, PM) {
639     // It is necessary to know the register usage of the entire call graph.  We
640     // allow calls without EnableAMDGPUFunctionCalls if they are marked
641     // noinline, so this is always required.
642     setRequiresCodeGenSCCOrder(true);
643   }
644 
645   GCNTargetMachine &getGCNTargetMachine() const {
646     return getTM<GCNTargetMachine>();
647   }
648 
649   ScheduleDAGInstrs *
650   createMachineScheduler(MachineSchedContext *C) const override;
651 
652   bool addPreISel() override;
653   void addMachineSSAOptimization() override;
654   bool addILPOpts() override;
655   bool addInstSelector() override;
656   bool addIRTranslator() override;
657   void addPreLegalizeMachineIR() override;
658   bool addLegalizeMachineIR() override;
659   void addPreRegBankSelect() override;
660   bool addRegBankSelect() override;
661   bool addGlobalInstructionSelect() override;
662   void addFastRegAlloc() override;
663   void addOptimizedRegAlloc() override;
664   void addPreRegAlloc() override;
665   bool addPreRewrite() override;
666   void addPostRegAlloc() override;
667   void addPreSched2() override;
668   void addPreEmitPass() override;
669 };
670 
671 } // end anonymous namespace
672 
673 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
674   if (getOptLevel() == CodeGenOpt::Aggressive)
675     addPass(createGVNPass());
676   else
677     addPass(createEarlyCSEPass());
678 }
679 
680 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
681   addPass(createLICMPass());
682   addPass(createSeparateConstOffsetFromGEPPass());
683   addPass(createSpeculativeExecutionPass());
684   // ReassociateGEPs exposes more opportunites for SLSR. See
685   // the example in reassociate-geps-and-slsr.ll.
686   addPass(createStraightLineStrengthReducePass());
687   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
688   // EarlyCSE can reuse.
689   addEarlyCSEOrGVNPass();
690   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
691   addPass(createNaryReassociatePass());
692   // NaryReassociate on GEPs creates redundant common expressions, so run
693   // EarlyCSE after it.
694   addPass(createEarlyCSEPass());
695 }
696 
697 void AMDGPUPassConfig::addIRPasses() {
698   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
699 
700   // There is no reason to run these.
701   disablePass(&StackMapLivenessID);
702   disablePass(&FuncletLayoutID);
703   disablePass(&PatchableFunctionID);
704 
705   addPass(createAMDGPUPrintfRuntimeBinding());
706 
707   // This must occur before inlining, as the inliner will not look through
708   // bitcast calls.
709   addPass(createAMDGPUFixFunctionBitcastsPass());
710 
711   // A call to propagate attributes pass in the backend in case opt was not run.
712   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
713 
714   addPass(createAtomicExpandPass());
715 
716 
717   addPass(createAMDGPULowerIntrinsicsPass());
718 
719   // Function calls are not supported, so make sure we inline everything.
720   addPass(createAMDGPUAlwaysInlinePass());
721   addPass(createAlwaysInlinerLegacyPass());
722   // We need to add the barrier noop pass, otherwise adding the function
723   // inlining pass will cause all of the PassConfigs passes to be run
724   // one function at a time, which means if we have a nodule with two
725   // functions, then we will generate code for the first function
726   // without ever running any passes on the second.
727   addPass(createBarrierNoopPass());
728 
729   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
730   if (TM.getTargetTriple().getArch() == Triple::r600)
731     addPass(createR600OpenCLImageTypeLoweringPass());
732 
733   // Replace OpenCL enqueued block function pointers with global variables.
734   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
735 
736   if (TM.getOptLevel() > CodeGenOpt::None) {
737     addPass(createInferAddressSpacesPass());
738     addPass(createAMDGPUPromoteAlloca());
739 
740     if (EnableSROA)
741       addPass(createSROAPass());
742 
743     if (EnableScalarIRPasses)
744       addStraightLineScalarOptimizationPasses();
745 
746     if (EnableAMDGPUAliasAnalysis) {
747       addPass(createAMDGPUAAWrapperPass());
748       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
749                                              AAResults &AAR) {
750         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
751           AAR.addAAResult(WrapperPass->getResult());
752         }));
753     }
754   }
755 
756   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
757     // TODO: May want to move later or split into an early and late one.
758     addPass(createAMDGPUCodeGenPreparePass());
759   }
760 
761   TargetPassConfig::addIRPasses();
762 
763   // EarlyCSE is not always strong enough to clean up what LSR produces. For
764   // example, GVN can combine
765   //
766   //   %0 = add %a, %b
767   //   %1 = add %b, %a
768   //
769   // and
770   //
771   //   %0 = shl nsw %a, 2
772   //   %1 = shl %a, 2
773   //
774   // but EarlyCSE can do neither of them.
775   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
776     addEarlyCSEOrGVNPass();
777 }
778 
779 void AMDGPUPassConfig::addCodeGenPrepare() {
780   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
781     addPass(createAMDGPUAnnotateKernelFeaturesPass());
782 
783   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
784       EnableLowerKernelArguments)
785     addPass(createAMDGPULowerKernelArgumentsPass());
786 
787   addPass(&AMDGPUPerfHintAnalysisID);
788 
789   TargetPassConfig::addCodeGenPrepare();
790 
791   if (EnableLoadStoreVectorizer)
792     addPass(createLoadStoreVectorizerPass());
793 
794   // LowerSwitch pass may introduce unreachable blocks that can
795   // cause unexpected behavior for subsequent passes. Placing it
796   // here seems better that these blocks would get cleaned up by
797   // UnreachableBlockElim inserted next in the pass flow.
798   addPass(createLowerSwitchPass());
799 }
800 
801 bool AMDGPUPassConfig::addPreISel() {
802   addPass(createFlattenCFGPass());
803   return false;
804 }
805 
806 bool AMDGPUPassConfig::addInstSelector() {
807   // Defer the verifier until FinalizeISel.
808   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
809   return false;
810 }
811 
812 bool AMDGPUPassConfig::addGCPasses() {
813   // Do nothing. GC is not supported.
814   return false;
815 }
816 
817 //===----------------------------------------------------------------------===//
818 // R600 Pass Setup
819 //===----------------------------------------------------------------------===//
820 
821 bool R600PassConfig::addPreISel() {
822   AMDGPUPassConfig::addPreISel();
823 
824   if (EnableR600StructurizeCFG)
825     addPass(createStructurizeCFGPass());
826   return false;
827 }
828 
829 bool R600PassConfig::addInstSelector() {
830   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
831   return false;
832 }
833 
834 void R600PassConfig::addPreRegAlloc() {
835   addPass(createR600VectorRegMerger());
836 }
837 
838 void R600PassConfig::addPreSched2() {
839   addPass(createR600EmitClauseMarkers(), false);
840   if (EnableR600IfConvert)
841     addPass(&IfConverterID, false);
842   addPass(createR600ClauseMergePass(), false);
843 }
844 
845 void R600PassConfig::addPreEmitPass() {
846   addPass(createAMDGPUCFGStructurizerPass(), false);
847   addPass(createR600ExpandSpecialInstrsPass(), false);
848   addPass(&FinalizeMachineBundlesID, false);
849   addPass(createR600Packetizer(), false);
850   addPass(createR600ControlFlowFinalizer(), false);
851 }
852 
853 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
854   return new R600PassConfig(*this, PM);
855 }
856 
857 //===----------------------------------------------------------------------===//
858 // GCN Pass Setup
859 //===----------------------------------------------------------------------===//
860 
861 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
862   MachineSchedContext *C) const {
863   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
864   if (ST.enableSIScheduler())
865     return createSIMachineScheduler(C);
866   return createGCNMaxOccupancyMachineScheduler(C);
867 }
868 
869 bool GCNPassConfig::addPreISel() {
870   AMDGPUPassConfig::addPreISel();
871 
872   if (EnableAtomicOptimizations) {
873     addPass(createAMDGPUAtomicOptimizerPass());
874   }
875 
876   // FIXME: We need to run a pass to propagate the attributes when calls are
877   // supported.
878 
879   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
880   // regions formed by them.
881   addPass(&AMDGPUUnifyDivergentExitNodesID);
882   if (!LateCFGStructurize) {
883     if (EnableStructurizerWorkarounds) {
884       addPass(createFixIrreduciblePass());
885       addPass(createUnifyLoopExitsPass());
886     }
887     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
888   }
889   addPass(createSinkingPass());
890   addPass(createAMDGPUAnnotateUniformValues());
891   if (!LateCFGStructurize) {
892     addPass(createSIAnnotateControlFlowPass());
893   }
894   addPass(createLCSSAPass());
895 
896   return false;
897 }
898 
899 void GCNPassConfig::addMachineSSAOptimization() {
900   TargetPassConfig::addMachineSSAOptimization();
901 
902   // We want to fold operands after PeepholeOptimizer has run (or as part of
903   // it), because it will eliminate extra copies making it easier to fold the
904   // real source operand. We want to eliminate dead instructions after, so that
905   // we see fewer uses of the copies. We then need to clean up the dead
906   // instructions leftover after the operands are folded as well.
907   //
908   // XXX - Can we get away without running DeadMachineInstructionElim again?
909   addPass(&SIFoldOperandsID);
910   if (EnableDPPCombine)
911     addPass(&GCNDPPCombineID);
912   addPass(&DeadMachineInstructionElimID);
913   addPass(&SILoadStoreOptimizerID);
914   if (EnableSDWAPeephole) {
915     addPass(&SIPeepholeSDWAID);
916     addPass(&EarlyMachineLICMID);
917     addPass(&MachineCSEID);
918     addPass(&SIFoldOperandsID);
919     addPass(&DeadMachineInstructionElimID);
920   }
921   addPass(createSIShrinkInstructionsPass());
922 }
923 
924 bool GCNPassConfig::addILPOpts() {
925   if (EnableEarlyIfConversion)
926     addPass(&EarlyIfConverterID);
927 
928   TargetPassConfig::addILPOpts();
929   return false;
930 }
931 
932 bool GCNPassConfig::addInstSelector() {
933   AMDGPUPassConfig::addInstSelector();
934   addPass(&SIFixSGPRCopiesID);
935   addPass(createSILowerI1CopiesPass());
936   addPass(createSIAddIMGInitPass());
937   return false;
938 }
939 
940 bool GCNPassConfig::addIRTranslator() {
941   addPass(new IRTranslator());
942   return false;
943 }
944 
945 void GCNPassConfig::addPreLegalizeMachineIR() {
946   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
947   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
948   addPass(new Localizer());
949 }
950 
951 bool GCNPassConfig::addLegalizeMachineIR() {
952   addPass(new Legalizer());
953   return false;
954 }
955 
956 void GCNPassConfig::addPreRegBankSelect() {
957   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
958   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
959 }
960 
961 bool GCNPassConfig::addRegBankSelect() {
962   addPass(new RegBankSelect());
963   return false;
964 }
965 
966 bool GCNPassConfig::addGlobalInstructionSelect() {
967   addPass(new InstructionSelect());
968   return false;
969 }
970 
971 void GCNPassConfig::addPreRegAlloc() {
972   if (LateCFGStructurize) {
973     addPass(createAMDGPUMachineCFGStructurizerPass());
974   }
975   addPass(createSIWholeQuadModePass());
976 }
977 
978 void GCNPassConfig::addFastRegAlloc() {
979   // FIXME: We have to disable the verifier here because of PHIElimination +
980   // TwoAddressInstructions disabling it.
981 
982   // This must be run immediately after phi elimination and before
983   // TwoAddressInstructions, otherwise the processing of the tied operand of
984   // SI_ELSE will introduce a copy of the tied operand source after the else.
985   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
986 
987   // This must be run just after RegisterCoalescing.
988   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
989 
990   TargetPassConfig::addFastRegAlloc();
991 }
992 
993 void GCNPassConfig::addOptimizedRegAlloc() {
994   if (OptExecMaskPreRA)
995     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
996   insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
997 
998   // This must be run immediately after phi elimination and before
999   // TwoAddressInstructions, otherwise the processing of the tied operand of
1000   // SI_ELSE will introduce a copy of the tied operand source after the else.
1001   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1002 
1003   // This must be run just after RegisterCoalescing.
1004   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
1005 
1006   if (EnableDCEInRA)
1007     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1008 
1009   TargetPassConfig::addOptimizedRegAlloc();
1010 }
1011 
1012 bool GCNPassConfig::addPreRewrite() {
1013   if (EnableRegReassign) {
1014     addPass(&GCNNSAReassignID);
1015     addPass(&GCNRegBankReassignID);
1016   }
1017   return true;
1018 }
1019 
1020 void GCNPassConfig::addPostRegAlloc() {
1021   addPass(&SIFixVGPRCopiesID);
1022   if (getOptLevel() > CodeGenOpt::None)
1023     addPass(&SIOptimizeExecMaskingID);
1024   TargetPassConfig::addPostRegAlloc();
1025 
1026   // Equivalent of PEI for SGPRs.
1027   addPass(&SILowerSGPRSpillsID);
1028 }
1029 
1030 void GCNPassConfig::addPreSched2() {
1031   addPass(&SIPostRABundlerID);
1032 }
1033 
1034 void GCNPassConfig::addPreEmitPass() {
1035   addPass(createSIMemoryLegalizerPass());
1036   addPass(createSIInsertWaitcntsPass());
1037   addPass(createSIShrinkInstructionsPass());
1038   addPass(createSIModeRegisterPass());
1039 
1040   // The hazard recognizer that runs as part of the post-ra scheduler does not
1041   // guarantee to be able handle all hazards correctly. This is because if there
1042   // are multiple scheduling regions in a basic block, the regions are scheduled
1043   // bottom up, so when we begin to schedule a region we don't know what
1044   // instructions were emitted directly before it.
1045   //
1046   // Here we add a stand-alone hazard recognizer pass which can handle all
1047   // cases.
1048   //
1049   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
1050   // be better for it to emit S_NOP <N> when possible.
1051   addPass(&PostRAHazardRecognizerID);
1052   if (getOptLevel() > CodeGenOpt::None)
1053     addPass(&SIInsertHardClausesID);
1054 
1055   addPass(&SIRemoveShortExecBranchesID);
1056   addPass(&SIInsertSkipsPassID);
1057   addPass(&SIPreEmitPeepholeID);
1058   addPass(&BranchRelaxationPassID);
1059 }
1060 
1061 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1062   return new GCNPassConfig(*this, PM);
1063 }
1064 
1065 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1066   return new yaml::SIMachineFunctionInfo();
1067 }
1068 
1069 yaml::MachineFunctionInfo *
1070 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1071   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1072   return new yaml::SIMachineFunctionInfo(*MFI,
1073                                          *MF.getSubtarget().getRegisterInfo());
1074 }
1075 
1076 bool GCNTargetMachine::parseMachineFunctionInfo(
1077     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1078     SMDiagnostic &Error, SMRange &SourceRange) const {
1079   const yaml::SIMachineFunctionInfo &YamlMFI =
1080       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1081   MachineFunction &MF = PFS.MF;
1082   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1083 
1084   MFI->initializeBaseYamlFields(YamlMFI);
1085 
1086   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1087     Register TempReg;
1088     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1089       SourceRange = RegName.SourceRange;
1090       return true;
1091     }
1092     RegVal = TempReg;
1093 
1094     return false;
1095   };
1096 
1097   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1098     // Create a diagnostic for a the register string literal.
1099     const MemoryBuffer &Buffer =
1100         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1101     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1102                          RegName.Value.size(), SourceMgr::DK_Error,
1103                          "incorrect register class for field", RegName.Value,
1104                          None, None);
1105     SourceRange = RegName.SourceRange;
1106     return true;
1107   };
1108 
1109   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1110       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1111       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1112     return true;
1113 
1114   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1115       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1116     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1117   }
1118 
1119   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1120       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1121     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1122   }
1123 
1124   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1125       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1126     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1127   }
1128 
1129   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1130                                    const TargetRegisterClass &RC,
1131                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1132                                    unsigned SystemSGPRs) {
1133     // Skip parsing if it's not present.
1134     if (!A)
1135       return false;
1136 
1137     if (A->IsRegister) {
1138       Register Reg;
1139       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1140         SourceRange = A->RegisterName.SourceRange;
1141         return true;
1142       }
1143       if (!RC.contains(Reg))
1144         return diagnoseRegisterClass(A->RegisterName);
1145       Arg = ArgDescriptor::createRegister(Reg);
1146     } else
1147       Arg = ArgDescriptor::createStack(A->StackOffset);
1148     // Check and apply the optional mask.
1149     if (A->Mask)
1150       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1151 
1152     MFI->NumUserSGPRs += UserSGPRs;
1153     MFI->NumSystemSGPRs += SystemSGPRs;
1154     return false;
1155   };
1156 
1157   if (YamlMFI.ArgInfo &&
1158       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1159                              AMDGPU::SGPR_128RegClass,
1160                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1161        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1162                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1163                              2, 0) ||
1164        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1165                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1166        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1167                              AMDGPU::SReg_64RegClass,
1168                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1169        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1170                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1171                              2, 0) ||
1172        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1173                              AMDGPU::SReg_64RegClass,
1174                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1175        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1176                              AMDGPU::SGPR_32RegClass,
1177                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1178        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1179                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1180                              0, 1) ||
1181        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1182                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1183                              0, 1) ||
1184        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1185                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1186                              0, 1) ||
1187        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1188                              AMDGPU::SGPR_32RegClass,
1189                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1190        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1191                              AMDGPU::SGPR_32RegClass,
1192                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1193        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1194                              AMDGPU::SReg_64RegClass,
1195                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1196        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1197                              AMDGPU::SReg_64RegClass,
1198                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1199        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1200                              AMDGPU::VGPR_32RegClass,
1201                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1202        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1203                              AMDGPU::VGPR_32RegClass,
1204                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1205        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1206                              AMDGPU::VGPR_32RegClass,
1207                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1208     return true;
1209 
1210   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1211   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1212   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1213   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1214   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1215   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1216 
1217   return false;
1218 }
1219