1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
21 #include "AMDGPUTargetTransformInfo.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600.h"
25 #include "R600TargetMachine.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIMachineScheduler.h"
28 #include "TargetInfo/AMDGPUTargetInfo.h"
29 #include "llvm/Analysis/CGSCCPassManager.h"
30 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/Localizer.h"
35 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
36 #include "llvm/CodeGen/MIRParser/MIParser.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/IntrinsicsAMDGPU.h"
41 #include "llvm/IR/LegacyPassManager.h"
42 #include "llvm/IR/PassManager.h"
43 #include "llvm/IR/PatternMatch.h"
44 #include "llvm/InitializePasses.h"
45 #include "llvm/MC/TargetRegistry.h"
46 #include "llvm/Passes/PassBuilder.h"
47 #include "llvm/Transforms/IPO.h"
48 #include "llvm/Transforms/IPO/AlwaysInliner.h"
49 #include "llvm/Transforms/IPO/GlobalDCE.h"
50 #include "llvm/Transforms/IPO/Internalize.h"
51 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include "llvm/Transforms/Scalar/GVN.h"
54 #include "llvm/Transforms/Scalar/InferAddressSpaces.h"
55 #include "llvm/Transforms/Utils.h"
56 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
57 #include "llvm/Transforms/Vectorize.h"
58 
59 using namespace llvm;
60 using namespace llvm::PatternMatch;
61 
62 namespace {
63 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
64 public:
65   SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
66     : RegisterRegAllocBase(N, D, C) {}
67 };
68 
69 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
70 public:
71   VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
72     : RegisterRegAllocBase(N, D, C) {}
73 };
74 
75 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
76                               const TargetRegisterClass &RC) {
77   return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
78 }
79 
80 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
81                               const TargetRegisterClass &RC) {
82   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
83 }
84 
85 
86 /// -{sgpr|vgpr}-regalloc=... command line option.
87 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
88 
89 /// A dummy default pass factory indicates whether the register allocator is
90 /// overridden on the command line.
91 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
92 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
93 
94 static SGPRRegisterRegAlloc
95 defaultSGPRRegAlloc("default",
96                     "pick SGPR register allocator based on -O option",
97                     useDefaultRegisterAllocator);
98 
99 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
100                RegisterPassParser<SGPRRegisterRegAlloc>>
101 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
102              cl::desc("Register allocator to use for SGPRs"));
103 
104 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
105                RegisterPassParser<VGPRRegisterRegAlloc>>
106 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
107              cl::desc("Register allocator to use for VGPRs"));
108 
109 
110 static void initializeDefaultSGPRRegisterAllocatorOnce() {
111   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
112 
113   if (!Ctor) {
114     Ctor = SGPRRegAlloc;
115     SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
116   }
117 }
118 
119 static void initializeDefaultVGPRRegisterAllocatorOnce() {
120   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
121 
122   if (!Ctor) {
123     Ctor = VGPRRegAlloc;
124     VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
125   }
126 }
127 
128 static FunctionPass *createBasicSGPRRegisterAllocator() {
129   return createBasicRegisterAllocator(onlyAllocateSGPRs);
130 }
131 
132 static FunctionPass *createGreedySGPRRegisterAllocator() {
133   return createGreedyRegisterAllocator(onlyAllocateSGPRs);
134 }
135 
136 static FunctionPass *createFastSGPRRegisterAllocator() {
137   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
138 }
139 
140 static FunctionPass *createBasicVGPRRegisterAllocator() {
141   return createBasicRegisterAllocator(onlyAllocateVGPRs);
142 }
143 
144 static FunctionPass *createGreedyVGPRRegisterAllocator() {
145   return createGreedyRegisterAllocator(onlyAllocateVGPRs);
146 }
147 
148 static FunctionPass *createFastVGPRRegisterAllocator() {
149   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
150 }
151 
152 static SGPRRegisterRegAlloc basicRegAllocSGPR(
153   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
154 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
155   "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
156 
157 static SGPRRegisterRegAlloc fastRegAllocSGPR(
158   "fast", "fast register allocator", createFastSGPRRegisterAllocator);
159 
160 
161 static VGPRRegisterRegAlloc basicRegAllocVGPR(
162   "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
163 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
164   "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
165 
166 static VGPRRegisterRegAlloc fastRegAllocVGPR(
167   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
168 }
169 
170 static cl::opt<bool> EnableSROA(
171   "amdgpu-sroa",
172   cl::desc("Run SROA after promote alloca pass"),
173   cl::ReallyHidden,
174   cl::init(true));
175 
176 static cl::opt<bool>
177 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
178                         cl::desc("Run early if-conversion"),
179                         cl::init(false));
180 
181 static cl::opt<bool>
182 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
183             cl::desc("Run pre-RA exec mask optimizations"),
184             cl::init(true));
185 
186 // Option to disable vectorizer for tests.
187 static cl::opt<bool> EnableLoadStoreVectorizer(
188   "amdgpu-load-store-vectorizer",
189   cl::desc("Enable load store vectorizer"),
190   cl::init(true),
191   cl::Hidden);
192 
193 // Option to control global loads scalarization
194 static cl::opt<bool> ScalarizeGlobal(
195   "amdgpu-scalarize-global-loads",
196   cl::desc("Enable global load scalarization"),
197   cl::init(true),
198   cl::Hidden);
199 
200 // Option to run internalize pass.
201 static cl::opt<bool> InternalizeSymbols(
202   "amdgpu-internalize-symbols",
203   cl::desc("Enable elimination of non-kernel functions and unused globals"),
204   cl::init(false),
205   cl::Hidden);
206 
207 // Option to inline all early.
208 static cl::opt<bool> EarlyInlineAll(
209   "amdgpu-early-inline-all",
210   cl::desc("Inline all functions early"),
211   cl::init(false),
212   cl::Hidden);
213 
214 static cl::opt<bool> EnableSDWAPeephole(
215   "amdgpu-sdwa-peephole",
216   cl::desc("Enable SDWA peepholer"),
217   cl::init(true));
218 
219 static cl::opt<bool> EnableDPPCombine(
220   "amdgpu-dpp-combine",
221   cl::desc("Enable DPP combiner"),
222   cl::init(true));
223 
224 // Enable address space based alias analysis
225 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
226   cl::desc("Enable AMDGPU Alias Analysis"),
227   cl::init(true));
228 
229 // Option to run late CFG structurizer
230 static cl::opt<bool, true> LateCFGStructurize(
231   "amdgpu-late-structurize",
232   cl::desc("Enable late CFG structurization"),
233   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
234   cl::Hidden);
235 
236 // Enable lib calls simplifications
237 static cl::opt<bool> EnableLibCallSimplify(
238   "amdgpu-simplify-libcall",
239   cl::desc("Enable amdgpu library simplifications"),
240   cl::init(true),
241   cl::Hidden);
242 
243 static cl::opt<bool> EnableLowerKernelArguments(
244   "amdgpu-ir-lower-kernel-arguments",
245   cl::desc("Lower kernel argument loads in IR pass"),
246   cl::init(true),
247   cl::Hidden);
248 
249 static cl::opt<bool> EnableRegReassign(
250   "amdgpu-reassign-regs",
251   cl::desc("Enable register reassign optimizations on gfx10+"),
252   cl::init(true),
253   cl::Hidden);
254 
255 static cl::opt<bool> OptVGPRLiveRange(
256     "amdgpu-opt-vgpr-liverange",
257     cl::desc("Enable VGPR liverange optimizations for if-else structure"),
258     cl::init(true), cl::Hidden);
259 
260 // Enable atomic optimization
261 static cl::opt<bool> EnableAtomicOptimizations(
262   "amdgpu-atomic-optimizations",
263   cl::desc("Enable atomic optimizations"),
264   cl::init(false),
265   cl::Hidden);
266 
267 // Enable Mode register optimization
268 static cl::opt<bool> EnableSIModeRegisterPass(
269   "amdgpu-mode-register",
270   cl::desc("Enable mode register pass"),
271   cl::init(true),
272   cl::Hidden);
273 
274 // Option is used in lit tests to prevent deadcoding of patterns inspected.
275 static cl::opt<bool>
276 EnableDCEInRA("amdgpu-dce-in-ra",
277     cl::init(true), cl::Hidden,
278     cl::desc("Enable machine DCE inside regalloc"));
279 
280 static cl::opt<bool> EnableSetWavePriority("amdgpu-set-wave-priority",
281                                            cl::desc("Adjust wave priority"),
282                                            cl::init(false), cl::Hidden);
283 
284 static cl::opt<bool> EnableScalarIRPasses(
285   "amdgpu-scalar-ir-passes",
286   cl::desc("Enable scalar IR passes"),
287   cl::init(true),
288   cl::Hidden);
289 
290 static cl::opt<bool> EnableStructurizerWorkarounds(
291     "amdgpu-enable-structurizer-workarounds",
292     cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
293     cl::Hidden);
294 
295 static cl::opt<bool> EnableLDSReplaceWithPointer(
296     "amdgpu-enable-lds-replace-with-pointer",
297     cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
298     cl::Hidden);
299 
300 static cl::opt<bool, true> EnableLowerModuleLDS(
301     "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
302     cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true),
303     cl::Hidden);
304 
305 static cl::opt<bool> EnablePreRAOptimizations(
306     "amdgpu-enable-pre-ra-optimizations",
307     cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
308     cl::Hidden);
309 
310 static cl::opt<bool> EnablePromoteKernelArguments(
311     "amdgpu-enable-promote-kernel-arguments",
312     cl::desc("Enable promotion of flat kernel pointer arguments to global"),
313     cl::Hidden, cl::init(true));
314 
315 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
316   // Register the target
317   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
318   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
319 
320   PassRegistry *PR = PassRegistry::getPassRegistry();
321   initializeR600ClauseMergePassPass(*PR);
322   initializeR600ControlFlowFinalizerPass(*PR);
323   initializeR600PacketizerPass(*PR);
324   initializeR600ExpandSpecialInstrsPassPass(*PR);
325   initializeR600VectorRegMergerPass(*PR);
326   initializeGlobalISel(*PR);
327   initializeAMDGPUDAGToDAGISelPass(*PR);
328   initializeGCNDPPCombinePass(*PR);
329   initializeSILowerI1CopiesPass(*PR);
330   initializeSILowerSGPRSpillsPass(*PR);
331   initializeSIFixSGPRCopiesPass(*PR);
332   initializeSIFixVGPRCopiesPass(*PR);
333   initializeSIFoldOperandsPass(*PR);
334   initializeSIPeepholeSDWAPass(*PR);
335   initializeSIShrinkInstructionsPass(*PR);
336   initializeSIOptimizeExecMaskingPreRAPass(*PR);
337   initializeSIOptimizeVGPRLiveRangePass(*PR);
338   initializeSILoadStoreOptimizerPass(*PR);
339   initializeAMDGPUCtorDtorLoweringPass(*PR);
340   initializeAMDGPUAlwaysInlinePass(*PR);
341   initializeAMDGPUAttributorPass(*PR);
342   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
343   initializeAMDGPUAnnotateUniformValuesPass(*PR);
344   initializeAMDGPUArgumentUsageInfoPass(*PR);
345   initializeAMDGPUAtomicOptimizerPass(*PR);
346   initializeAMDGPULowerKernelArgumentsPass(*PR);
347   initializeAMDGPUPromoteKernelArgumentsPass(*PR);
348   initializeAMDGPULowerKernelAttributesPass(*PR);
349   initializeAMDGPULowerIntrinsicsPass(*PR);
350   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
351   initializeAMDGPUPostLegalizerCombinerPass(*PR);
352   initializeAMDGPUPreLegalizerCombinerPass(*PR);
353   initializeAMDGPURegBankCombinerPass(*PR);
354   initializeAMDGPUPromoteAllocaPass(*PR);
355   initializeAMDGPUPromoteAllocaToVectorPass(*PR);
356   initializeAMDGPUCodeGenPreparePass(*PR);
357   initializeAMDGPULateCodeGenPreparePass(*PR);
358   initializeAMDGPUPropagateAttributesEarlyPass(*PR);
359   initializeAMDGPUPropagateAttributesLatePass(*PR);
360   initializeAMDGPUReplaceLDSUseWithPointerPass(*PR);
361   initializeAMDGPULowerModuleLDSPass(*PR);
362   initializeAMDGPURewriteOutArgumentsPass(*PR);
363   initializeAMDGPUUnifyMetadataPass(*PR);
364   initializeSIAnnotateControlFlowPass(*PR);
365   initializeSIInsertHardClausesPass(*PR);
366   initializeSIInsertWaitcntsPass(*PR);
367   initializeSIModeRegisterPass(*PR);
368   initializeSIWholeQuadModePass(*PR);
369   initializeSILowerControlFlowPass(*PR);
370   initializeSIPreEmitPeepholePass(*PR);
371   initializeSILateBranchLoweringPass(*PR);
372   initializeSIMemoryLegalizerPass(*PR);
373   initializeSIOptimizeExecMaskingPass(*PR);
374   initializeSIPreAllocateWWMRegsPass(*PR);
375   initializeSIFormMemoryClausesPass(*PR);
376   initializeSIPostRABundlerPass(*PR);
377   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
378   initializeAMDGPUAAWrapperPassPass(*PR);
379   initializeAMDGPUExternalAAWrapperPass(*PR);
380   initializeAMDGPUUseNativeCallsPass(*PR);
381   initializeAMDGPUSimplifyLibCallsPass(*PR);
382   initializeAMDGPUPrintfRuntimeBindingPass(*PR);
383   initializeAMDGPUResourceUsageAnalysisPass(*PR);
384   initializeGCNNSAReassignPass(*PR);
385   initializeGCNPreRAOptimizationsPass(*PR);
386 }
387 
388 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
389   return std::make_unique<AMDGPUTargetObjectFile>();
390 }
391 
392 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
393   return new SIScheduleDAGMI(C);
394 }
395 
396 static ScheduleDAGInstrs *
397 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
398   ScheduleDAGMILive *DAG =
399     new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
400   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
401   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
402   DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
403   return DAG;
404 }
405 
406 static ScheduleDAGInstrs *
407 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
408   auto DAG = new GCNIterativeScheduler(C,
409     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
410   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
411   return DAG;
412 }
413 
414 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
415   return new GCNIterativeScheduler(C,
416     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
417 }
418 
419 static ScheduleDAGInstrs *
420 createIterativeILPMachineScheduler(MachineSchedContext *C) {
421   auto DAG = new GCNIterativeScheduler(C,
422     GCNIterativeScheduler::SCHEDULE_ILP);
423   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
424   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
425   return DAG;
426 }
427 
428 static MachineSchedRegistry
429 SISchedRegistry("si", "Run SI's custom scheduler",
430                 createSIMachineScheduler);
431 
432 static MachineSchedRegistry
433 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
434                              "Run GCN scheduler to maximize occupancy",
435                              createGCNMaxOccupancyMachineScheduler);
436 
437 static MachineSchedRegistry
438 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
439   "Run GCN scheduler to maximize occupancy (experimental)",
440   createIterativeGCNMaxOccupancyMachineScheduler);
441 
442 static MachineSchedRegistry
443 GCNMinRegSchedRegistry("gcn-minreg",
444   "Run GCN iterative scheduler for minimal register usage (experimental)",
445   createMinRegScheduler);
446 
447 static MachineSchedRegistry
448 GCNILPSchedRegistry("gcn-ilp",
449   "Run GCN iterative scheduler for ILP scheduling (experimental)",
450   createIterativeILPMachineScheduler);
451 
452 static StringRef computeDataLayout(const Triple &TT) {
453   if (TT.getArch() == Triple::r600) {
454     // 32-bit pointers.
455     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
456            "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
457   }
458 
459   // 32-bit private, local, and region pointers. 64-bit global, constant and
460   // flat, non-integral buffer fat pointers.
461   return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
462          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
463          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
464          "-ni:7";
465 }
466 
467 LLVM_READNONE
468 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
469   if (!GPU.empty())
470     return GPU;
471 
472   // Need to default to a target with flat support for HSA.
473   if (TT.getArch() == Triple::amdgcn)
474     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
475 
476   return "r600";
477 }
478 
479 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
480   // The AMDGPU toolchain only supports generating shared objects, so we
481   // must always use PIC.
482   return Reloc::PIC_;
483 }
484 
485 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
486                                          StringRef CPU, StringRef FS,
487                                          TargetOptions Options,
488                                          Optional<Reloc::Model> RM,
489                                          Optional<CodeModel::Model> CM,
490                                          CodeGenOpt::Level OptLevel)
491     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
492                         FS, Options, getEffectiveRelocModel(RM),
493                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
494       TLOF(createTLOF(getTargetTriple())) {
495   initAsmInfo();
496   if (TT.getArch() == Triple::amdgcn) {
497     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
498       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
499     else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
500       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
501   }
502 }
503 
504 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
505 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
506 bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
507 
508 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
509 
510 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
511   Attribute GPUAttr = F.getFnAttribute("target-cpu");
512   return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
513 }
514 
515 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
516   Attribute FSAttr = F.getFnAttribute("target-features");
517 
518   return FSAttr.isValid() ? FSAttr.getValueAsString()
519                           : getTargetFeatureString();
520 }
521 
522 /// Predicate for Internalize pass.
523 static bool mustPreserveGV(const GlobalValue &GV) {
524   if (const Function *F = dyn_cast<Function>(&GV))
525     return F->isDeclaration() || F->getName().startswith("__asan_") ||
526            F->getName().startswith("__sanitizer_") ||
527            AMDGPU::isEntryFunctionCC(F->getCallingConv());
528 
529   GV.removeDeadConstantUsers();
530   return !GV.use_empty();
531 }
532 
533 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
534   Builder.DivergentTarget = true;
535 
536   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
537   bool Internalize = InternalizeSymbols;
538   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
539   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
540   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
541   bool PromoteKernelArguments =
542       EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less;
543 
544   if (EnableFunctionCalls) {
545     delete Builder.Inliner;
546     Builder.Inliner = createFunctionInliningPass();
547   }
548 
549   Builder.addExtension(
550     PassManagerBuilder::EP_ModuleOptimizerEarly,
551     [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
552                                                legacy::PassManagerBase &PM) {
553       if (AMDGPUAA) {
554         PM.add(createAMDGPUAAWrapperPass());
555         PM.add(createAMDGPUExternalAAWrapperPass());
556       }
557       PM.add(createAMDGPUUnifyMetadataPass());
558       PM.add(createAMDGPUPrintfRuntimeBinding());
559       if (Internalize)
560         PM.add(createInternalizePass(mustPreserveGV));
561       PM.add(createAMDGPUPropagateAttributesLatePass(this));
562       if (Internalize)
563         PM.add(createGlobalDCEPass());
564       if (EarlyInline)
565         PM.add(createAMDGPUAlwaysInlinePass(false));
566   });
567 
568   Builder.addExtension(
569     PassManagerBuilder::EP_EarlyAsPossible,
570     [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
571                                       legacy::PassManagerBase &PM) {
572       if (AMDGPUAA) {
573         PM.add(createAMDGPUAAWrapperPass());
574         PM.add(createAMDGPUExternalAAWrapperPass());
575       }
576       PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this));
577       PM.add(llvm::createAMDGPUUseNativeCallsPass());
578       if (LibCallSimplify)
579         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this));
580   });
581 
582   Builder.addExtension(
583     PassManagerBuilder::EP_CGSCCOptimizerLate,
584     [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &,
585                                         legacy::PassManagerBase &PM) {
586       // Add promote kernel arguments pass to the opt pipeline right before
587       // infer address spaces which is needed to do actual address space
588       // rewriting.
589       if (PromoteKernelArguments)
590         PM.add(createAMDGPUPromoteKernelArgumentsPass());
591 
592       // Add infer address spaces pass to the opt pipeline after inlining
593       // but before SROA to increase SROA opportunities.
594       PM.add(createInferAddressSpacesPass());
595 
596       // This should run after inlining to have any chance of doing anything,
597       // and before other cleanup optimizations.
598       PM.add(createAMDGPULowerKernelAttributesPass());
599 
600       // Promote alloca to vector before SROA and loop unroll. If we manage
601       // to eliminate allocas before unroll we may choose to unroll less.
602       if (EnableOpt)
603         PM.add(createAMDGPUPromoteAllocaToVector());
604   });
605 }
606 
607 void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
608   AAM.registerFunctionAnalysis<AMDGPUAA>();
609 }
610 
611 void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
612   PB.registerPipelineParsingCallback(
613       [this](StringRef PassName, ModulePassManager &PM,
614              ArrayRef<PassBuilder::PipelineElement>) {
615         if (PassName == "amdgpu-propagate-attributes-late") {
616           PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
617           return true;
618         }
619         if (PassName == "amdgpu-unify-metadata") {
620           PM.addPass(AMDGPUUnifyMetadataPass());
621           return true;
622         }
623         if (PassName == "amdgpu-printf-runtime-binding") {
624           PM.addPass(AMDGPUPrintfRuntimeBindingPass());
625           return true;
626         }
627         if (PassName == "amdgpu-always-inline") {
628           PM.addPass(AMDGPUAlwaysInlinePass());
629           return true;
630         }
631         if (PassName == "amdgpu-replace-lds-use-with-pointer") {
632           PM.addPass(AMDGPUReplaceLDSUseWithPointerPass());
633           return true;
634         }
635         if (PassName == "amdgpu-lower-module-lds") {
636           PM.addPass(AMDGPULowerModuleLDSPass());
637           return true;
638         }
639         return false;
640       });
641   PB.registerPipelineParsingCallback(
642       [this](StringRef PassName, FunctionPassManager &PM,
643              ArrayRef<PassBuilder::PipelineElement>) {
644         if (PassName == "amdgpu-simplifylib") {
645           PM.addPass(AMDGPUSimplifyLibCallsPass(*this));
646           return true;
647         }
648         if (PassName == "amdgpu-usenative") {
649           PM.addPass(AMDGPUUseNativeCallsPass());
650           return true;
651         }
652         if (PassName == "amdgpu-promote-alloca") {
653           PM.addPass(AMDGPUPromoteAllocaPass(*this));
654           return true;
655         }
656         if (PassName == "amdgpu-promote-alloca-to-vector") {
657           PM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
658           return true;
659         }
660         if (PassName == "amdgpu-lower-kernel-attributes") {
661           PM.addPass(AMDGPULowerKernelAttributesPass());
662           return true;
663         }
664         if (PassName == "amdgpu-propagate-attributes-early") {
665           PM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
666           return true;
667         }
668         if (PassName == "amdgpu-promote-kernel-arguments") {
669           PM.addPass(AMDGPUPromoteKernelArgumentsPass());
670           return true;
671         }
672         return false;
673       });
674 
675   PB.registerAnalysisRegistrationCallback([](FunctionAnalysisManager &FAM) {
676     FAM.registerPass([&] { return AMDGPUAA(); });
677   });
678 
679   PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
680     if (AAName == "amdgpu-aa") {
681       AAM.registerFunctionAnalysis<AMDGPUAA>();
682       return true;
683     }
684     return false;
685   });
686 
687   PB.registerPipelineStartEPCallback(
688       [this](ModulePassManager &PM, OptimizationLevel Level) {
689         FunctionPassManager FPM;
690         FPM.addPass(AMDGPUPropagateAttributesEarlyPass(*this));
691         FPM.addPass(AMDGPUUseNativeCallsPass());
692         if (EnableLibCallSimplify && Level != OptimizationLevel::O0)
693           FPM.addPass(AMDGPUSimplifyLibCallsPass(*this));
694         PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
695       });
696 
697   PB.registerPipelineEarlySimplificationEPCallback(
698       [this](ModulePassManager &PM, OptimizationLevel Level) {
699         if (Level == OptimizationLevel::O0)
700           return;
701 
702         PM.addPass(AMDGPUUnifyMetadataPass());
703         PM.addPass(AMDGPUPrintfRuntimeBindingPass());
704 
705         if (InternalizeSymbols) {
706           PM.addPass(InternalizePass(mustPreserveGV));
707         }
708         PM.addPass(AMDGPUPropagateAttributesLatePass(*this));
709         if (InternalizeSymbols) {
710           PM.addPass(GlobalDCEPass());
711         }
712         if (EarlyInlineAll && !EnableFunctionCalls)
713           PM.addPass(AMDGPUAlwaysInlinePass());
714       });
715 
716   PB.registerCGSCCOptimizerLateEPCallback(
717       [this](CGSCCPassManager &PM, OptimizationLevel Level) {
718         if (Level == OptimizationLevel::O0)
719           return;
720 
721         FunctionPassManager FPM;
722 
723         // Add promote kernel arguments pass to the opt pipeline right before
724         // infer address spaces which is needed to do actual address space
725         // rewriting.
726         if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
727             EnablePromoteKernelArguments)
728           FPM.addPass(AMDGPUPromoteKernelArgumentsPass());
729 
730         // Add infer address spaces pass to the opt pipeline after inlining
731         // but before SROA to increase SROA opportunities.
732         FPM.addPass(InferAddressSpacesPass());
733 
734         // This should run after inlining to have any chance of doing
735         // anything, and before other cleanup optimizations.
736         FPM.addPass(AMDGPULowerKernelAttributesPass());
737 
738         if (Level != OptimizationLevel::O0) {
739           // Promote alloca to vector before SROA and loop unroll. If we
740           // manage to eliminate allocas before unroll we may choose to unroll
741           // less.
742           FPM.addPass(AMDGPUPromoteAllocaToVectorPass(*this));
743         }
744 
745         PM.addPass(createCGSCCToFunctionPassAdaptor(std::move(FPM)));
746       });
747 }
748 
749 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
750   return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
751           AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
752           AddrSpace == AMDGPUAS::REGION_ADDRESS)
753              ? -1
754              : 0;
755 }
756 
757 bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
758                                               unsigned DestAS) const {
759   return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
760          AMDGPU::isFlatGlobalAddrSpace(DestAS);
761 }
762 
763 unsigned AMDGPUTargetMachine::getAssumedAddrSpace(const Value *V) const {
764   const auto *LD = dyn_cast<LoadInst>(V);
765   if (!LD)
766     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
767 
768   // It must be a generic pointer loaded.
769   assert(V->getType()->isPointerTy() &&
770          V->getType()->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS);
771 
772   const auto *Ptr = LD->getPointerOperand();
773   if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
774     return AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
775   // For a generic pointer loaded from the constant memory, it could be assumed
776   // as a global pointer since the constant memory is only populated on the
777   // host side. As implied by the offload programming model, only global
778   // pointers could be referenced on the host side.
779   return AMDGPUAS::GLOBAL_ADDRESS;
780 }
781 
782 std::pair<const Value *, unsigned>
783 AMDGPUTargetMachine::getPredicatedAddrSpace(const Value *V) const {
784   if (auto *II = dyn_cast<IntrinsicInst>(V)) {
785     switch (II->getIntrinsicID()) {
786     case Intrinsic::amdgcn_is_shared:
787       return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
788     case Intrinsic::amdgcn_is_private:
789       return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
790     default:
791       break;
792     }
793     return std::make_pair(nullptr, -1);
794   }
795   // Check the global pointer predication based on
796   // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
797   // the order of 'is_shared' and 'is_private' is not significant.
798   Value *Ptr;
799   if (match(
800           const_cast<Value *>(V),
801           m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
802                   m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
803                       m_Deferred(Ptr))))))
804     return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
805 
806   return std::make_pair(nullptr, -1);
807 }
808 
809 //===----------------------------------------------------------------------===//
810 // GCN Target Machine (SI+)
811 //===----------------------------------------------------------------------===//
812 
813 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
814                                    StringRef CPU, StringRef FS,
815                                    TargetOptions Options,
816                                    Optional<Reloc::Model> RM,
817                                    Optional<CodeModel::Model> CM,
818                                    CodeGenOpt::Level OL, bool JIT)
819     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
820 
821 const TargetSubtargetInfo *
822 GCNTargetMachine::getSubtargetImpl(const Function &F) const {
823   StringRef GPU = getGPUName(F);
824   StringRef FS = getFeatureString(F);
825 
826   SmallString<128> SubtargetKey(GPU);
827   SubtargetKey.append(FS);
828 
829   auto &I = SubtargetMap[SubtargetKey];
830   if (!I) {
831     // This needs to be done before we create a new subtarget since any
832     // creation will depend on the TM and the code generation flags on the
833     // function that reside in TargetOptions.
834     resetTargetOptions(F);
835     I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
836   }
837 
838   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
839 
840   return I.get();
841 }
842 
843 TargetTransformInfo
844 GCNTargetMachine::getTargetTransformInfo(const Function &F) const {
845   return TargetTransformInfo(GCNTTIImpl(this, F));
846 }
847 
848 //===----------------------------------------------------------------------===//
849 // AMDGPU Pass Setup
850 //===----------------------------------------------------------------------===//
851 
852 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
853   return getStandardCSEConfigForOpt(TM->getOptLevel());
854 }
855 
856 namespace {
857 
858 class GCNPassConfig final : public AMDGPUPassConfig {
859 public:
860   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
861     : AMDGPUPassConfig(TM, PM) {
862     // It is necessary to know the register usage of the entire call graph.  We
863     // allow calls without EnableAMDGPUFunctionCalls if they are marked
864     // noinline, so this is always required.
865     setRequiresCodeGenSCCOrder(true);
866     substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
867   }
868 
869   GCNTargetMachine &getGCNTargetMachine() const {
870     return getTM<GCNTargetMachine>();
871   }
872 
873   ScheduleDAGInstrs *
874   createMachineScheduler(MachineSchedContext *C) const override;
875 
876   ScheduleDAGInstrs *
877   createPostMachineScheduler(MachineSchedContext *C) const override {
878     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
879     const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
880     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
881     DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
882     return DAG;
883   }
884 
885   bool addPreISel() override;
886   void addMachineSSAOptimization() override;
887   bool addILPOpts() override;
888   bool addInstSelector() override;
889   bool addIRTranslator() override;
890   void addPreLegalizeMachineIR() override;
891   bool addLegalizeMachineIR() override;
892   void addPreRegBankSelect() override;
893   bool addRegBankSelect() override;
894   void addPreGlobalInstructionSelect() override;
895   bool addGlobalInstructionSelect() override;
896   void addFastRegAlloc() override;
897   void addOptimizedRegAlloc() override;
898 
899   FunctionPass *createSGPRAllocPass(bool Optimized);
900   FunctionPass *createVGPRAllocPass(bool Optimized);
901   FunctionPass *createRegAllocPass(bool Optimized) override;
902 
903   bool addRegAssignAndRewriteFast() override;
904   bool addRegAssignAndRewriteOptimized() override;
905 
906   void addPreRegAlloc() override;
907   bool addPreRewrite() override;
908   void addPostRegAlloc() override;
909   void addPreSched2() override;
910   void addPreEmitPass() override;
911 };
912 
913 } // end anonymous namespace
914 
915 AMDGPUPassConfig::AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
916     : TargetPassConfig(TM, PM) {
917   // Exceptions and StackMaps are not supported, so these passes will never do
918   // anything.
919   disablePass(&StackMapLivenessID);
920   disablePass(&FuncletLayoutID);
921   // Garbage collection is not supported.
922   disablePass(&GCLoweringID);
923   disablePass(&ShadowStackGCLoweringID);
924 }
925 
926 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
927   if (getOptLevel() == CodeGenOpt::Aggressive)
928     addPass(createGVNPass());
929   else
930     addPass(createEarlyCSEPass());
931 }
932 
933 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
934   addPass(createLICMPass());
935   addPass(createSeparateConstOffsetFromGEPPass());
936   addPass(createSpeculativeExecutionPass());
937   // ReassociateGEPs exposes more opportunities for SLSR. See
938   // the example in reassociate-geps-and-slsr.ll.
939   addPass(createStraightLineStrengthReducePass());
940   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
941   // EarlyCSE can reuse.
942   addEarlyCSEOrGVNPass();
943   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
944   addPass(createNaryReassociatePass());
945   // NaryReassociate on GEPs creates redundant common expressions, so run
946   // EarlyCSE after it.
947   addPass(createEarlyCSEPass());
948 }
949 
950 void AMDGPUPassConfig::addIRPasses() {
951   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
952 
953   // There is no reason to run these.
954   disablePass(&StackMapLivenessID);
955   disablePass(&FuncletLayoutID);
956   disablePass(&PatchableFunctionID);
957 
958   addPass(createAMDGPUPrintfRuntimeBinding());
959   addPass(createAMDGPUCtorDtorLoweringPass());
960 
961   // A call to propagate attributes pass in the backend in case opt was not run.
962   addPass(createAMDGPUPropagateAttributesEarlyPass(&TM));
963 
964   addPass(createAMDGPULowerIntrinsicsPass());
965 
966   // Function calls are not supported, so make sure we inline everything.
967   addPass(createAMDGPUAlwaysInlinePass());
968   addPass(createAlwaysInlinerLegacyPass());
969   // We need to add the barrier noop pass, otherwise adding the function
970   // inlining pass will cause all of the PassConfigs passes to be run
971   // one function at a time, which means if we have a nodule with two
972   // functions, then we will generate code for the first function
973   // without ever running any passes on the second.
974   addPass(createBarrierNoopPass());
975 
976   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
977   if (TM.getTargetTriple().getArch() == Triple::r600)
978     addPass(createR600OpenCLImageTypeLoweringPass());
979 
980   // Replace OpenCL enqueued block function pointers with global variables.
981   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
982 
983   // Can increase LDS used by kernel so runs before PromoteAlloca
984   if (EnableLowerModuleLDS) {
985     // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
986     // pass "amdgpu-lower-module-lds", and also it required to be run only if
987     // "amdgpu-lower-module-lds" pass is enabled.
988     if (EnableLDSReplaceWithPointer)
989       addPass(createAMDGPUReplaceLDSUseWithPointerPass());
990 
991     addPass(createAMDGPULowerModuleLDSPass());
992   }
993 
994   if (TM.getOptLevel() > CodeGenOpt::None)
995     addPass(createInferAddressSpacesPass());
996 
997   addPass(createAtomicExpandPass());
998 
999   if (TM.getOptLevel() > CodeGenOpt::None) {
1000     addPass(createAMDGPUPromoteAlloca());
1001 
1002     if (EnableSROA)
1003       addPass(createSROAPass());
1004     if (isPassEnabled(EnableScalarIRPasses))
1005       addStraightLineScalarOptimizationPasses();
1006 
1007     if (EnableAMDGPUAliasAnalysis) {
1008       addPass(createAMDGPUAAWrapperPass());
1009       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
1010                                              AAResults &AAR) {
1011         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1012           AAR.addAAResult(WrapperPass->getResult());
1013         }));
1014     }
1015 
1016     if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
1017       // TODO: May want to move later or split into an early and late one.
1018       addPass(createAMDGPUCodeGenPreparePass());
1019     }
1020   }
1021 
1022   TargetPassConfig::addIRPasses();
1023 
1024   // EarlyCSE is not always strong enough to clean up what LSR produces. For
1025   // example, GVN can combine
1026   //
1027   //   %0 = add %a, %b
1028   //   %1 = add %b, %a
1029   //
1030   // and
1031   //
1032   //   %0 = shl nsw %a, 2
1033   //   %1 = shl %a, 2
1034   //
1035   // but EarlyCSE can do neither of them.
1036   if (isPassEnabled(EnableScalarIRPasses))
1037     addEarlyCSEOrGVNPass();
1038 }
1039 
1040 void AMDGPUPassConfig::addCodeGenPrepare() {
1041   if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1042     addPass(createAMDGPUAttributorPass());
1043 
1044     // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1045     // analysis, and should be removed.
1046     addPass(createAMDGPUAnnotateKernelFeaturesPass());
1047   }
1048 
1049   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1050       EnableLowerKernelArguments)
1051     addPass(createAMDGPULowerKernelArgumentsPass());
1052 
1053   TargetPassConfig::addCodeGenPrepare();
1054 
1055   if (isPassEnabled(EnableLoadStoreVectorizer))
1056     addPass(createLoadStoreVectorizerPass());
1057 
1058   // LowerSwitch pass may introduce unreachable blocks that can
1059   // cause unexpected behavior for subsequent passes. Placing it
1060   // here seems better that these blocks would get cleaned up by
1061   // UnreachableBlockElim inserted next in the pass flow.
1062   addPass(createLowerSwitchPass());
1063 }
1064 
1065 bool AMDGPUPassConfig::addPreISel() {
1066   if (TM->getOptLevel() > CodeGenOpt::None)
1067     addPass(createFlattenCFGPass());
1068   return false;
1069 }
1070 
1071 bool AMDGPUPassConfig::addInstSelector() {
1072   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
1073   return false;
1074 }
1075 
1076 bool AMDGPUPassConfig::addGCPasses() {
1077   // Do nothing. GC is not supported.
1078   return false;
1079 }
1080 
1081 llvm::ScheduleDAGInstrs *
1082 AMDGPUPassConfig::createMachineScheduler(MachineSchedContext *C) const {
1083   ScheduleDAGMILive *DAG = createGenericSchedLive(C);
1084   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1085   return DAG;
1086 }
1087 
1088 //===----------------------------------------------------------------------===//
1089 // GCN Pass Setup
1090 //===----------------------------------------------------------------------===//
1091 
1092 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1093   MachineSchedContext *C) const {
1094   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1095   if (ST.enableSIScheduler())
1096     return createSIMachineScheduler(C);
1097   return createGCNMaxOccupancyMachineScheduler(C);
1098 }
1099 
1100 bool GCNPassConfig::addPreISel() {
1101   AMDGPUPassConfig::addPreISel();
1102 
1103   if (TM->getOptLevel() > CodeGenOpt::None)
1104     addPass(createAMDGPULateCodeGenPreparePass());
1105 
1106   if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1107     addPass(createAMDGPUAtomicOptimizerPass());
1108   }
1109 
1110   if (TM->getOptLevel() > CodeGenOpt::None)
1111     addPass(createSinkingPass());
1112 
1113   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1114   // regions formed by them.
1115   addPass(&AMDGPUUnifyDivergentExitNodesID);
1116   if (!LateCFGStructurize) {
1117     if (EnableStructurizerWorkarounds) {
1118       addPass(createFixIrreduciblePass());
1119       addPass(createUnifyLoopExitsPass());
1120     }
1121     addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1122   }
1123   addPass(createAMDGPUAnnotateUniformValues());
1124   if (!LateCFGStructurize) {
1125     addPass(createSIAnnotateControlFlowPass());
1126   }
1127   addPass(createLCSSAPass());
1128 
1129   if (TM->getOptLevel() > CodeGenOpt::Less)
1130     addPass(&AMDGPUPerfHintAnalysisID);
1131 
1132   return false;
1133 }
1134 
1135 void GCNPassConfig::addMachineSSAOptimization() {
1136   TargetPassConfig::addMachineSSAOptimization();
1137 
1138   // We want to fold operands after PeepholeOptimizer has run (or as part of
1139   // it), because it will eliminate extra copies making it easier to fold the
1140   // real source operand. We want to eliminate dead instructions after, so that
1141   // we see fewer uses of the copies. We then need to clean up the dead
1142   // instructions leftover after the operands are folded as well.
1143   //
1144   // XXX - Can we get away without running DeadMachineInstructionElim again?
1145   addPass(&SIFoldOperandsID);
1146   if (EnableDPPCombine)
1147     addPass(&GCNDPPCombineID);
1148   addPass(&SILoadStoreOptimizerID);
1149   if (isPassEnabled(EnableSDWAPeephole)) {
1150     addPass(&SIPeepholeSDWAID);
1151     addPass(&EarlyMachineLICMID);
1152     addPass(&MachineCSEID);
1153     addPass(&SIFoldOperandsID);
1154   }
1155   addPass(&DeadMachineInstructionElimID);
1156   addPass(createSIShrinkInstructionsPass());
1157 }
1158 
1159 bool GCNPassConfig::addILPOpts() {
1160   if (EnableEarlyIfConversion)
1161     addPass(&EarlyIfConverterID);
1162 
1163   TargetPassConfig::addILPOpts();
1164   return false;
1165 }
1166 
1167 bool GCNPassConfig::addInstSelector() {
1168   AMDGPUPassConfig::addInstSelector();
1169   addPass(&SIFixSGPRCopiesID);
1170   addPass(createSILowerI1CopiesPass());
1171   return false;
1172 }
1173 
1174 bool GCNPassConfig::addIRTranslator() {
1175   addPass(new IRTranslator(getOptLevel()));
1176   return false;
1177 }
1178 
1179 void GCNPassConfig::addPreLegalizeMachineIR() {
1180   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1181   addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1182   addPass(new Localizer());
1183 }
1184 
1185 bool GCNPassConfig::addLegalizeMachineIR() {
1186   addPass(new Legalizer());
1187   return false;
1188 }
1189 
1190 void GCNPassConfig::addPreRegBankSelect() {
1191   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1192   addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1193 }
1194 
1195 bool GCNPassConfig::addRegBankSelect() {
1196   addPass(new RegBankSelect());
1197   return false;
1198 }
1199 
1200 void GCNPassConfig::addPreGlobalInstructionSelect() {
1201   bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1202   addPass(createAMDGPURegBankCombiner(IsOptNone));
1203 }
1204 
1205 bool GCNPassConfig::addGlobalInstructionSelect() {
1206   addPass(new InstructionSelect(getOptLevel()));
1207   return false;
1208 }
1209 
1210 void GCNPassConfig::addPreRegAlloc() {
1211   if (LateCFGStructurize) {
1212     addPass(createAMDGPUMachineCFGStructurizerPass());
1213   }
1214 }
1215 
1216 void GCNPassConfig::addFastRegAlloc() {
1217   // FIXME: We have to disable the verifier here because of PHIElimination +
1218   // TwoAddressInstructions disabling it.
1219 
1220   // This must be run immediately after phi elimination and before
1221   // TwoAddressInstructions, otherwise the processing of the tied operand of
1222   // SI_ELSE will introduce a copy of the tied operand source after the else.
1223   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1224 
1225   insertPass(&TwoAddressInstructionPassID, &SIWholeQuadModeID);
1226   insertPass(&TwoAddressInstructionPassID, &SIPreAllocateWWMRegsID);
1227 
1228   TargetPassConfig::addFastRegAlloc();
1229 }
1230 
1231 void GCNPassConfig::addOptimizedRegAlloc() {
1232   // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1233   // instructions that cause scheduling barriers.
1234   insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1235   insertPass(&MachineSchedulerID, &SIPreAllocateWWMRegsID);
1236 
1237   if (OptExecMaskPreRA)
1238     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
1239 
1240   if (isPassEnabled(EnablePreRAOptimizations))
1241     insertPass(&RenameIndependentSubregsID, &GCNPreRAOptimizationsID);
1242 
1243   // This is not an essential optimization and it has a noticeable impact on
1244   // compilation time, so we only enable it from O2.
1245   if (TM->getOptLevel() > CodeGenOpt::Less)
1246     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
1247 
1248   // FIXME: when an instruction has a Killed operand, and the instruction is
1249   // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1250   // the register in LiveVariables, this would trigger a failure in verifier,
1251   // we should fix it and enable the verifier.
1252   if (OptVGPRLiveRange)
1253     insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID);
1254   // This must be run immediately after phi elimination and before
1255   // TwoAddressInstructions, otherwise the processing of the tied operand of
1256   // SI_ELSE will introduce a copy of the tied operand source after the else.
1257   insertPass(&PHIEliminationID, &SILowerControlFlowID);
1258 
1259   if (EnableDCEInRA)
1260     insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
1261 
1262   TargetPassConfig::addOptimizedRegAlloc();
1263 }
1264 
1265 bool GCNPassConfig::addPreRewrite() {
1266   if (EnableRegReassign)
1267     addPass(&GCNNSAReassignID);
1268   return true;
1269 }
1270 
1271 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1272   // Initialize the global default.
1273   llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1274                   initializeDefaultSGPRRegisterAllocatorOnce);
1275 
1276   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1277   if (Ctor != useDefaultRegisterAllocator)
1278     return Ctor();
1279 
1280   if (Optimized)
1281     return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1282 
1283   return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1284 }
1285 
1286 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1287   // Initialize the global default.
1288   llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1289                   initializeDefaultVGPRRegisterAllocatorOnce);
1290 
1291   RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1292   if (Ctor != useDefaultRegisterAllocator)
1293     return Ctor();
1294 
1295   if (Optimized)
1296     return createGreedyVGPRRegisterAllocator();
1297 
1298   return createFastVGPRRegisterAllocator();
1299 }
1300 
1301 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1302   llvm_unreachable("should not be used");
1303 }
1304 
1305 static const char RegAllocOptNotSupportedMessage[] =
1306   "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1307 
1308 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1309   if (!usingDefaultRegAlloc())
1310     report_fatal_error(RegAllocOptNotSupportedMessage);
1311 
1312   addPass(createSGPRAllocPass(false));
1313 
1314   // Equivalent of PEI for SGPRs.
1315   addPass(&SILowerSGPRSpillsID);
1316 
1317   addPass(createVGPRAllocPass(false));
1318   return true;
1319 }
1320 
1321 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1322   if (!usingDefaultRegAlloc())
1323     report_fatal_error(RegAllocOptNotSupportedMessage);
1324 
1325   addPass(createSGPRAllocPass(true));
1326 
1327   // Commit allocated register changes. This is mostly necessary because too
1328   // many things rely on the use lists of the physical registers, such as the
1329   // verifier. This is only necessary with allocators which use LiveIntervals,
1330   // since FastRegAlloc does the replacements itself.
1331   addPass(createVirtRegRewriter(false));
1332 
1333   // Equivalent of PEI for SGPRs.
1334   addPass(&SILowerSGPRSpillsID);
1335 
1336   addPass(createVGPRAllocPass(true));
1337 
1338   addPreRewrite();
1339   addPass(&VirtRegRewriterID);
1340 
1341   return true;
1342 }
1343 
1344 void GCNPassConfig::addPostRegAlloc() {
1345   addPass(&SIFixVGPRCopiesID);
1346   if (getOptLevel() > CodeGenOpt::None)
1347     addPass(&SIOptimizeExecMaskingID);
1348   TargetPassConfig::addPostRegAlloc();
1349 }
1350 
1351 void GCNPassConfig::addPreSched2() {
1352   if (TM->getOptLevel() > CodeGenOpt::None)
1353     addPass(createSIShrinkInstructionsPass());
1354   addPass(&SIPostRABundlerID);
1355 }
1356 
1357 void GCNPassConfig::addPreEmitPass() {
1358   addPass(createSIMemoryLegalizerPass());
1359   addPass(createSIInsertWaitcntsPass());
1360 
1361   addPass(createSIModeRegisterPass());
1362 
1363   if (getOptLevel() > CodeGenOpt::None)
1364     addPass(&SIInsertHardClausesID);
1365 
1366   addPass(&SILateBranchLoweringPassID);
1367   if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
1368     addPass(createAMDGPUSetWavePriorityPass());
1369   if (getOptLevel() > CodeGenOpt::None)
1370     addPass(&SIPreEmitPeepholeID);
1371   // The hazard recognizer that runs as part of the post-ra scheduler does not
1372   // guarantee to be able handle all hazards correctly. This is because if there
1373   // are multiple scheduling regions in a basic block, the regions are scheduled
1374   // bottom up, so when we begin to schedule a region we don't know what
1375   // instructions were emitted directly before it.
1376   //
1377   // Here we add a stand-alone hazard recognizer pass which can handle all
1378   // cases.
1379   addPass(&PostRAHazardRecognizerID);
1380   addPass(&BranchRelaxationPassID);
1381 }
1382 
1383 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
1384   return new GCNPassConfig(*this, PM);
1385 }
1386 
1387 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
1388   return new yaml::SIMachineFunctionInfo();
1389 }
1390 
1391 yaml::MachineFunctionInfo *
1392 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
1393   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1394   return new yaml::SIMachineFunctionInfo(
1395       *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1396 }
1397 
1398 bool GCNTargetMachine::parseMachineFunctionInfo(
1399     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
1400     SMDiagnostic &Error, SMRange &SourceRange) const {
1401   const yaml::SIMachineFunctionInfo &YamlMFI =
1402       static_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1403   MachineFunction &MF = PFS.MF;
1404   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1405 
1406   if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1407     return true;
1408 
1409   if (MFI->Occupancy == 0) {
1410     // Fixup the subtarget dependent default value.
1411     const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1412     MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1413   }
1414 
1415   auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1416     Register TempReg;
1417     if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1418       SourceRange = RegName.SourceRange;
1419       return true;
1420     }
1421     RegVal = TempReg;
1422 
1423     return false;
1424   };
1425 
1426   auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
1427                                    Register &RegVal) {
1428     return !RegName.Value.empty() && parseRegister(RegName, RegVal);
1429   };
1430 
1431   if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1432     return true;
1433 
1434   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1435     // Create a diagnostic for a the register string literal.
1436     const MemoryBuffer &Buffer =
1437         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1438     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1439                          RegName.Value.size(), SourceMgr::DK_Error,
1440                          "incorrect register class for field", RegName.Value,
1441                          None, None);
1442     SourceRange = RegName.SourceRange;
1443     return true;
1444   };
1445 
1446   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1447       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1448       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1449     return true;
1450 
1451   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1452       !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1453     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1454   }
1455 
1456   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1457       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1458     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1459   }
1460 
1461   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1462       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1463     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1464   }
1465 
1466   for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
1467     Register ParsedReg;
1468     if (parseRegister(YamlReg, ParsedReg))
1469       return true;
1470 
1471     MFI->reserveWWMRegister(ParsedReg);
1472   }
1473 
1474   auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1475                                    const TargetRegisterClass &RC,
1476                                    ArgDescriptor &Arg, unsigned UserSGPRs,
1477                                    unsigned SystemSGPRs) {
1478     // Skip parsing if it's not present.
1479     if (!A)
1480       return false;
1481 
1482     if (A->IsRegister) {
1483       Register Reg;
1484       if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1485         SourceRange = A->RegisterName.SourceRange;
1486         return true;
1487       }
1488       if (!RC.contains(Reg))
1489         return diagnoseRegisterClass(A->RegisterName);
1490       Arg = ArgDescriptor::createRegister(Reg);
1491     } else
1492       Arg = ArgDescriptor::createStack(A->StackOffset);
1493     // Check and apply the optional mask.
1494     if (A->Mask)
1495       Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1496 
1497     MFI->NumUserSGPRs += UserSGPRs;
1498     MFI->NumSystemSGPRs += SystemSGPRs;
1499     return false;
1500   };
1501 
1502   if (YamlMFI.ArgInfo &&
1503       (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1504                              AMDGPU::SGPR_128RegClass,
1505                              MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1506        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1507                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1508                              2, 0) ||
1509        parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1510                              MFI->ArgInfo.QueuePtr, 2, 0) ||
1511        parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1512                              AMDGPU::SReg_64RegClass,
1513                              MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1514        parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1515                              AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1516                              2, 0) ||
1517        parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1518                              AMDGPU::SReg_64RegClass,
1519                              MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1520        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1521                              AMDGPU::SGPR_32RegClass,
1522                              MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1523        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1524                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1525                              0, 1) ||
1526        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1527                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1528                              0, 1) ||
1529        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1530                              AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1531                              0, 1) ||
1532        parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1533                              AMDGPU::SGPR_32RegClass,
1534                              MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1535        parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1536                              AMDGPU::SGPR_32RegClass,
1537                              MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1538        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1539                              AMDGPU::SReg_64RegClass,
1540                              MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1541        parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1542                              AMDGPU::SReg_64RegClass,
1543                              MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1544        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1545                              AMDGPU::VGPR_32RegClass,
1546                              MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1547        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1548                              AMDGPU::VGPR_32RegClass,
1549                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1550        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1551                              AMDGPU::VGPR_32RegClass,
1552                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1553     return true;
1554 
1555   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1556   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1557   MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1558   MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1559   MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
1560   MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
1561 
1562   return false;
1563 }
1564