1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::init(false),
124   cl::Hidden);
125 
126 extern "C" void LLVMInitializeAMDGPUTarget() {
127   // Register the target
128   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
129   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
130 
131   PassRegistry *PR = PassRegistry::getPassRegistry();
132   initializeSILowerI1CopiesPass(*PR);
133   initializeSIFixSGPRCopiesPass(*PR);
134   initializeSIFixVGPRCopiesPass(*PR);
135   initializeSIFoldOperandsPass(*PR);
136   initializeSIPeepholeSDWAPass(*PR);
137   initializeSIShrinkInstructionsPass(*PR);
138   initializeSIFixControlFlowLiveIntervalsPass(*PR);
139   initializeSILoadStoreOptimizerPass(*PR);
140   initializeAMDGPUAlwaysInlinePass(*PR);
141   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
142   initializeAMDGPUAnnotateUniformValuesPass(*PR);
143   initializeAMDGPULowerIntrinsicsPass(*PR);
144   initializeAMDGPUPromoteAllocaPass(*PR);
145   initializeAMDGPUCodeGenPreparePass(*PR);
146   initializeAMDGPUUnifyMetadataPass(*PR);
147   initializeSIAnnotateControlFlowPass(*PR);
148   initializeSIInsertWaitsPass(*PR);
149   initializeSIInsertWaitcntsPass(*PR);
150   initializeSIWholeQuadModePass(*PR);
151   initializeSILowerControlFlowPass(*PR);
152   initializeSIInsertSkipsPass(*PR);
153   initializeSIMemoryLegalizerPass(*PR);
154   initializeSIDebuggerInsertNopsPass(*PR);
155   initializeSIOptimizeExecMaskingPass(*PR);
156   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
157   initializeAMDGPUAAWrapperPassPass(*PR);
158 }
159 
160 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
161   return llvm::make_unique<AMDGPUTargetObjectFile>();
162 }
163 
164 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
165   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
166 }
167 
168 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
169   return new SIScheduleDAGMI(C);
170 }
171 
172 static ScheduleDAGInstrs *
173 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
174   ScheduleDAGMILive *DAG =
175     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
176   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
177   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
178   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
179   return DAG;
180 }
181 
182 static ScheduleDAGInstrs *
183 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
184   auto DAG = new GCNIterativeScheduler(C,
185     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
186   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
187   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
188   return DAG;
189 }
190 
191 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
192   return new GCNIterativeScheduler(C,
193     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
194 }
195 
196 static MachineSchedRegistry
197 R600SchedRegistry("r600", "Run R600's custom scheduler",
198                    createR600MachineScheduler);
199 
200 static MachineSchedRegistry
201 SISchedRegistry("si", "Run SI's custom scheduler",
202                 createSIMachineScheduler);
203 
204 static MachineSchedRegistry
205 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
206                              "Run GCN scheduler to maximize occupancy",
207                              createGCNMaxOccupancyMachineScheduler);
208 
209 static MachineSchedRegistry
210 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
211   "Run GCN scheduler to maximize occupancy (experimental)",
212   createIterativeGCNMaxOccupancyMachineScheduler);
213 
214 static MachineSchedRegistry
215 GCNMinRegSchedRegistry("gcn-minreg",
216   "Run GCN iterative scheduler for minimal register usage (experimental)",
217   createMinRegScheduler);
218 
219 static StringRef computeDataLayout(const Triple &TT) {
220   if (TT.getArch() == Triple::r600) {
221     // 32-bit pointers.
222     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
223             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
224   }
225 
226   // 32-bit private, local, and region pointers. 64-bit global, constant and
227   // flat.
228   if (TT.getEnvironmentName() == "amdgiz" ||
229       TT.getEnvironmentName() == "amdgizcl")
230     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
231          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
232          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
233   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
234       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
235       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
236 }
237 
238 LLVM_READNONE
239 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
240   if (!GPU.empty())
241     return GPU;
242 
243   // HSA only supports CI+, so change the default GPU to a CI for HSA.
244   if (TT.getArch() == Triple::amdgcn)
245     return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
246 
247   return "r600";
248 }
249 
250 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
251   // The AMDGPU toolchain only supports generating shared objects, so we
252   // must always use PIC.
253   return Reloc::PIC_;
254 }
255 
256 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
257                                          StringRef CPU, StringRef FS,
258                                          TargetOptions Options,
259                                          Optional<Reloc::Model> RM,
260                                          CodeModel::Model CM,
261                                          CodeGenOpt::Level OptLevel)
262   : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
263                       FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
264     TLOF(createTLOF(getTargetTriple())) {
265   AS = AMDGPU::getAMDGPUAS(TT);
266   initAsmInfo();
267 }
268 
269 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
270 
271 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
272   Attribute GPUAttr = F.getFnAttribute("target-cpu");
273   return GPUAttr.hasAttribute(Attribute::None) ?
274     getTargetCPU() : GPUAttr.getValueAsString();
275 }
276 
277 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
278   Attribute FSAttr = F.getFnAttribute("target-features");
279 
280   return FSAttr.hasAttribute(Attribute::None) ?
281     getTargetFeatureString() :
282     FSAttr.getValueAsString();
283 }
284 
285 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
286   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
287       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
288         AAR.addAAResult(WrapperPass->getResult());
289       });
290 }
291 
292 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
293   Builder.DivergentTarget = true;
294 
295   bool Internalize = InternalizeSymbols &&
296                      (getOptLevel() > CodeGenOpt::None) &&
297                      (getTargetTriple().getArch() == Triple::amdgcn);
298   bool EarlyInline = EarlyInlineAll &&
299                      (getOptLevel() > CodeGenOpt::None);
300   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && getOptLevel() > CodeGenOpt::None;
301 
302   Builder.addExtension(
303     PassManagerBuilder::EP_ModuleOptimizerEarly,
304     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
305                                          legacy::PassManagerBase &PM) {
306       if (AMDGPUAA) {
307         PM.add(createAMDGPUAAWrapperPass());
308         PM.add(createAMDGPUExternalAAWrapperPass());
309       }
310       PM.add(createAMDGPUUnifyMetadataPass());
311       if (Internalize) {
312         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
313           if (const Function *F = dyn_cast<Function>(&GV)) {
314             if (F->isDeclaration())
315                 return true;
316             switch (F->getCallingConv()) {
317             default:
318               return false;
319             case CallingConv::AMDGPU_VS:
320             case CallingConv::AMDGPU_HS:
321             case CallingConv::AMDGPU_GS:
322             case CallingConv::AMDGPU_PS:
323             case CallingConv::AMDGPU_CS:
324             case CallingConv::AMDGPU_KERNEL:
325             case CallingConv::SPIR_KERNEL:
326               return true;
327             }
328           }
329           return !GV.use_empty();
330         }));
331         PM.add(createGlobalDCEPass());
332       }
333       if (EarlyInline)
334         PM.add(createAMDGPUAlwaysInlinePass(false));
335   });
336 
337   Builder.addExtension(
338     PassManagerBuilder::EP_EarlyAsPossible,
339     [AMDGPUAA](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
340       if (AMDGPUAA) {
341         PM.add(createAMDGPUAAWrapperPass());
342         PM.add(createAMDGPUExternalAAWrapperPass());
343       }
344   });
345 
346   Builder.addExtension(
347     PassManagerBuilder::EP_CGSCCOptimizerLate,
348     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
349       // Add infer address spaces pass to the opt pipeline after inlining
350       // but before SROA to increase SROA opportunities.
351       PM.add(createInferAddressSpacesPass());
352   });
353 }
354 
355 //===----------------------------------------------------------------------===//
356 // R600 Target Machine (R600 -> Cayman)
357 //===----------------------------------------------------------------------===//
358 
359 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
360                                      StringRef CPU, StringRef FS,
361                                      TargetOptions Options,
362                                      Optional<Reloc::Model> RM,
363                                      CodeModel::Model CM, CodeGenOpt::Level OL)
364   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
365   setRequiresStructuredCFG(true);
366 }
367 
368 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
369   const Function &F) const {
370   StringRef GPU = getGPUName(F);
371   StringRef FS = getFeatureString(F);
372 
373   SmallString<128> SubtargetKey(GPU);
374   SubtargetKey.append(FS);
375 
376   auto &I = SubtargetMap[SubtargetKey];
377   if (!I) {
378     // This needs to be done before we create a new subtarget since any
379     // creation will depend on the TM and the code generation flags on the
380     // function that reside in TargetOptions.
381     resetTargetOptions(F);
382     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
383   }
384 
385   return I.get();
386 }
387 
388 //===----------------------------------------------------------------------===//
389 // GCN Target Machine (SI+)
390 //===----------------------------------------------------------------------===//
391 
392 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
393                                    StringRef CPU, StringRef FS,
394                                    TargetOptions Options,
395                                    Optional<Reloc::Model> RM,
396                                    CodeModel::Model CM, CodeGenOpt::Level OL)
397   : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
398 
399 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
400   StringRef GPU = getGPUName(F);
401   StringRef FS = getFeatureString(F);
402 
403   SmallString<128> SubtargetKey(GPU);
404   SubtargetKey.append(FS);
405 
406   auto &I = SubtargetMap[SubtargetKey];
407   if (!I) {
408     // This needs to be done before we create a new subtarget since any
409     // creation will depend on the TM and the code generation flags on the
410     // function that reside in TargetOptions.
411     resetTargetOptions(F);
412     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
413   }
414 
415   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
416 
417   return I.get();
418 }
419 
420 //===----------------------------------------------------------------------===//
421 // AMDGPU Pass Setup
422 //===----------------------------------------------------------------------===//
423 
424 namespace {
425 
426 class AMDGPUPassConfig : public TargetPassConfig {
427 public:
428   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
429     : TargetPassConfig(TM, PM) {
430     // Exceptions and StackMaps are not supported, so these passes will never do
431     // anything.
432     disablePass(&StackMapLivenessID);
433     disablePass(&FuncletLayoutID);
434   }
435 
436   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
437     return getTM<AMDGPUTargetMachine>();
438   }
439 
440   ScheduleDAGInstrs *
441   createMachineScheduler(MachineSchedContext *C) const override {
442     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
443     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
444     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
445     return DAG;
446   }
447 
448   void addEarlyCSEOrGVNPass();
449   void addStraightLineScalarOptimizationPasses();
450   void addIRPasses() override;
451   void addCodeGenPrepare() override;
452   bool addPreISel() override;
453   bool addInstSelector() override;
454   bool addGCPasses() override;
455 };
456 
457 class R600PassConfig final : public AMDGPUPassConfig {
458 public:
459   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
460     : AMDGPUPassConfig(TM, PM) {}
461 
462   ScheduleDAGInstrs *createMachineScheduler(
463     MachineSchedContext *C) const override {
464     return createR600MachineScheduler(C);
465   }
466 
467   bool addPreISel() override;
468   void addPreRegAlloc() override;
469   void addPreSched2() override;
470   void addPreEmitPass() override;
471 };
472 
473 class GCNPassConfig final : public AMDGPUPassConfig {
474 public:
475   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
476     : AMDGPUPassConfig(TM, PM) {}
477 
478   GCNTargetMachine &getGCNTargetMachine() const {
479     return getTM<GCNTargetMachine>();
480   }
481 
482   ScheduleDAGInstrs *
483   createMachineScheduler(MachineSchedContext *C) const override;
484 
485   bool addPreISel() override;
486   void addMachineSSAOptimization() override;
487   bool addILPOpts() override;
488   bool addInstSelector() override;
489 #ifdef LLVM_BUILD_GLOBAL_ISEL
490   bool addIRTranslator() override;
491   bool addLegalizeMachineIR() override;
492   bool addRegBankSelect() override;
493   bool addGlobalInstructionSelect() override;
494 #endif
495   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
496   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
497   void addPreRegAlloc() override;
498   void addPostRegAlloc() override;
499   void addPreSched2() override;
500   void addPreEmitPass() override;
501 };
502 
503 } // end anonymous namespace
504 
505 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
506   return TargetIRAnalysis([this](const Function &F) {
507     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
508   });
509 }
510 
511 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
512   if (getOptLevel() == CodeGenOpt::Aggressive)
513     addPass(createGVNPass());
514   else
515     addPass(createEarlyCSEPass());
516 }
517 
518 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
519   addPass(createSeparateConstOffsetFromGEPPass());
520   addPass(createSpeculativeExecutionPass());
521   // ReassociateGEPs exposes more opportunites for SLSR. See
522   // the example in reassociate-geps-and-slsr.ll.
523   addPass(createStraightLineStrengthReducePass());
524   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
525   // EarlyCSE can reuse.
526   addEarlyCSEOrGVNPass();
527   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
528   addPass(createNaryReassociatePass());
529   // NaryReassociate on GEPs creates redundant common expressions, so run
530   // EarlyCSE after it.
531   addPass(createEarlyCSEPass());
532 }
533 
534 void AMDGPUPassConfig::addIRPasses() {
535   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
536 
537   // There is no reason to run these.
538   disablePass(&StackMapLivenessID);
539   disablePass(&FuncletLayoutID);
540   disablePass(&PatchableFunctionID);
541 
542   addPass(createAMDGPULowerIntrinsicsPass());
543 
544   // Function calls are not supported, so make sure we inline everything.
545   addPass(createAMDGPUAlwaysInlinePass());
546   addPass(createAlwaysInlinerLegacyPass());
547   // We need to add the barrier noop pass, otherwise adding the function
548   // inlining pass will cause all of the PassConfigs passes to be run
549   // one function at a time, which means if we have a nodule with two
550   // functions, then we will generate code for the first function
551   // without ever running any passes on the second.
552   addPass(createBarrierNoopPass());
553 
554   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
555     // TODO: May want to move later or split into an early and late one.
556 
557     addPass(createAMDGPUCodeGenPreparePass());
558   }
559 
560   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
561   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
562 
563   if (TM.getOptLevel() > CodeGenOpt::None) {
564     addPass(createInferAddressSpacesPass());
565     addPass(createAMDGPUPromoteAlloca());
566 
567     if (EnableSROA)
568       addPass(createSROAPass());
569 
570     addStraightLineScalarOptimizationPasses();
571 
572     if (EnableAMDGPUAliasAnalysis) {
573       addPass(createAMDGPUAAWrapperPass());
574       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
575                                              AAResults &AAR) {
576         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
577           AAR.addAAResult(WrapperPass->getResult());
578         }));
579     }
580   }
581 
582   TargetPassConfig::addIRPasses();
583 
584   // EarlyCSE is not always strong enough to clean up what LSR produces. For
585   // example, GVN can combine
586   //
587   //   %0 = add %a, %b
588   //   %1 = add %b, %a
589   //
590   // and
591   //
592   //   %0 = shl nsw %a, 2
593   //   %1 = shl %a, 2
594   //
595   // but EarlyCSE can do neither of them.
596   if (getOptLevel() != CodeGenOpt::None)
597     addEarlyCSEOrGVNPass();
598 }
599 
600 void AMDGPUPassConfig::addCodeGenPrepare() {
601   TargetPassConfig::addCodeGenPrepare();
602 
603   if (EnableLoadStoreVectorizer)
604     addPass(createLoadStoreVectorizerPass());
605 }
606 
607 bool AMDGPUPassConfig::addPreISel() {
608   addPass(createFlattenCFGPass());
609   return false;
610 }
611 
612 bool AMDGPUPassConfig::addInstSelector() {
613   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
614   return false;
615 }
616 
617 bool AMDGPUPassConfig::addGCPasses() {
618   // Do nothing. GC is not supported.
619   return false;
620 }
621 
622 //===----------------------------------------------------------------------===//
623 // R600 Pass Setup
624 //===----------------------------------------------------------------------===//
625 
626 bool R600PassConfig::addPreISel() {
627   AMDGPUPassConfig::addPreISel();
628 
629   if (EnableR600StructurizeCFG)
630     addPass(createStructurizeCFGPass());
631   return false;
632 }
633 
634 void R600PassConfig::addPreRegAlloc() {
635   addPass(createR600VectorRegMerger());
636 }
637 
638 void R600PassConfig::addPreSched2() {
639   addPass(createR600EmitClauseMarkers(), false);
640   if (EnableR600IfConvert)
641     addPass(&IfConverterID, false);
642   addPass(createR600ClauseMergePass(), false);
643 }
644 
645 void R600PassConfig::addPreEmitPass() {
646   addPass(createAMDGPUCFGStructurizerPass(), false);
647   addPass(createR600ExpandSpecialInstrsPass(), false);
648   addPass(&FinalizeMachineBundlesID, false);
649   addPass(createR600Packetizer(), false);
650   addPass(createR600ControlFlowFinalizer(), false);
651 }
652 
653 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
654   return new R600PassConfig(*this, PM);
655 }
656 
657 //===----------------------------------------------------------------------===//
658 // GCN Pass Setup
659 //===----------------------------------------------------------------------===//
660 
661 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
662   MachineSchedContext *C) const {
663   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
664   if (ST.enableSIScheduler())
665     return createSIMachineScheduler(C);
666   return createGCNMaxOccupancyMachineScheduler(C);
667 }
668 
669 bool GCNPassConfig::addPreISel() {
670   AMDGPUPassConfig::addPreISel();
671 
672   // FIXME: We need to run a pass to propagate the attributes when calls are
673   // supported.
674   addPass(createAMDGPUAnnotateKernelFeaturesPass());
675 
676   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
677   // regions formed by them.
678   addPass(&AMDGPUUnifyDivergentExitNodesID);
679   if (!LateCFGStructurize) {
680     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
681   }
682   addPass(createSinkingPass());
683   addPass(createAMDGPUAnnotateUniformValues());
684   if (!LateCFGStructurize) {
685     addPass(createSIAnnotateControlFlowPass());
686   }
687 
688   return false;
689 }
690 
691 void GCNPassConfig::addMachineSSAOptimization() {
692   TargetPassConfig::addMachineSSAOptimization();
693 
694   // We want to fold operands after PeepholeOptimizer has run (or as part of
695   // it), because it will eliminate extra copies making it easier to fold the
696   // real source operand. We want to eliminate dead instructions after, so that
697   // we see fewer uses of the copies. We then need to clean up the dead
698   // instructions leftover after the operands are folded as well.
699   //
700   // XXX - Can we get away without running DeadMachineInstructionElim again?
701   addPass(&SIFoldOperandsID);
702   addPass(&DeadMachineInstructionElimID);
703   addPass(&SILoadStoreOptimizerID);
704   if (EnableSDWAPeephole) {
705     addPass(&SIPeepholeSDWAID);
706     addPass(&MachineLICMID);
707     addPass(&MachineCSEID);
708     addPass(&SIFoldOperandsID);
709     addPass(&DeadMachineInstructionElimID);
710   }
711   addPass(createSIShrinkInstructionsPass());
712 }
713 
714 bool GCNPassConfig::addILPOpts() {
715   if (EnableEarlyIfConversion)
716     addPass(&EarlyIfConverterID);
717 
718   TargetPassConfig::addILPOpts();
719   return false;
720 }
721 
722 bool GCNPassConfig::addInstSelector() {
723   AMDGPUPassConfig::addInstSelector();
724   addPass(createSILowerI1CopiesPass());
725   addPass(&SIFixSGPRCopiesID);
726   return false;
727 }
728 
729 #ifdef LLVM_BUILD_GLOBAL_ISEL
730 bool GCNPassConfig::addIRTranslator() {
731   addPass(new IRTranslator());
732   return false;
733 }
734 
735 bool GCNPassConfig::addLegalizeMachineIR() {
736   addPass(new Legalizer());
737   return false;
738 }
739 
740 bool GCNPassConfig::addRegBankSelect() {
741   addPass(new RegBankSelect());
742   return false;
743 }
744 
745 bool GCNPassConfig::addGlobalInstructionSelect() {
746   addPass(new InstructionSelect());
747   return false;
748 }
749 
750 #endif
751 
752 void GCNPassConfig::addPreRegAlloc() {
753   if (LateCFGStructurize) {
754     addPass(createAMDGPUMachineCFGStructurizerPass());
755   }
756   addPass(createSIWholeQuadModePass());
757 }
758 
759 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
760   // FIXME: We have to disable the verifier here because of PHIElimination +
761   // TwoAddressInstructions disabling it.
762 
763   // This must be run immediately after phi elimination and before
764   // TwoAddressInstructions, otherwise the processing of the tied operand of
765   // SI_ELSE will introduce a copy of the tied operand source after the else.
766   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
767 
768   TargetPassConfig::addFastRegAlloc(RegAllocPass);
769 }
770 
771 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
772   // This needs to be run directly before register allocation because earlier
773   // passes might recompute live intervals.
774   insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
775 
776   // This must be run immediately after phi elimination and before
777   // TwoAddressInstructions, otherwise the processing of the tied operand of
778   // SI_ELSE will introduce a copy of the tied operand source after the else.
779   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
780 
781   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
782 }
783 
784 void GCNPassConfig::addPostRegAlloc() {
785   addPass(&SIFixVGPRCopiesID);
786   addPass(&SIOptimizeExecMaskingID);
787   TargetPassConfig::addPostRegAlloc();
788 }
789 
790 void GCNPassConfig::addPreSched2() {
791 }
792 
793 void GCNPassConfig::addPreEmitPass() {
794   // The hazard recognizer that runs as part of the post-ra scheduler does not
795   // guarantee to be able handle all hazards correctly. This is because if there
796   // are multiple scheduling regions in a basic block, the regions are scheduled
797   // bottom up, so when we begin to schedule a region we don't know what
798   // instructions were emitted directly before it.
799   //
800   // Here we add a stand-alone hazard recognizer pass which can handle all
801   // cases.
802   addPass(&PostRAHazardRecognizerID);
803 
804   if (EnableSIInsertWaitcntsPass)
805     addPass(createSIInsertWaitcntsPass());
806   else
807     addPass(createSIInsertWaitsPass());
808   addPass(createSIShrinkInstructionsPass());
809   addPass(&SIInsertSkipsPassID);
810   addPass(createSIMemoryLegalizerPass());
811   addPass(createSIDebuggerInsertNopsPass());
812   addPass(&BranchRelaxationPassID);
813 }
814 
815 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
816   return new GCNPassConfig(*this, PM);
817 }
818 
819