1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Utils.h"
49 #include "llvm/Transforms/Vectorize.h"
50 #include <memory>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableR600StructurizeCFG(
55   "r600-ir-structurize",
56   cl::desc("Use StructurizeCFG IR pass"),
57   cl::init(true));
58 
59 static cl::opt<bool> EnableSROA(
60   "amdgpu-sroa",
61   cl::desc("Run SROA after promote alloca pass"),
62   cl::ReallyHidden,
63   cl::init(true));
64 
65 static cl::opt<bool>
66 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
67                         cl::desc("Run early if-conversion"),
68                         cl::init(false));
69 
70 static cl::opt<bool> EnableR600IfConvert(
71   "r600-if-convert",
72   cl::desc("Use if conversion pass"),
73   cl::ReallyHidden,
74   cl::init(true));
75 
76 // Option to disable vectorizer for tests.
77 static cl::opt<bool> EnableLoadStoreVectorizer(
78   "amdgpu-load-store-vectorizer",
79   cl::desc("Enable load store vectorizer"),
80   cl::init(true),
81   cl::Hidden);
82 
83 // Option to control global loads scalarization
84 static cl::opt<bool> ScalarizeGlobal(
85   "amdgpu-scalarize-global-loads",
86   cl::desc("Enable global load scalarization"),
87   cl::init(true),
88   cl::Hidden);
89 
90 // Option to run internalize pass.
91 static cl::opt<bool> InternalizeSymbols(
92   "amdgpu-internalize-symbols",
93   cl::desc("Enable elimination of non-kernel functions and unused globals"),
94   cl::init(false),
95   cl::Hidden);
96 
97 // Option to inline all early.
98 static cl::opt<bool> EarlyInlineAll(
99   "amdgpu-early-inline-all",
100   cl::desc("Inline all functions early"),
101   cl::init(false),
102   cl::Hidden);
103 
104 static cl::opt<bool> EnableSDWAPeephole(
105   "amdgpu-sdwa-peephole",
106   cl::desc("Enable SDWA peepholer"),
107   cl::init(true));
108 
109 // Enable address space based alias analysis
110 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
111   cl::desc("Enable AMDGPU Alias Analysis"),
112   cl::init(true));
113 
114 // Option to run late CFG structurizer
115 static cl::opt<bool, true> LateCFGStructurize(
116   "amdgpu-late-structurize",
117   cl::desc("Enable late CFG structurization"),
118   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
119   cl::Hidden);
120 
121 static cl::opt<bool, true> EnableAMDGPUFunctionCalls(
122   "amdgpu-function-calls",
123   cl::desc("Enable AMDGPU function call support"),
124   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
125   cl::init(false),
126   cl::Hidden);
127 
128 // Enable lib calls simplifications
129 static cl::opt<bool> EnableLibCallSimplify(
130   "amdgpu-simplify-libcall",
131   cl::desc("Enable amdgpu library simplifications"),
132   cl::init(true),
133   cl::Hidden);
134 
135 static cl::opt<bool> EnableLowerKernelArguments(
136   "amdgpu-ir-lower-kernel-arguments",
137   cl::desc("Lower kernel argument loads in IR pass"),
138   cl::init(true),
139   cl::Hidden);
140 
141 // Enable atomic optimization
142 static cl::opt<bool> EnableAtomicOptimizations(
143   "amdgpu-atomic-optimizations",
144   cl::desc("Enable atomic optimizations"),
145   cl::init(false),
146   cl::Hidden);
147 
148 extern "C" void LLVMInitializeAMDGPUTarget() {
149   // Register the target
150   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
151   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
152 
153   PassRegistry *PR = PassRegistry::getPassRegistry();
154   initializeR600ClauseMergePassPass(*PR);
155   initializeR600ControlFlowFinalizerPass(*PR);
156   initializeR600PacketizerPass(*PR);
157   initializeR600ExpandSpecialInstrsPassPass(*PR);
158   initializeR600VectorRegMergerPass(*PR);
159   initializeGlobalISel(*PR);
160   initializeAMDGPUDAGToDAGISelPass(*PR);
161   initializeSILowerI1CopiesPass(*PR);
162   initializeSIFixSGPRCopiesPass(*PR);
163   initializeSIFixVGPRCopiesPass(*PR);
164   initializeSIFoldOperandsPass(*PR);
165   initializeSIPeepholeSDWAPass(*PR);
166   initializeSIShrinkInstructionsPass(*PR);
167   initializeSIOptimizeExecMaskingPreRAPass(*PR);
168   initializeSILoadStoreOptimizerPass(*PR);
169   initializeAMDGPUFixFunctionBitcastsPass(*PR);
170   initializeAMDGPUAlwaysInlinePass(*PR);
171   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
172   initializeAMDGPUAnnotateUniformValuesPass(*PR);
173   initializeAMDGPUArgumentUsageInfoPass(*PR);
174   initializeAMDGPUAtomicOptimizerPass(*PR);
175   initializeAMDGPULowerKernelArgumentsPass(*PR);
176   initializeAMDGPULowerKernelAttributesPass(*PR);
177   initializeAMDGPULowerIntrinsicsPass(*PR);
178   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
179   initializeAMDGPUPromoteAllocaPass(*PR);
180   initializeAMDGPUCodeGenPreparePass(*PR);
181   initializeAMDGPURewriteOutArgumentsPass(*PR);
182   initializeAMDGPUUnifyMetadataPass(*PR);
183   initializeSIAnnotateControlFlowPass(*PR);
184   initializeSIInsertWaitcntsPass(*PR);
185   initializeSIWholeQuadModePass(*PR);
186   initializeSILowerControlFlowPass(*PR);
187   initializeSIInsertSkipsPass(*PR);
188   initializeSIMemoryLegalizerPass(*PR);
189   initializeSIDebuggerInsertNopsPass(*PR);
190   initializeSIOptimizeExecMaskingPass(*PR);
191   initializeSIFixWWMLivenessPass(*PR);
192   initializeSIFormMemoryClausesPass(*PR);
193   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
194   initializeAMDGPUAAWrapperPassPass(*PR);
195   initializeAMDGPUUseNativeCallsPass(*PR);
196   initializeAMDGPUSimplifyLibCallsPass(*PR);
197   initializeAMDGPUInlinerPass(*PR);
198 }
199 
200 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
201   return llvm::make_unique<AMDGPUTargetObjectFile>();
202 }
203 
204 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
205   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
206 }
207 
208 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
209   return new SIScheduleDAGMI(C);
210 }
211 
212 static ScheduleDAGInstrs *
213 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
214   ScheduleDAGMILive *DAG =
215     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
216   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
217   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
218   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
219   return DAG;
220 }
221 
222 static ScheduleDAGInstrs *
223 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
224   auto DAG = new GCNIterativeScheduler(C,
225     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
226   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
227   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
228   return DAG;
229 }
230 
231 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
232   return new GCNIterativeScheduler(C,
233     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
234 }
235 
236 static ScheduleDAGInstrs *
237 createIterativeILPMachineScheduler(MachineSchedContext *C) {
238   auto DAG = new GCNIterativeScheduler(C,
239     GCNIterativeScheduler::SCHEDULE_ILP);
240   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
241   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
242   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
243   return DAG;
244 }
245 
246 static MachineSchedRegistry
247 R600SchedRegistry("r600", "Run R600's custom scheduler",
248                    createR600MachineScheduler);
249 
250 static MachineSchedRegistry
251 SISchedRegistry("si", "Run SI's custom scheduler",
252                 createSIMachineScheduler);
253 
254 static MachineSchedRegistry
255 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
256                              "Run GCN scheduler to maximize occupancy",
257                              createGCNMaxOccupancyMachineScheduler);
258 
259 static MachineSchedRegistry
260 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
261   "Run GCN scheduler to maximize occupancy (experimental)",
262   createIterativeGCNMaxOccupancyMachineScheduler);
263 
264 static MachineSchedRegistry
265 GCNMinRegSchedRegistry("gcn-minreg",
266   "Run GCN iterative scheduler for minimal register usage (experimental)",
267   createMinRegScheduler);
268 
269 static MachineSchedRegistry
270 GCNILPSchedRegistry("gcn-ilp",
271   "Run GCN iterative scheduler for ILP scheduling (experimental)",
272   createIterativeILPMachineScheduler);
273 
274 static StringRef computeDataLayout(const Triple &TT) {
275   if (TT.getArch() == Triple::r600) {
276     // 32-bit pointers.
277       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
278              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
279   }
280 
281   // 32-bit private, local, and region pointers. 64-bit global, constant and
282   // flat.
283     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
284          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
285          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
286 }
287 
288 LLVM_READNONE
289 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
290   if (!GPU.empty())
291     return GPU;
292 
293   if (TT.getArch() == Triple::amdgcn)
294     return "generic";
295 
296   return "r600";
297 }
298 
299 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
300   // The AMDGPU toolchain only supports generating shared objects, so we
301   // must always use PIC.
302   return Reloc::PIC_;
303 }
304 
305 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
306   if (CM)
307     return *CM;
308   return CodeModel::Small;
309 }
310 
311 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
312                                          StringRef CPU, StringRef FS,
313                                          TargetOptions Options,
314                                          Optional<Reloc::Model> RM,
315                                          Optional<CodeModel::Model> CM,
316                                          CodeGenOpt::Level OptLevel)
317     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
318                         FS, Options, getEffectiveRelocModel(RM),
319                         getEffectiveCodeModel(CM), OptLevel),
320       TLOF(createTLOF(getTargetTriple())) {
321   initAsmInfo();
322 }
323 
324 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
325 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
326 
327 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
328 
329 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
330   Attribute GPUAttr = F.getFnAttribute("target-cpu");
331   return GPUAttr.hasAttribute(Attribute::None) ?
332     getTargetCPU() : GPUAttr.getValueAsString();
333 }
334 
335 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
336   Attribute FSAttr = F.getFnAttribute("target-features");
337 
338   return FSAttr.hasAttribute(Attribute::None) ?
339     getTargetFeatureString() :
340     FSAttr.getValueAsString();
341 }
342 
343 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
344   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
345       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
346         AAR.addAAResult(WrapperPass->getResult());
347       });
348 }
349 
350 /// Predicate for Internalize pass.
351 static bool mustPreserveGV(const GlobalValue &GV) {
352   if (const Function *F = dyn_cast<Function>(&GV))
353     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
354 
355   return !GV.use_empty();
356 }
357 
358 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
359   Builder.DivergentTarget = true;
360 
361   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
362   bool Internalize = InternalizeSymbols;
363   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableAMDGPUFunctionCalls;
364   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
365   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
366 
367   if (EnableAMDGPUFunctionCalls) {
368     delete Builder.Inliner;
369     Builder.Inliner = createAMDGPUFunctionInliningPass();
370   }
371 
372   Builder.addExtension(
373     PassManagerBuilder::EP_ModuleOptimizerEarly,
374     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
375                                          legacy::PassManagerBase &PM) {
376       if (AMDGPUAA) {
377         PM.add(createAMDGPUAAWrapperPass());
378         PM.add(createAMDGPUExternalAAWrapperPass());
379       }
380       PM.add(createAMDGPUUnifyMetadataPass());
381       if (Internalize) {
382         PM.add(createInternalizePass(mustPreserveGV));
383         PM.add(createGlobalDCEPass());
384       }
385       if (EarlyInline)
386         PM.add(createAMDGPUAlwaysInlinePass(false));
387   });
388 
389   const auto &Opt = Options;
390   Builder.addExtension(
391     PassManagerBuilder::EP_EarlyAsPossible,
392     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
393                                       legacy::PassManagerBase &PM) {
394       if (AMDGPUAA) {
395         PM.add(createAMDGPUAAWrapperPass());
396         PM.add(createAMDGPUExternalAAWrapperPass());
397       }
398       PM.add(llvm::createAMDGPUUseNativeCallsPass());
399       if (LibCallSimplify)
400         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
401   });
402 
403   Builder.addExtension(
404     PassManagerBuilder::EP_CGSCCOptimizerLate,
405     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
406       // Add infer address spaces pass to the opt pipeline after inlining
407       // but before SROA to increase SROA opportunities.
408       PM.add(createInferAddressSpacesPass());
409 
410       // This should run after inlining to have any chance of doing anything,
411       // and before other cleanup optimizations.
412       PM.add(createAMDGPULowerKernelAttributesPass());
413   });
414 }
415 
416 //===----------------------------------------------------------------------===//
417 // R600 Target Machine (R600 -> Cayman)
418 //===----------------------------------------------------------------------===//
419 
420 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
421                                      StringRef CPU, StringRef FS,
422                                      TargetOptions Options,
423                                      Optional<Reloc::Model> RM,
424                                      Optional<CodeModel::Model> CM,
425                                      CodeGenOpt::Level OL, bool JIT)
426     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
427   setRequiresStructuredCFG(true);
428 }
429 
430 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
431   const Function &F) const {
432   StringRef GPU = getGPUName(F);
433   StringRef FS = getFeatureString(F);
434 
435   SmallString<128> SubtargetKey(GPU);
436   SubtargetKey.append(FS);
437 
438   auto &I = SubtargetMap[SubtargetKey];
439   if (!I) {
440     // This needs to be done before we create a new subtarget since any
441     // creation will depend on the TM and the code generation flags on the
442     // function that reside in TargetOptions.
443     resetTargetOptions(F);
444     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
445   }
446 
447   return I.get();
448 }
449 
450 TargetTransformInfo
451 R600TargetMachine::getTargetTransformInfo(const Function &F) {
452   return TargetTransformInfo(R600TTIImpl(this, F));
453 }
454 
455 //===----------------------------------------------------------------------===//
456 // GCN Target Machine (SI+)
457 //===----------------------------------------------------------------------===//
458 
459 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
460                                    StringRef CPU, StringRef FS,
461                                    TargetOptions Options,
462                                    Optional<Reloc::Model> RM,
463                                    Optional<CodeModel::Model> CM,
464                                    CodeGenOpt::Level OL, bool JIT)
465     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
466 
467 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
468   StringRef GPU = getGPUName(F);
469   StringRef FS = getFeatureString(F);
470 
471   SmallString<128> SubtargetKey(GPU);
472   SubtargetKey.append(FS);
473 
474   auto &I = SubtargetMap[SubtargetKey];
475   if (!I) {
476     // This needs to be done before we create a new subtarget since any
477     // creation will depend on the TM and the code generation flags on the
478     // function that reside in TargetOptions.
479     resetTargetOptions(F);
480     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
481   }
482 
483   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
484 
485   return I.get();
486 }
487 
488 TargetTransformInfo
489 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
490   return TargetTransformInfo(GCNTTIImpl(this, F));
491 }
492 
493 //===----------------------------------------------------------------------===//
494 // AMDGPU Pass Setup
495 //===----------------------------------------------------------------------===//
496 
497 namespace {
498 
499 class AMDGPUPassConfig : public TargetPassConfig {
500 public:
501   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
502     : TargetPassConfig(TM, PM) {
503     // Exceptions and StackMaps are not supported, so these passes will never do
504     // anything.
505     disablePass(&StackMapLivenessID);
506     disablePass(&FuncletLayoutID);
507   }
508 
509   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
510     return getTM<AMDGPUTargetMachine>();
511   }
512 
513   ScheduleDAGInstrs *
514   createMachineScheduler(MachineSchedContext *C) const override {
515     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
516     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
517     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
518     return DAG;
519   }
520 
521   void addEarlyCSEOrGVNPass();
522   void addStraightLineScalarOptimizationPasses();
523   void addIRPasses() override;
524   void addCodeGenPrepare() override;
525   bool addPreISel() override;
526   bool addInstSelector() override;
527   bool addGCPasses() override;
528 };
529 
530 class R600PassConfig final : public AMDGPUPassConfig {
531 public:
532   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
533     : AMDGPUPassConfig(TM, PM) {}
534 
535   ScheduleDAGInstrs *createMachineScheduler(
536     MachineSchedContext *C) const override {
537     return createR600MachineScheduler(C);
538   }
539 
540   bool addPreISel() override;
541   bool addInstSelector() override;
542   void addPreRegAlloc() override;
543   void addPreSched2() override;
544   void addPreEmitPass() override;
545 };
546 
547 class GCNPassConfig final : public AMDGPUPassConfig {
548 public:
549   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
550     : AMDGPUPassConfig(TM, PM) {
551     // It is necessary to know the register usage of the entire call graph.  We
552     // allow calls without EnableAMDGPUFunctionCalls if they are marked
553     // noinline, so this is always required.
554     setRequiresCodeGenSCCOrder(true);
555   }
556 
557   GCNTargetMachine &getGCNTargetMachine() const {
558     return getTM<GCNTargetMachine>();
559   }
560 
561   ScheduleDAGInstrs *
562   createMachineScheduler(MachineSchedContext *C) const override;
563 
564   bool addPreISel() override;
565   void addMachineSSAOptimization() override;
566   bool addILPOpts() override;
567   bool addInstSelector() override;
568   bool addIRTranslator() override;
569   bool addLegalizeMachineIR() override;
570   bool addRegBankSelect() override;
571   bool addGlobalInstructionSelect() override;
572   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
573   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
574   void addPreRegAlloc() override;
575   void addPostRegAlloc() override;
576   void addPreSched2() override;
577   void addPreEmitPass() override;
578 };
579 
580 } // end anonymous namespace
581 
582 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
583   if (getOptLevel() == CodeGenOpt::Aggressive)
584     addPass(createGVNPass());
585   else
586     addPass(createEarlyCSEPass());
587 }
588 
589 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
590   addPass(createLICMPass());
591   addPass(createSeparateConstOffsetFromGEPPass());
592   addPass(createSpeculativeExecutionPass());
593   // ReassociateGEPs exposes more opportunites for SLSR. See
594   // the example in reassociate-geps-and-slsr.ll.
595   addPass(createStraightLineStrengthReducePass());
596   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
597   // EarlyCSE can reuse.
598   addEarlyCSEOrGVNPass();
599   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
600   addPass(createNaryReassociatePass());
601   // NaryReassociate on GEPs creates redundant common expressions, so run
602   // EarlyCSE after it.
603   addPass(createEarlyCSEPass());
604 }
605 
606 void AMDGPUPassConfig::addIRPasses() {
607   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
608 
609   // There is no reason to run these.
610   disablePass(&StackMapLivenessID);
611   disablePass(&FuncletLayoutID);
612   disablePass(&PatchableFunctionID);
613 
614   addPass(createAtomicExpandPass());
615 
616   // This must occur before inlining, as the inliner will not look through
617   // bitcast calls.
618   addPass(createAMDGPUFixFunctionBitcastsPass());
619 
620   addPass(createAMDGPULowerIntrinsicsPass());
621 
622   // Function calls are not supported, so make sure we inline everything.
623   addPass(createAMDGPUAlwaysInlinePass());
624   addPass(createAlwaysInlinerLegacyPass());
625   // We need to add the barrier noop pass, otherwise adding the function
626   // inlining pass will cause all of the PassConfigs passes to be run
627   // one function at a time, which means if we have a nodule with two
628   // functions, then we will generate code for the first function
629   // without ever running any passes on the second.
630   addPass(createBarrierNoopPass());
631 
632   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
633     // TODO: May want to move later or split into an early and late one.
634 
635     addPass(createAMDGPUCodeGenPreparePass());
636   }
637 
638   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
639   if (TM.getTargetTriple().getArch() == Triple::r600)
640     addPass(createR600OpenCLImageTypeLoweringPass());
641 
642   // Replace OpenCL enqueued block function pointers with global variables.
643   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
644 
645   if (TM.getOptLevel() > CodeGenOpt::None) {
646     addPass(createInferAddressSpacesPass());
647     addPass(createAMDGPUPromoteAlloca());
648 
649     if (EnableSROA)
650       addPass(createSROAPass());
651 
652     addStraightLineScalarOptimizationPasses();
653 
654     if (EnableAMDGPUAliasAnalysis) {
655       addPass(createAMDGPUAAWrapperPass());
656       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
657                                              AAResults &AAR) {
658         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
659           AAR.addAAResult(WrapperPass->getResult());
660         }));
661     }
662   }
663 
664   TargetPassConfig::addIRPasses();
665 
666   // EarlyCSE is not always strong enough to clean up what LSR produces. For
667   // example, GVN can combine
668   //
669   //   %0 = add %a, %b
670   //   %1 = add %b, %a
671   //
672   // and
673   //
674   //   %0 = shl nsw %a, 2
675   //   %1 = shl %a, 2
676   //
677   // but EarlyCSE can do neither of them.
678   if (getOptLevel() != CodeGenOpt::None)
679     addEarlyCSEOrGVNPass();
680 }
681 
682 void AMDGPUPassConfig::addCodeGenPrepare() {
683   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
684       EnableLowerKernelArguments)
685     addPass(createAMDGPULowerKernelArgumentsPass());
686 
687   TargetPassConfig::addCodeGenPrepare();
688 
689   if (EnableLoadStoreVectorizer)
690     addPass(createLoadStoreVectorizerPass());
691 }
692 
693 bool AMDGPUPassConfig::addPreISel() {
694   addPass(createLowerSwitchPass());
695   addPass(createFlattenCFGPass());
696   return false;
697 }
698 
699 bool AMDGPUPassConfig::addInstSelector() {
700   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
701   return false;
702 }
703 
704 bool AMDGPUPassConfig::addGCPasses() {
705   // Do nothing. GC is not supported.
706   return false;
707 }
708 
709 //===----------------------------------------------------------------------===//
710 // R600 Pass Setup
711 //===----------------------------------------------------------------------===//
712 
713 bool R600PassConfig::addPreISel() {
714   AMDGPUPassConfig::addPreISel();
715 
716   if (EnableR600StructurizeCFG)
717     addPass(createStructurizeCFGPass());
718   return false;
719 }
720 
721 bool R600PassConfig::addInstSelector() {
722   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
723   return false;
724 }
725 
726 void R600PassConfig::addPreRegAlloc() {
727   addPass(createR600VectorRegMerger());
728 }
729 
730 void R600PassConfig::addPreSched2() {
731   addPass(createR600EmitClauseMarkers(), false);
732   if (EnableR600IfConvert)
733     addPass(&IfConverterID, false);
734   addPass(createR600ClauseMergePass(), false);
735 }
736 
737 void R600PassConfig::addPreEmitPass() {
738   addPass(createAMDGPUCFGStructurizerPass(), false);
739   addPass(createR600ExpandSpecialInstrsPass(), false);
740   addPass(&FinalizeMachineBundlesID, false);
741   addPass(createR600Packetizer(), false);
742   addPass(createR600ControlFlowFinalizer(), false);
743 }
744 
745 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
746   return new R600PassConfig(*this, PM);
747 }
748 
749 //===----------------------------------------------------------------------===//
750 // GCN Pass Setup
751 //===----------------------------------------------------------------------===//
752 
753 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
754   MachineSchedContext *C) const {
755   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
756   if (ST.enableSIScheduler())
757     return createSIMachineScheduler(C);
758   return createGCNMaxOccupancyMachineScheduler(C);
759 }
760 
761 bool GCNPassConfig::addPreISel() {
762   AMDGPUPassConfig::addPreISel();
763 
764   if (EnableAtomicOptimizations) {
765     addPass(createAMDGPUAtomicOptimizerPass());
766   }
767 
768   // FIXME: We need to run a pass to propagate the attributes when calls are
769   // supported.
770   addPass(createAMDGPUAnnotateKernelFeaturesPass());
771 
772   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
773   // regions formed by them.
774   addPass(&AMDGPUUnifyDivergentExitNodesID);
775   if (!LateCFGStructurize) {
776     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
777   }
778   addPass(createSinkingPass());
779   addPass(createAMDGPUAnnotateUniformValues());
780   if (!LateCFGStructurize) {
781     addPass(createSIAnnotateControlFlowPass());
782   }
783 
784   return false;
785 }
786 
787 void GCNPassConfig::addMachineSSAOptimization() {
788   TargetPassConfig::addMachineSSAOptimization();
789 
790   // We want to fold operands after PeepholeOptimizer has run (or as part of
791   // it), because it will eliminate extra copies making it easier to fold the
792   // real source operand. We want to eliminate dead instructions after, so that
793   // we see fewer uses of the copies. We then need to clean up the dead
794   // instructions leftover after the operands are folded as well.
795   //
796   // XXX - Can we get away without running DeadMachineInstructionElim again?
797   addPass(&SIFoldOperandsID);
798   addPass(&DeadMachineInstructionElimID);
799   addPass(&SILoadStoreOptimizerID);
800   if (EnableSDWAPeephole) {
801     addPass(&SIPeepholeSDWAID);
802     addPass(&EarlyMachineLICMID);
803     addPass(&MachineCSEID);
804     addPass(&SIFoldOperandsID);
805     addPass(&DeadMachineInstructionElimID);
806   }
807   addPass(createSIShrinkInstructionsPass());
808 }
809 
810 bool GCNPassConfig::addILPOpts() {
811   if (EnableEarlyIfConversion)
812     addPass(&EarlyIfConverterID);
813 
814   TargetPassConfig::addILPOpts();
815   return false;
816 }
817 
818 bool GCNPassConfig::addInstSelector() {
819   AMDGPUPassConfig::addInstSelector();
820   addPass(&SIFixSGPRCopiesID);
821   addPass(createSILowerI1CopiesPass());
822   return false;
823 }
824 
825 bool GCNPassConfig::addIRTranslator() {
826   addPass(new IRTranslator());
827   return false;
828 }
829 
830 bool GCNPassConfig::addLegalizeMachineIR() {
831   addPass(new Legalizer());
832   return false;
833 }
834 
835 bool GCNPassConfig::addRegBankSelect() {
836   addPass(new RegBankSelect());
837   return false;
838 }
839 
840 bool GCNPassConfig::addGlobalInstructionSelect() {
841   addPass(new InstructionSelect());
842   return false;
843 }
844 
845 void GCNPassConfig::addPreRegAlloc() {
846   if (LateCFGStructurize) {
847     addPass(createAMDGPUMachineCFGStructurizerPass());
848   }
849   addPass(createSIWholeQuadModePass());
850 }
851 
852 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
853   // FIXME: We have to disable the verifier here because of PHIElimination +
854   // TwoAddressInstructions disabling it.
855 
856   // This must be run immediately after phi elimination and before
857   // TwoAddressInstructions, otherwise the processing of the tied operand of
858   // SI_ELSE will introduce a copy of the tied operand source after the else.
859   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
860 
861   // This must be run after SILowerControlFlow, since it needs to use the
862   // machine-level CFG, but before register allocation.
863   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
864 
865   TargetPassConfig::addFastRegAlloc(RegAllocPass);
866 }
867 
868 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
869   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
870 
871   insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
872 
873   // This must be run immediately after phi elimination and before
874   // TwoAddressInstructions, otherwise the processing of the tied operand of
875   // SI_ELSE will introduce a copy of the tied operand source after the else.
876   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
877 
878   // This must be run after SILowerControlFlow, since it needs to use the
879   // machine-level CFG, but before register allocation.
880   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
881 
882   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
883 }
884 
885 void GCNPassConfig::addPostRegAlloc() {
886   addPass(&SIFixVGPRCopiesID);
887   addPass(&SIOptimizeExecMaskingID);
888   TargetPassConfig::addPostRegAlloc();
889 }
890 
891 void GCNPassConfig::addPreSched2() {
892 }
893 
894 void GCNPassConfig::addPreEmitPass() {
895   addPass(createSIMemoryLegalizerPass());
896   addPass(createSIInsertWaitcntsPass());
897   addPass(createSIShrinkInstructionsPass());
898 
899   // The hazard recognizer that runs as part of the post-ra scheduler does not
900   // guarantee to be able handle all hazards correctly. This is because if there
901   // are multiple scheduling regions in a basic block, the regions are scheduled
902   // bottom up, so when we begin to schedule a region we don't know what
903   // instructions were emitted directly before it.
904   //
905   // Here we add a stand-alone hazard recognizer pass which can handle all
906   // cases.
907   //
908   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
909   // be better for it to emit S_NOP <N> when possible.
910   addPass(&PostRAHazardRecognizerID);
911 
912   addPass(&SIInsertSkipsPassID);
913   addPass(createSIDebuggerInsertNopsPass());
914   addPass(&BranchRelaxationPassID);
915 }
916 
917 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
918   return new GCNPassConfig(*this, PM);
919 }
920