1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPUTargetObjectFile.h"
18 #include "AMDGPU.h"
19 #include "AMDGPUTargetTransformInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineScheduler.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "llvm/Analysis/Passes.h"
26 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Verifier.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/IR/LegacyPassManager.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_os_ostream.h"
35 #include "llvm/Transforms/IPO.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include <llvm/CodeGen/Passes.h>
38 
39 using namespace llvm;
40 
41 extern "C" void LLVMInitializeAMDGPUTarget() {
42   // Register the target
43   RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
44   RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
45 
46   PassRegistry *PR = PassRegistry::getPassRegistry();
47   initializeSILowerI1CopiesPass(*PR);
48   initializeSIFixSGPRCopiesPass(*PR);
49   initializeSIFoldOperandsPass(*PR);
50   initializeSIFixSGPRLiveRangesPass(*PR);
51   initializeSIFixControlFlowLiveIntervalsPass(*PR);
52   initializeSILoadStoreOptimizerPass(*PR);
53   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
54   initializeAMDGPUAnnotateUniformValuesPass(*PR);
55   initializeSIAnnotateControlFlowPass(*PR);
56 }
57 
58 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
59   if (TT.getOS() == Triple::AMDHSA)
60     return make_unique<AMDGPUHSATargetObjectFile>();
61 
62   return make_unique<AMDGPUTargetObjectFile>();
63 }
64 
65 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
66   return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
67 }
68 
69 static MachineSchedRegistry
70 R600SchedRegistry("r600", "Run R600's custom scheduler",
71                    createR600MachineScheduler);
72 
73 static MachineSchedRegistry
74 SISchedRegistry("si", "Run SI's custom scheduler",
75                 createSIMachineScheduler);
76 
77 static std::string computeDataLayout(const Triple &TT) {
78   std::string Ret = "e-p:32:32";
79 
80   if (TT.getArch() == Triple::amdgcn) {
81     // 32-bit private, local, and region pointers. 64-bit global and constant.
82     Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
83   }
84 
85   Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
86          "-v512:512-v1024:1024-v2048:2048-n32:64";
87 
88   return Ret;
89 }
90 
91 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
92                                          StringRef CPU, StringRef FS,
93                                          TargetOptions Options, Reloc::Model RM,
94                                          CodeModel::Model CM,
95                                          CodeGenOpt::Level OptLevel)
96     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
97                         OptLevel),
98       TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this),
99       IntrinsicInfo() {
100   setRequiresStructuredCFG(true);
101   initAsmInfo();
102 }
103 
104 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
105 
106 //===----------------------------------------------------------------------===//
107 // R600 Target Machine (R600 -> Cayman)
108 //===----------------------------------------------------------------------===//
109 
110 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
111                                      StringRef FS, StringRef CPU,
112                                      TargetOptions Options, Reloc::Model RM,
113                                      CodeModel::Model CM, CodeGenOpt::Level OL)
114     : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
115 
116 //===----------------------------------------------------------------------===//
117 // GCN Target Machine (SI+)
118 //===----------------------------------------------------------------------===//
119 
120 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
121                                    StringRef FS, StringRef CPU,
122                                    TargetOptions Options, Reloc::Model RM,
123                                    CodeModel::Model CM, CodeGenOpt::Level OL)
124     : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
125 
126 //===----------------------------------------------------------------------===//
127 // AMDGPU Pass Setup
128 //===----------------------------------------------------------------------===//
129 
130 namespace {
131 class AMDGPUPassConfig : public TargetPassConfig {
132 public:
133   AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
134     : TargetPassConfig(TM, PM) {
135 
136     // Exceptions and StackMaps are not supported, so these passes will never do
137     // anything.
138     disablePass(&StackMapLivenessID);
139     disablePass(&FuncletLayoutID);
140   }
141 
142   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
143     return getTM<AMDGPUTargetMachine>();
144   }
145 
146   ScheduleDAGInstrs *
147   createMachineScheduler(MachineSchedContext *C) const override {
148     const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
149     if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
150       return createR600MachineScheduler(C);
151     else if (ST.enableSIScheduler())
152       return createSIMachineScheduler(C);
153     return nullptr;
154   }
155 
156   void addIRPasses() override;
157   void addCodeGenPrepare() override;
158   bool addPreISel() override;
159   bool addInstSelector() override;
160   bool addGCPasses() override;
161 };
162 
163 class R600PassConfig : public AMDGPUPassConfig {
164 public:
165   R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
166     : AMDGPUPassConfig(TM, PM) { }
167 
168   bool addPreISel() override;
169   void addPreRegAlloc() override;
170   void addPreSched2() override;
171   void addPreEmitPass() override;
172 };
173 
174 class GCNPassConfig : public AMDGPUPassConfig {
175 public:
176   GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
177     : AMDGPUPassConfig(TM, PM) { }
178   bool addPreISel() override;
179   bool addInstSelector() override;
180   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
181   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
182   void addPreRegAlloc() override;
183   void addPostRegAlloc() override;
184   void addPreSched2() override;
185   void addPreEmitPass() override;
186 };
187 
188 } // End of anonymous namespace
189 
190 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
191   return TargetIRAnalysis([this](const Function &F) {
192     return TargetTransformInfo(
193         AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
194   });
195 }
196 
197 void AMDGPUPassConfig::addIRPasses() {
198   // Function calls are not supported, so make sure we inline everything.
199   addPass(createAMDGPUAlwaysInlinePass());
200   addPass(createAlwaysInlinerPass());
201   // We need to add the barrier noop pass, otherwise adding the function
202   // inlining pass will cause all of the PassConfigs passes to be run
203   // one function at a time, which means if we have a nodule with two
204   // functions, then we will generate code for the first function
205   // without ever running any passes on the second.
206   addPass(createBarrierNoopPass());
207 
208   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
209   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
210 
211   TargetPassConfig::addIRPasses();
212 }
213 
214 void AMDGPUPassConfig::addCodeGenPrepare() {
215   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
216   if (ST.isPromoteAllocaEnabled()) {
217     addPass(createAMDGPUPromoteAlloca(ST));
218     addPass(createSROAPass());
219   }
220   TargetPassConfig::addCodeGenPrepare();
221 }
222 
223 bool
224 AMDGPUPassConfig::addPreISel() {
225   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
226   addPass(createFlattenCFGPass());
227   if (ST.IsIRStructurizerEnabled())
228     addPass(createStructurizeCFGPass());
229   return false;
230 }
231 
232 bool AMDGPUPassConfig::addInstSelector() {
233   addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
234   return false;
235 }
236 
237 bool AMDGPUPassConfig::addGCPasses() {
238   // Do nothing. GC is not supported.
239   return false;
240 }
241 
242 //===----------------------------------------------------------------------===//
243 // R600 Pass Setup
244 //===----------------------------------------------------------------------===//
245 
246 bool R600PassConfig::addPreISel() {
247   AMDGPUPassConfig::addPreISel();
248   addPass(createR600TextureIntrinsicsReplacer());
249   return false;
250 }
251 
252 void R600PassConfig::addPreRegAlloc() {
253   addPass(createR600VectorRegMerger(*TM));
254 }
255 
256 void R600PassConfig::addPreSched2() {
257   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
258   addPass(createR600EmitClauseMarkers(), false);
259   if (ST.isIfCvtEnabled())
260     addPass(&IfConverterID, false);
261   addPass(createR600ClauseMergePass(*TM), false);
262 }
263 
264 void R600PassConfig::addPreEmitPass() {
265   addPass(createAMDGPUCFGStructurizerPass(), false);
266   addPass(createR600ExpandSpecialInstrsPass(*TM), false);
267   addPass(&FinalizeMachineBundlesID, false);
268   addPass(createR600Packetizer(*TM), false);
269   addPass(createR600ControlFlowFinalizer(*TM), false);
270 }
271 
272 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
273   return new R600PassConfig(this, PM);
274 }
275 
276 //===----------------------------------------------------------------------===//
277 // GCN Pass Setup
278 //===----------------------------------------------------------------------===//
279 
280 bool GCNPassConfig::addPreISel() {
281   AMDGPUPassConfig::addPreISel();
282 
283   // FIXME: We need to run a pass to propagate the attributes when calls are
284   // supported.
285   addPass(&AMDGPUAnnotateKernelFeaturesID);
286 
287   addPass(createSinkingPass());
288   addPass(createSITypeRewriter());
289   addPass(createSIAnnotateControlFlowPass());
290   addPass(createAMDGPUAnnotateUniformValues());
291 
292   return false;
293 }
294 
295 bool GCNPassConfig::addInstSelector() {
296   AMDGPUPassConfig::addInstSelector();
297   addPass(createSILowerI1CopiesPass());
298   addPass(&SIFixSGPRCopiesID);
299   addPass(createSIFoldOperandsPass());
300   return false;
301 }
302 
303 void GCNPassConfig::addPreRegAlloc() {
304   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
305 
306   // This needs to be run directly before register allocation because
307   // earlier passes might recompute live intervals.
308   // TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
309   if (getOptLevel() > CodeGenOpt::None) {
310     insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
311   }
312 
313   if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
314     // Don't do this with no optimizations since it throws away debug info by
315     // merging nonadjacent loads.
316 
317     // This should be run after scheduling, but before register allocation. It
318     // also need extra copies to the address operand to be eliminated.
319     insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
320     insertPass(&MachineSchedulerID, &RegisterCoalescerID);
321   }
322   addPass(createSIShrinkInstructionsPass(), false);
323 }
324 
325 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
326   addPass(&SIFixSGPRLiveRangesID);
327   TargetPassConfig::addFastRegAlloc(RegAllocPass);
328 }
329 
330 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
331   // We want to run this after LiveVariables is computed to avoid computing them
332   // twice.
333   // FIXME: We shouldn't disable the verifier here. r249087 introduced a failure
334   // that needs to be fixed.
335   insertPass(&LiveVariablesID, &SIFixSGPRLiveRangesID, /*VerifyAfter=*/false);
336   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
337 }
338 
339 void GCNPassConfig::addPostRegAlloc() {
340   addPass(createSIShrinkInstructionsPass(), false);
341 }
342 
343 void GCNPassConfig::addPreSched2() {
344 }
345 
346 void GCNPassConfig::addPreEmitPass() {
347   addPass(createSIInsertWaits(*TM), false);
348   addPass(createSILowerControlFlowPass(*TM), false);
349 }
350 
351 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
352   return new GCNPassConfig(this, PM);
353 }
354