1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information  needed to emit code for R600 and SI GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUAliasAnalysis.h"
19 #include "AMDGPUCallLowering.h"
20 #include "AMDGPUInstructionSelector.h"
21 #include "AMDGPULegalizerInfo.h"
22 #include "AMDGPUMacroFusion.h"
23 #include "AMDGPUTargetObjectFile.h"
24 #include "AMDGPUTargetTransformInfo.h"
25 #include "GCNIterativeScheduler.h"
26 #include "GCNSchedStrategy.h"
27 #include "R600MachineScheduler.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/LegacyPassManager.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Transforms/IPO.h"
44 #include "llvm/Transforms/IPO/AlwaysInliner.h"
45 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 #include "llvm/Transforms/Vectorize.h"
49 #include <memory>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableR600StructurizeCFG(
54   "r600-ir-structurize",
55   cl::desc("Use StructurizeCFG IR pass"),
56   cl::init(true));
57 
58 static cl::opt<bool> EnableSROA(
59   "amdgpu-sroa",
60   cl::desc("Run SROA after promote alloca pass"),
61   cl::ReallyHidden,
62   cl::init(true));
63 
64 static cl::opt<bool>
65 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
66                         cl::desc("Run early if-conversion"),
67                         cl::init(false));
68 
69 static cl::opt<bool> EnableR600IfConvert(
70   "r600-if-convert",
71   cl::desc("Use if conversion pass"),
72   cl::ReallyHidden,
73   cl::init(true));
74 
75 // Option to disable vectorizer for tests.
76 static cl::opt<bool> EnableLoadStoreVectorizer(
77   "amdgpu-load-store-vectorizer",
78   cl::desc("Enable load store vectorizer"),
79   cl::init(true),
80   cl::Hidden);
81 
82 // Option to to control global loads scalarization
83 static cl::opt<bool> ScalarizeGlobal(
84   "amdgpu-scalarize-global-loads",
85   cl::desc("Enable global load scalarization"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to run internalize pass.
90 static cl::opt<bool> InternalizeSymbols(
91   "amdgpu-internalize-symbols",
92   cl::desc("Enable elimination of non-kernel functions and unused globals"),
93   cl::init(false),
94   cl::Hidden);
95 
96 // Option to inline all early.
97 static cl::opt<bool> EarlyInlineAll(
98   "amdgpu-early-inline-all",
99   cl::desc("Inline all functions early"),
100   cl::init(false),
101   cl::Hidden);
102 
103 static cl::opt<bool> EnableSDWAPeephole(
104   "amdgpu-sdwa-peephole",
105   cl::desc("Enable SDWA peepholer"),
106   cl::init(true));
107 
108 // Enable address space based alias analysis
109 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
110   cl::desc("Enable AMDGPU Alias Analysis"),
111   cl::init(true));
112 
113 // Option to enable new waitcnt insertion pass.
114 static cl::opt<bool> EnableSIInsertWaitcntsPass(
115   "enable-si-insert-waitcnts",
116   cl::desc("Use new waitcnt insertion pass"),
117   cl::init(true));
118 
119 // Option to run late CFG structurizer
120 static cl::opt<bool> LateCFGStructurize(
121   "amdgpu-late-structurize",
122   cl::desc("Enable late CFG structurization"),
123   cl::init(false),
124   cl::Hidden);
125 
126 static cl::opt<bool> EnableAMDGPUFunctionCalls(
127   "amdgpu-function-calls",
128   cl::Hidden,
129   cl::desc("Enable AMDGPU function call support"),
130   cl::init(false));
131 
132 // Enable lib calls simplifications
133 static cl::opt<bool> EnableLibCallSimplify(
134   "amdgpu-simplify-libcall",
135   cl::desc("Enable mdgpu library simplifications"),
136   cl::init(true),
137   cl::Hidden);
138 
139 extern "C" void LLVMInitializeAMDGPUTarget() {
140   // Register the target
141   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
142   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
143 
144   PassRegistry *PR = PassRegistry::getPassRegistry();
145   initializeR600ClauseMergePassPass(*PR);
146   initializeR600ControlFlowFinalizerPass(*PR);
147   initializeR600PacketizerPass(*PR);
148   initializeR600ExpandSpecialInstrsPassPass(*PR);
149   initializeR600VectorRegMergerPass(*PR);
150   initializeAMDGPUDAGToDAGISelPass(*PR);
151   initializeSILowerI1CopiesPass(*PR);
152   initializeSIFixSGPRCopiesPass(*PR);
153   initializeSIFixVGPRCopiesPass(*PR);
154   initializeSIFoldOperandsPass(*PR);
155   initializeSIPeepholeSDWAPass(*PR);
156   initializeSIShrinkInstructionsPass(*PR);
157   initializeSIOptimizeExecMaskingPreRAPass(*PR);
158   initializeSILoadStoreOptimizerPass(*PR);
159   initializeAMDGPUAlwaysInlinePass(*PR);
160   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
161   initializeAMDGPUAnnotateUniformValuesPass(*PR);
162   initializeAMDGPUArgumentUsageInfoPass(*PR);
163   initializeAMDGPULowerIntrinsicsPass(*PR);
164   initializeAMDGPUPromoteAllocaPass(*PR);
165   initializeAMDGPUCodeGenPreparePass(*PR);
166   initializeAMDGPURewriteOutArgumentsPass(*PR);
167   initializeAMDGPUUnifyMetadataPass(*PR);
168   initializeSIAnnotateControlFlowPass(*PR);
169   initializeSIInsertWaitsPass(*PR);
170   initializeSIInsertWaitcntsPass(*PR);
171   initializeSIWholeQuadModePass(*PR);
172   initializeSILowerControlFlowPass(*PR);
173   initializeSIInsertSkipsPass(*PR);
174   initializeSIMemoryLegalizerPass(*PR);
175   initializeSIDebuggerInsertNopsPass(*PR);
176   initializeSIOptimizeExecMaskingPass(*PR);
177   initializeSIFixWWMLivenessPass(*PR);
178   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
179   initializeAMDGPUAAWrapperPassPass(*PR);
180   initializeAMDGPUUseNativeCallsPass(*PR);
181   initializeAMDGPUSimplifyLibCallsPass(*PR);
182 }
183 
184 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
185   return llvm::make_unique<AMDGPUTargetObjectFile>();
186 }
187 
188 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
189   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
190 }
191 
192 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
193   return new SIScheduleDAGMI(C);
194 }
195 
196 static ScheduleDAGInstrs *
197 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
198   ScheduleDAGMILive *DAG =
199     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
200   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
201   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
202   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
203   return DAG;
204 }
205 
206 static ScheduleDAGInstrs *
207 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
208   auto DAG = new GCNIterativeScheduler(C,
209     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
210   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
211   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
212   return DAG;
213 }
214 
215 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
216   return new GCNIterativeScheduler(C,
217     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
218 }
219 
220 static MachineSchedRegistry
221 R600SchedRegistry("r600", "Run R600's custom scheduler",
222                    createR600MachineScheduler);
223 
224 static MachineSchedRegistry
225 SISchedRegistry("si", "Run SI's custom scheduler",
226                 createSIMachineScheduler);
227 
228 static MachineSchedRegistry
229 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
230                              "Run GCN scheduler to maximize occupancy",
231                              createGCNMaxOccupancyMachineScheduler);
232 
233 static MachineSchedRegistry
234 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
235   "Run GCN scheduler to maximize occupancy (experimental)",
236   createIterativeGCNMaxOccupancyMachineScheduler);
237 
238 static MachineSchedRegistry
239 GCNMinRegSchedRegistry("gcn-minreg",
240   "Run GCN iterative scheduler for minimal register usage (experimental)",
241   createMinRegScheduler);
242 
243 static StringRef computeDataLayout(const Triple &TT) {
244   if (TT.getArch() == Triple::r600) {
245     // 32-bit pointers.
246     return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
247             "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
248   }
249 
250   // 32-bit private, local, and region pointers. 64-bit global, constant and
251   // flat.
252   if (TT.getEnvironmentName() == "amdgiz" ||
253       TT.getEnvironmentName() == "amdgizcl")
254     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
255          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
256          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
257   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
258       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
259       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
260 }
261 
262 LLVM_READNONE
263 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
264   if (!GPU.empty())
265     return GPU;
266 
267   if (TT.getArch() == Triple::amdgcn)
268     return "generic";
269 
270   return "r600";
271 }
272 
273 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
274   // The AMDGPU toolchain only supports generating shared objects, so we
275   // must always use PIC.
276   return Reloc::PIC_;
277 }
278 
279 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
280   if (CM)
281     return *CM;
282   return CodeModel::Small;
283 }
284 
285 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
286                                          StringRef CPU, StringRef FS,
287                                          TargetOptions Options,
288                                          Optional<Reloc::Model> RM,
289                                          Optional<CodeModel::Model> CM,
290                                          CodeGenOpt::Level OptLevel)
291     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
292                         FS, Options, getEffectiveRelocModel(RM),
293                         getEffectiveCodeModel(CM), OptLevel),
294       TLOF(createTLOF(getTargetTriple())) {
295   AS = AMDGPU::getAMDGPUAS(TT);
296   initAsmInfo();
297 }
298 
299 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
300 
301 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
302   Attribute GPUAttr = F.getFnAttribute("target-cpu");
303   return GPUAttr.hasAttribute(Attribute::None) ?
304     getTargetCPU() : GPUAttr.getValueAsString();
305 }
306 
307 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
308   Attribute FSAttr = F.getFnAttribute("target-features");
309 
310   return FSAttr.hasAttribute(Attribute::None) ?
311     getTargetFeatureString() :
312     FSAttr.getValueAsString();
313 }
314 
315 static ImmutablePass *createAMDGPUExternalAAWrapperPass() {
316   return createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
317       if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
318         AAR.addAAResult(WrapperPass->getResult());
319       });
320 }
321 
322 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
323   Builder.DivergentTarget = true;
324 
325   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
326   bool Internalize = InternalizeSymbols && EnableOpt &&
327                      (getTargetTriple().getArch() == Triple::amdgcn);
328   bool EarlyInline = EarlyInlineAll && EnableOpt;
329   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
330   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
331 
332   Builder.addExtension(
333     PassManagerBuilder::EP_ModuleOptimizerEarly,
334     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
335                                          legacy::PassManagerBase &PM) {
336       if (AMDGPUAA) {
337         PM.add(createAMDGPUAAWrapperPass());
338         PM.add(createAMDGPUExternalAAWrapperPass());
339       }
340       PM.add(createAMDGPUUnifyMetadataPass());
341       if (Internalize) {
342         PM.add(createInternalizePass([=](const GlobalValue &GV) -> bool {
343           if (const Function *F = dyn_cast<Function>(&GV)) {
344             if (F->isDeclaration())
345                 return true;
346             switch (F->getCallingConv()) {
347             default:
348               return false;
349             case CallingConv::AMDGPU_VS:
350             case CallingConv::AMDGPU_HS:
351             case CallingConv::AMDGPU_GS:
352             case CallingConv::AMDGPU_PS:
353             case CallingConv::AMDGPU_CS:
354             case CallingConv::AMDGPU_KERNEL:
355             case CallingConv::SPIR_KERNEL:
356               return true;
357             }
358           }
359           return !GV.use_empty();
360         }));
361         PM.add(createGlobalDCEPass());
362       }
363       if (EarlyInline)
364         PM.add(createAMDGPUAlwaysInlinePass(false));
365   });
366 
367   Builder.addExtension(
368     PassManagerBuilder::EP_EarlyAsPossible,
369     [AMDGPUAA, LibCallSimplify](const PassManagerBuilder &,
370                                 legacy::PassManagerBase &PM) {
371       if (AMDGPUAA) {
372         PM.add(createAMDGPUAAWrapperPass());
373         PM.add(createAMDGPUExternalAAWrapperPass());
374       }
375       PM.add(llvm::createAMDGPUUseNativeCallsPass());
376       if (LibCallSimplify)
377         PM.add(llvm::createAMDGPUSimplifyLibCallsPass());
378   });
379 
380   Builder.addExtension(
381     PassManagerBuilder::EP_CGSCCOptimizerLate,
382     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
383       // Add infer address spaces pass to the opt pipeline after inlining
384       // but before SROA to increase SROA opportunities.
385       PM.add(createInferAddressSpacesPass());
386   });
387 }
388 
389 //===----------------------------------------------------------------------===//
390 // R600 Target Machine (R600 -> Cayman)
391 //===----------------------------------------------------------------------===//
392 
393 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
394                                      StringRef CPU, StringRef FS,
395                                      TargetOptions Options,
396                                      Optional<Reloc::Model> RM,
397                                      Optional<CodeModel::Model> CM,
398                                      CodeGenOpt::Level OL, bool JIT)
399     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
400   setRequiresStructuredCFG(true);
401 }
402 
403 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
404   const Function &F) const {
405   StringRef GPU = getGPUName(F);
406   StringRef FS = getFeatureString(F);
407 
408   SmallString<128> SubtargetKey(GPU);
409   SubtargetKey.append(FS);
410 
411   auto &I = SubtargetMap[SubtargetKey];
412   if (!I) {
413     // This needs to be done before we create a new subtarget since any
414     // creation will depend on the TM and the code generation flags on the
415     // function that reside in TargetOptions.
416     resetTargetOptions(F);
417     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
418   }
419 
420   return I.get();
421 }
422 
423 //===----------------------------------------------------------------------===//
424 // GCN Target Machine (SI+)
425 //===----------------------------------------------------------------------===//
426 
427 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
428                                    StringRef CPU, StringRef FS,
429                                    TargetOptions Options,
430                                    Optional<Reloc::Model> RM,
431                                    Optional<CodeModel::Model> CM,
432                                    CodeGenOpt::Level OL, bool JIT)
433     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
434 
435 const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
436   StringRef GPU = getGPUName(F);
437   StringRef FS = getFeatureString(F);
438 
439   SmallString<128> SubtargetKey(GPU);
440   SubtargetKey.append(FS);
441 
442   auto &I = SubtargetMap[SubtargetKey];
443   if (!I) {
444     // This needs to be done before we create a new subtarget since any
445     // creation will depend on the TM and the code generation flags on the
446     // function that reside in TargetOptions.
447     resetTargetOptions(F);
448     I = llvm::make_unique<SISubtarget>(TargetTriple, GPU, FS, *this);
449   }
450 
451   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
452 
453   return I.get();
454 }
455 
456 //===----------------------------------------------------------------------===//
457 // AMDGPU Pass Setup
458 //===----------------------------------------------------------------------===//
459 
460 namespace {
461 
462 class AMDGPUPassConfig : public TargetPassConfig {
463 public:
464   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
465     : TargetPassConfig(TM, PM) {
466     // Exceptions and StackMaps are not supported, so these passes will never do
467     // anything.
468     disablePass(&StackMapLivenessID);
469     disablePass(&FuncletLayoutID);
470   }
471 
472   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
473     return getTM<AMDGPUTargetMachine>();
474   }
475 
476   ScheduleDAGInstrs *
477   createMachineScheduler(MachineSchedContext *C) const override {
478     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
479     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
480     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
481     return DAG;
482   }
483 
484   void addEarlyCSEOrGVNPass();
485   void addStraightLineScalarOptimizationPasses();
486   void addIRPasses() override;
487   void addCodeGenPrepare() override;
488   bool addPreISel() override;
489   bool addInstSelector() override;
490   bool addGCPasses() override;
491 };
492 
493 class R600PassConfig final : public AMDGPUPassConfig {
494 public:
495   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
496     : AMDGPUPassConfig(TM, PM) {}
497 
498   ScheduleDAGInstrs *createMachineScheduler(
499     MachineSchedContext *C) const override {
500     return createR600MachineScheduler(C);
501   }
502 
503   bool addPreISel() override;
504   bool addInstSelector() override;
505   void addPreRegAlloc() override;
506   void addPreSched2() override;
507   void addPreEmitPass() override;
508 };
509 
510 class GCNPassConfig final : public AMDGPUPassConfig {
511 public:
512   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
513     : AMDGPUPassConfig(TM, PM) {
514     // It is necessary to know the register usage of the entire call graph.  We
515     // allow calls without EnableAMDGPUFunctionCalls if they are marked
516     // noinline, so this is always required.
517     setRequiresCodeGenSCCOrder(true);
518   }
519 
520   GCNTargetMachine &getGCNTargetMachine() const {
521     return getTM<GCNTargetMachine>();
522   }
523 
524   ScheduleDAGInstrs *
525   createMachineScheduler(MachineSchedContext *C) const override;
526 
527   bool addPreISel() override;
528   void addMachineSSAOptimization() override;
529   bool addILPOpts() override;
530   bool addInstSelector() override;
531   bool addIRTranslator() override;
532   bool addLegalizeMachineIR() override;
533   bool addRegBankSelect() override;
534   bool addGlobalInstructionSelect() override;
535   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
536   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
537   void addPreRegAlloc() override;
538   void addPostRegAlloc() override;
539   void addPreSched2() override;
540   void addPreEmitPass() override;
541 };
542 
543 } // end anonymous namespace
544 
545 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
546   return TargetIRAnalysis([this](const Function &F) {
547     return TargetTransformInfo(AMDGPUTTIImpl(this, F));
548   });
549 }
550 
551 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
552   if (getOptLevel() == CodeGenOpt::Aggressive)
553     addPass(createGVNPass());
554   else
555     addPass(createEarlyCSEPass());
556 }
557 
558 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
559   addPass(createSeparateConstOffsetFromGEPPass());
560   addPass(createSpeculativeExecutionPass());
561   // ReassociateGEPs exposes more opportunites for SLSR. See
562   // the example in reassociate-geps-and-slsr.ll.
563   addPass(createStraightLineStrengthReducePass());
564   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
565   // EarlyCSE can reuse.
566   addEarlyCSEOrGVNPass();
567   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
568   addPass(createNaryReassociatePass());
569   // NaryReassociate on GEPs creates redundant common expressions, so run
570   // EarlyCSE after it.
571   addPass(createEarlyCSEPass());
572 }
573 
574 void AMDGPUPassConfig::addIRPasses() {
575   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
576 
577   // There is no reason to run these.
578   disablePass(&StackMapLivenessID);
579   disablePass(&FuncletLayoutID);
580   disablePass(&PatchableFunctionID);
581 
582   addPass(createAMDGPULowerIntrinsicsPass());
583 
584   if (TM.getTargetTriple().getArch() == Triple::r600 ||
585       !EnableAMDGPUFunctionCalls) {
586     // Function calls are not supported, so make sure we inline everything.
587     addPass(createAMDGPUAlwaysInlinePass());
588     addPass(createAlwaysInlinerLegacyPass());
589     // We need to add the barrier noop pass, otherwise adding the function
590     // inlining pass will cause all of the PassConfigs passes to be run
591     // one function at a time, which means if we have a nodule with two
592     // functions, then we will generate code for the first function
593     // without ever running any passes on the second.
594     addPass(createBarrierNoopPass());
595   }
596 
597   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
598     // TODO: May want to move later or split into an early and late one.
599 
600     addPass(createAMDGPUCodeGenPreparePass());
601   }
602 
603   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
604   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
605 
606   if (TM.getOptLevel() > CodeGenOpt::None) {
607     addPass(createInferAddressSpacesPass());
608     addPass(createAMDGPUPromoteAlloca());
609 
610     if (EnableSROA)
611       addPass(createSROAPass());
612 
613     addStraightLineScalarOptimizationPasses();
614 
615     if (EnableAMDGPUAliasAnalysis) {
616       addPass(createAMDGPUAAWrapperPass());
617       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
618                                              AAResults &AAR) {
619         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
620           AAR.addAAResult(WrapperPass->getResult());
621         }));
622     }
623   }
624 
625   TargetPassConfig::addIRPasses();
626 
627   // EarlyCSE is not always strong enough to clean up what LSR produces. For
628   // example, GVN can combine
629   //
630   //   %0 = add %a, %b
631   //   %1 = add %b, %a
632   //
633   // and
634   //
635   //   %0 = shl nsw %a, 2
636   //   %1 = shl %a, 2
637   //
638   // but EarlyCSE can do neither of them.
639   if (getOptLevel() != CodeGenOpt::None)
640     addEarlyCSEOrGVNPass();
641 }
642 
643 void AMDGPUPassConfig::addCodeGenPrepare() {
644   TargetPassConfig::addCodeGenPrepare();
645 
646   if (EnableLoadStoreVectorizer)
647     addPass(createLoadStoreVectorizerPass());
648 }
649 
650 bool AMDGPUPassConfig::addPreISel() {
651   addPass(createFlattenCFGPass());
652   return false;
653 }
654 
655 bool AMDGPUPassConfig::addInstSelector() {
656   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
657   return false;
658 }
659 
660 bool AMDGPUPassConfig::addGCPasses() {
661   // Do nothing. GC is not supported.
662   return false;
663 }
664 
665 //===----------------------------------------------------------------------===//
666 // R600 Pass Setup
667 //===----------------------------------------------------------------------===//
668 
669 bool R600PassConfig::addPreISel() {
670   AMDGPUPassConfig::addPreISel();
671 
672   if (EnableR600StructurizeCFG)
673     addPass(createStructurizeCFGPass());
674   return false;
675 }
676 
677 bool R600PassConfig::addInstSelector() {
678   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
679   return false;
680 }
681 
682 void R600PassConfig::addPreRegAlloc() {
683   addPass(createR600VectorRegMerger());
684 }
685 
686 void R600PassConfig::addPreSched2() {
687   addPass(createR600EmitClauseMarkers(), false);
688   if (EnableR600IfConvert)
689     addPass(&IfConverterID, false);
690   addPass(createR600ClauseMergePass(), false);
691 }
692 
693 void R600PassConfig::addPreEmitPass() {
694   addPass(createAMDGPUCFGStructurizerPass(), false);
695   addPass(createR600ExpandSpecialInstrsPass(), false);
696   addPass(&FinalizeMachineBundlesID, false);
697   addPass(createR600Packetizer(), false);
698   addPass(createR600ControlFlowFinalizer(), false);
699 }
700 
701 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
702   return new R600PassConfig(*this, PM);
703 }
704 
705 //===----------------------------------------------------------------------===//
706 // GCN Pass Setup
707 //===----------------------------------------------------------------------===//
708 
709 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
710   MachineSchedContext *C) const {
711   const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
712   if (ST.enableSIScheduler())
713     return createSIMachineScheduler(C);
714   return createGCNMaxOccupancyMachineScheduler(C);
715 }
716 
717 bool GCNPassConfig::addPreISel() {
718   AMDGPUPassConfig::addPreISel();
719 
720   // FIXME: We need to run a pass to propagate the attributes when calls are
721   // supported.
722   addPass(createAMDGPUAnnotateKernelFeaturesPass());
723 
724   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
725   // regions formed by them.
726   addPass(&AMDGPUUnifyDivergentExitNodesID);
727   if (!LateCFGStructurize) {
728     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
729   }
730   addPass(createSinkingPass());
731   addPass(createAMDGPUAnnotateUniformValues());
732   if (!LateCFGStructurize) {
733     addPass(createSIAnnotateControlFlowPass());
734   }
735 
736   return false;
737 }
738 
739 void GCNPassConfig::addMachineSSAOptimization() {
740   TargetPassConfig::addMachineSSAOptimization();
741 
742   // We want to fold operands after PeepholeOptimizer has run (or as part of
743   // it), because it will eliminate extra copies making it easier to fold the
744   // real source operand. We want to eliminate dead instructions after, so that
745   // we see fewer uses of the copies. We then need to clean up the dead
746   // instructions leftover after the operands are folded as well.
747   //
748   // XXX - Can we get away without running DeadMachineInstructionElim again?
749   addPass(&SIFoldOperandsID);
750   addPass(&DeadMachineInstructionElimID);
751   addPass(&SILoadStoreOptimizerID);
752   if (EnableSDWAPeephole) {
753     addPass(&SIPeepholeSDWAID);
754     addPass(&MachineLICMID);
755     addPass(&MachineCSEID);
756     addPass(&SIFoldOperandsID);
757     addPass(&DeadMachineInstructionElimID);
758   }
759   addPass(createSIShrinkInstructionsPass());
760 }
761 
762 bool GCNPassConfig::addILPOpts() {
763   if (EnableEarlyIfConversion)
764     addPass(&EarlyIfConverterID);
765 
766   TargetPassConfig::addILPOpts();
767   return false;
768 }
769 
770 bool GCNPassConfig::addInstSelector() {
771   AMDGPUPassConfig::addInstSelector();
772   addPass(createSILowerI1CopiesPass());
773   addPass(&SIFixSGPRCopiesID);
774   return false;
775 }
776 
777 bool GCNPassConfig::addIRTranslator() {
778   addPass(new IRTranslator());
779   return false;
780 }
781 
782 bool GCNPassConfig::addLegalizeMachineIR() {
783   addPass(new Legalizer());
784   return false;
785 }
786 
787 bool GCNPassConfig::addRegBankSelect() {
788   addPass(new RegBankSelect());
789   return false;
790 }
791 
792 bool GCNPassConfig::addGlobalInstructionSelect() {
793   addPass(new InstructionSelect());
794   return false;
795 }
796 
797 void GCNPassConfig::addPreRegAlloc() {
798   if (LateCFGStructurize) {
799     addPass(createAMDGPUMachineCFGStructurizerPass());
800   }
801   addPass(createSIWholeQuadModePass());
802 }
803 
804 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
805   // FIXME: We have to disable the verifier here because of PHIElimination +
806   // TwoAddressInstructions disabling it.
807 
808   // This must be run immediately after phi elimination and before
809   // TwoAddressInstructions, otherwise the processing of the tied operand of
810   // SI_ELSE will introduce a copy of the tied operand source after the else.
811   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
812 
813   // This must be run after SILowerControlFlow, since it needs to use the
814   // machine-level CFG, but before register allocation.
815   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
816 
817   TargetPassConfig::addFastRegAlloc(RegAllocPass);
818 }
819 
820 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
821   insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
822 
823   // This must be run immediately after phi elimination and before
824   // TwoAddressInstructions, otherwise the processing of the tied operand of
825   // SI_ELSE will introduce a copy of the tied operand source after the else.
826   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
827 
828   // This must be run after SILowerControlFlow, since it needs to use the
829   // machine-level CFG, but before register allocation.
830   insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
831 
832   TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
833 }
834 
835 void GCNPassConfig::addPostRegAlloc() {
836   addPass(&SIFixVGPRCopiesID);
837   addPass(&SIOptimizeExecMaskingID);
838   TargetPassConfig::addPostRegAlloc();
839 }
840 
841 void GCNPassConfig::addPreSched2() {
842 }
843 
844 void GCNPassConfig::addPreEmitPass() {
845   // The hazard recognizer that runs as part of the post-ra scheduler does not
846   // guarantee to be able handle all hazards correctly. This is because if there
847   // are multiple scheduling regions in a basic block, the regions are scheduled
848   // bottom up, so when we begin to schedule a region we don't know what
849   // instructions were emitted directly before it.
850   //
851   // Here we add a stand-alone hazard recognizer pass which can handle all
852   // cases.
853   addPass(&PostRAHazardRecognizerID);
854 
855   if (EnableSIInsertWaitcntsPass)
856     addPass(createSIInsertWaitcntsPass());
857   else
858     addPass(createSIInsertWaitsPass());
859   addPass(createSIShrinkInstructionsPass());
860   addPass(&SIInsertSkipsPassID);
861   addPass(createSIMemoryLegalizerPass());
862   addPass(createSIDebuggerInsertNopsPass());
863   addPass(&BranchRelaxationPassID);
864 }
865 
866 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
867   return new GCNPassConfig(*this, PM);
868 }
869 
870