1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information  needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUCallLowering.h"
19 #include "AMDGPUInstructionSelector.h"
20 #include "AMDGPULegalizerInfo.h"
21 #include "AMDGPUMacroFusion.h"
22 #include "AMDGPUTargetObjectFile.h"
23 #include "AMDGPUTargetTransformInfo.h"
24 #include "GCNIterativeScheduler.h"
25 #include "GCNSchedStrategy.h"
26 #include "R600MachineScheduler.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIMachineScheduler.h"
29 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/MIRParser/MIParser.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/TargetPassConfig.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/LegacyPassManager.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Transforms/IPO.h"
45 #include "llvm/Transforms/IPO/AlwaysInliner.h"
46 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
47 #include "llvm/Transforms/Scalar.h"
48 #include "llvm/Transforms/Scalar/GVN.h"
49 #include "llvm/Transforms/Utils.h"
50 #include "llvm/Transforms/Vectorize.h"
51 #include <memory>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableR600StructurizeCFG(
56   "r600-ir-structurize",
57   cl::desc("Use StructurizeCFG IR pass"),
58   cl::init(true));
59 
60 static cl::opt<bool> EnableSROA(
61   "amdgpu-sroa",
62   cl::desc("Run SROA after promote alloca pass"),
63   cl::ReallyHidden,
64   cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68                         cl::desc("Run early if-conversion"),
69                         cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73             cl::desc("Run pre-RA exec mask optimizations"),
74             cl::init(true));
75 
76 static cl::opt<bool> EnableR600IfConvert(
77   "r600-if-convert",
78   cl::desc("Use if conversion pass"),
79   cl::ReallyHidden,
80   cl::init(true));
81 
82 // Option to disable vectorizer for tests.
83 static cl::opt<bool> EnableLoadStoreVectorizer(
84   "amdgpu-load-store-vectorizer",
85   cl::desc("Enable load store vectorizer"),
86   cl::init(true),
87   cl::Hidden);
88 
89 // Option to control global loads scalarization
90 static cl::opt<bool> ScalarizeGlobal(
91   "amdgpu-scalarize-global-loads",
92   cl::desc("Enable global load scalarization"),
93   cl::init(true),
94   cl::Hidden);
95 
96 // Option to run internalize pass.
97 static cl::opt<bool> InternalizeSymbols(
98   "amdgpu-internalize-symbols",
99   cl::desc("Enable elimination of non-kernel functions and unused globals"),
100   cl::init(false),
101   cl::Hidden);
102 
103 // Option to inline all early.
104 static cl::opt<bool> EarlyInlineAll(
105   "amdgpu-early-inline-all",
106   cl::desc("Inline all functions early"),
107   cl::init(false),
108   cl::Hidden);
109 
110 static cl::opt<bool> EnableSDWAPeephole(
111   "amdgpu-sdwa-peephole",
112   cl::desc("Enable SDWA peepholer"),
113   cl::init(true));
114 
115 static cl::opt<bool> EnableDPPCombine(
116   "amdgpu-dpp-combine",
117   cl::desc("Enable DPP combiner"),
118   cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122   cl::desc("Enable AMDGPU Alias Analysis"),
123   cl::init(true));
124 
125 // Option to run late CFG structurizer
126 static cl::opt<bool, true> LateCFGStructurize(
127   "amdgpu-late-structurize",
128   cl::desc("Enable late CFG structurization"),
129   cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG),
130   cl::Hidden);
131 
132 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
133   "amdgpu-function-calls",
134   cl::desc("Enable AMDGPU function call support"),
135   cl::location(AMDGPUTargetMachine::EnableFunctionCalls),
136   cl::init(true),
137   cl::Hidden);
138 
139 // Enable lib calls simplifications
140 static cl::opt<bool> EnableLibCallSimplify(
141   "amdgpu-simplify-libcall",
142   cl::desc("Enable amdgpu library simplifications"),
143   cl::init(true),
144   cl::Hidden);
145 
146 static cl::opt<bool> EnableLowerKernelArguments(
147   "amdgpu-ir-lower-kernel-arguments",
148   cl::desc("Lower kernel argument loads in IR pass"),
149   cl::init(true),
150   cl::Hidden);
151 
152 static cl::opt<bool> EnableRegReassign(
153   "amdgpu-reassign-regs",
154   cl::desc("Enable register reassign optimizations on gfx10+"),
155   cl::init(true),
156   cl::Hidden);
157 
158 // Enable atomic optimization
159 static cl::opt<bool> EnableAtomicOptimizations(
160   "amdgpu-atomic-optimizations",
161   cl::desc("Enable atomic optimizations"),
162   cl::init(false),
163   cl::Hidden);
164 
165 // Enable Mode register optimization
166 static cl::opt<bool> EnableSIModeRegisterPass(
167   "amdgpu-mode-register",
168   cl::desc("Enable mode register pass"),
169   cl::init(true),
170   cl::Hidden);
171 
172 // Option is used in lit tests to prevent deadcoding of patterns inspected.
173 static cl::opt<bool>
174 EnableDCEInRA("amdgpu-dce-in-ra",
175     cl::init(true), cl::Hidden,
176     cl::desc("Enable machine DCE inside regalloc"));
177 
178 static cl::opt<bool> EnableScalarIRPasses(
179   "amdgpu-scalar-ir-passes",
180   cl::desc("Enable scalar IR passes"),
181   cl::init(true),
182   cl::Hidden);
183 
184 extern "C" void LLVMInitializeAMDGPUTarget() {
185   // Register the target
186   RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
187   RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
188 
189   PassRegistry *PR = PassRegistry::getPassRegistry();
190   initializeR600ClauseMergePassPass(*PR);
191   initializeR600ControlFlowFinalizerPass(*PR);
192   initializeR600PacketizerPass(*PR);
193   initializeR600ExpandSpecialInstrsPassPass(*PR);
194   initializeR600VectorRegMergerPass(*PR);
195   initializeGlobalISel(*PR);
196   initializeAMDGPUDAGToDAGISelPass(*PR);
197   initializeGCNDPPCombinePass(*PR);
198   initializeSILowerI1CopiesPass(*PR);
199   initializeSIFixSGPRCopiesPass(*PR);
200   initializeSIFixVGPRCopiesPass(*PR);
201   initializeSIFixupVectorISelPass(*PR);
202   initializeSIFoldOperandsPass(*PR);
203   initializeSIPeepholeSDWAPass(*PR);
204   initializeSIShrinkInstructionsPass(*PR);
205   initializeSIOptimizeExecMaskingPreRAPass(*PR);
206   initializeSILoadStoreOptimizerPass(*PR);
207   initializeAMDGPUFixFunctionBitcastsPass(*PR);
208   initializeAMDGPUAlwaysInlinePass(*PR);
209   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
210   initializeAMDGPUAnnotateUniformValuesPass(*PR);
211   initializeAMDGPUArgumentUsageInfoPass(*PR);
212   initializeAMDGPUAtomicOptimizerPass(*PR);
213   initializeAMDGPULowerKernelArgumentsPass(*PR);
214   initializeAMDGPULowerKernelAttributesPass(*PR);
215   initializeAMDGPULowerIntrinsicsPass(*PR);
216   initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(*PR);
217   initializeAMDGPUPromoteAllocaPass(*PR);
218   initializeAMDGPUCodeGenPreparePass(*PR);
219   initializeAMDGPURewriteOutArgumentsPass(*PR);
220   initializeAMDGPUUnifyMetadataPass(*PR);
221   initializeSIAnnotateControlFlowPass(*PR);
222   initializeSIInsertWaitcntsPass(*PR);
223   initializeSIModeRegisterPass(*PR);
224   initializeSIWholeQuadModePass(*PR);
225   initializeSILowerControlFlowPass(*PR);
226   initializeSIInsertSkipsPass(*PR);
227   initializeSIMemoryLegalizerPass(*PR);
228   initializeSIOptimizeExecMaskingPass(*PR);
229   initializeSIPreAllocateWWMRegsPass(*PR);
230   initializeSIFormMemoryClausesPass(*PR);
231   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
232   initializeAMDGPUAAWrapperPassPass(*PR);
233   initializeAMDGPUExternalAAWrapperPass(*PR);
234   initializeAMDGPUUseNativeCallsPass(*PR);
235   initializeAMDGPUSimplifyLibCallsPass(*PR);
236   initializeAMDGPUInlinerPass(*PR);
237   initializeGCNRegBankReassignPass(*PR);
238   initializeGCNNSAReassignPass(*PR);
239 }
240 
241 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
242   return llvm::make_unique<AMDGPUTargetObjectFile>();
243 }
244 
245 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
246   return new ScheduleDAGMILive(C, llvm::make_unique<R600SchedStrategy>());
247 }
248 
249 static ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C) {
250   return new SIScheduleDAGMI(C);
251 }
252 
253 static ScheduleDAGInstrs *
254 createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
255   ScheduleDAGMILive *DAG =
256     new GCNScheduleDAGMILive(C, make_unique<GCNMaxOccupancySchedStrategy>(C));
257   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
258   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
259   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
260   return DAG;
261 }
262 
263 static ScheduleDAGInstrs *
264 createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) {
265   auto DAG = new GCNIterativeScheduler(C,
266     GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY);
267   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
268   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
269   return DAG;
270 }
271 
272 static ScheduleDAGInstrs *createMinRegScheduler(MachineSchedContext *C) {
273   return new GCNIterativeScheduler(C,
274     GCNIterativeScheduler::SCHEDULE_MINREGFORCED);
275 }
276 
277 static ScheduleDAGInstrs *
278 createIterativeILPMachineScheduler(MachineSchedContext *C) {
279   auto DAG = new GCNIterativeScheduler(C,
280     GCNIterativeScheduler::SCHEDULE_ILP);
281   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
282   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
283   DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
284   return DAG;
285 }
286 
287 static MachineSchedRegistry
288 R600SchedRegistry("r600", "Run R600's custom scheduler",
289                    createR600MachineScheduler);
290 
291 static MachineSchedRegistry
292 SISchedRegistry("si", "Run SI's custom scheduler",
293                 createSIMachineScheduler);
294 
295 static MachineSchedRegistry
296 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
297                              "Run GCN scheduler to maximize occupancy",
298                              createGCNMaxOccupancyMachineScheduler);
299 
300 static MachineSchedRegistry
301 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
302   "Run GCN scheduler to maximize occupancy (experimental)",
303   createIterativeGCNMaxOccupancyMachineScheduler);
304 
305 static MachineSchedRegistry
306 GCNMinRegSchedRegistry("gcn-minreg",
307   "Run GCN iterative scheduler for minimal register usage (experimental)",
308   createMinRegScheduler);
309 
310 static MachineSchedRegistry
311 GCNILPSchedRegistry("gcn-ilp",
312   "Run GCN iterative scheduler for ILP scheduling (experimental)",
313   createIterativeILPMachineScheduler);
314 
315 static StringRef computeDataLayout(const Triple &TT) {
316   if (TT.getArch() == Triple::r600) {
317     // 32-bit pointers.
318       return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
319              "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
320   }
321 
322   // 32-bit private, local, and region pointers. 64-bit global, constant and
323   // flat, non-integral buffer fat pointers.
324     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
325          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
326          "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
327          "-ni:7";
328 }
329 
330 LLVM_READNONE
331 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
332   if (!GPU.empty())
333     return GPU;
334 
335   // Need to default to a target with flat support for HSA.
336   if (TT.getArch() == Triple::amdgcn)
337     return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
338 
339   return "r600";
340 }
341 
342 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
343   // The AMDGPU toolchain only supports generating shared objects, so we
344   // must always use PIC.
345   return Reloc::PIC_;
346 }
347 
348 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
349                                          StringRef CPU, StringRef FS,
350                                          TargetOptions Options,
351                                          Optional<Reloc::Model> RM,
352                                          Optional<CodeModel::Model> CM,
353                                          CodeGenOpt::Level OptLevel)
354     : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
355                         FS, Options, getEffectiveRelocModel(RM),
356                         getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
357       TLOF(createTLOF(getTargetTriple())) {
358   initAsmInfo();
359 }
360 
361 bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
362 bool AMDGPUTargetMachine::EnableFunctionCalls = false;
363 
364 AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
365 
366 StringRef AMDGPUTargetMachine::getGPUName(const Function &F) const {
367   Attribute GPUAttr = F.getFnAttribute("target-cpu");
368   return GPUAttr.hasAttribute(Attribute::None) ?
369     getTargetCPU() : GPUAttr.getValueAsString();
370 }
371 
372 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
373   Attribute FSAttr = F.getFnAttribute("target-features");
374 
375   return FSAttr.hasAttribute(Attribute::None) ?
376     getTargetFeatureString() :
377     FSAttr.getValueAsString();
378 }
379 
380 /// Predicate for Internalize pass.
381 static bool mustPreserveGV(const GlobalValue &GV) {
382   if (const Function *F = dyn_cast<Function>(&GV))
383     return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
384 
385   return !GV.use_empty();
386 }
387 
388 void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
389   Builder.DivergentTarget = true;
390 
391   bool EnableOpt = getOptLevel() > CodeGenOpt::None;
392   bool Internalize = InternalizeSymbols;
393   bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
394   bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
395   bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
396 
397   if (EnableFunctionCalls) {
398     delete Builder.Inliner;
399     Builder.Inliner = createAMDGPUFunctionInliningPass();
400   }
401 
402   Builder.addExtension(
403     PassManagerBuilder::EP_ModuleOptimizerEarly,
404     [Internalize, EarlyInline, AMDGPUAA](const PassManagerBuilder &,
405                                          legacy::PassManagerBase &PM) {
406       if (AMDGPUAA) {
407         PM.add(createAMDGPUAAWrapperPass());
408         PM.add(createAMDGPUExternalAAWrapperPass());
409       }
410       PM.add(createAMDGPUUnifyMetadataPass());
411       if (Internalize) {
412         PM.add(createInternalizePass(mustPreserveGV));
413         PM.add(createGlobalDCEPass());
414       }
415       if (EarlyInline)
416         PM.add(createAMDGPUAlwaysInlinePass(false));
417   });
418 
419   const auto &Opt = Options;
420   Builder.addExtension(
421     PassManagerBuilder::EP_EarlyAsPossible,
422     [AMDGPUAA, LibCallSimplify, &Opt](const PassManagerBuilder &,
423                                       legacy::PassManagerBase &PM) {
424       if (AMDGPUAA) {
425         PM.add(createAMDGPUAAWrapperPass());
426         PM.add(createAMDGPUExternalAAWrapperPass());
427       }
428       PM.add(llvm::createAMDGPUUseNativeCallsPass());
429       if (LibCallSimplify)
430         PM.add(llvm::createAMDGPUSimplifyLibCallsPass(Opt));
431   });
432 
433   Builder.addExtension(
434     PassManagerBuilder::EP_CGSCCOptimizerLate,
435     [](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
436       // Add infer address spaces pass to the opt pipeline after inlining
437       // but before SROA to increase SROA opportunities.
438       PM.add(createInferAddressSpacesPass());
439 
440       // This should run after inlining to have any chance of doing anything,
441       // and before other cleanup optimizations.
442       PM.add(createAMDGPULowerKernelAttributesPass());
443   });
444 }
445 
446 //===----------------------------------------------------------------------===//
447 // R600 Target Machine (R600 -> Cayman)
448 //===----------------------------------------------------------------------===//
449 
450 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
451                                      StringRef CPU, StringRef FS,
452                                      TargetOptions Options,
453                                      Optional<Reloc::Model> RM,
454                                      Optional<CodeModel::Model> CM,
455                                      CodeGenOpt::Level OL, bool JIT)
456     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
457   setRequiresStructuredCFG(true);
458 
459   // Override the default since calls aren't supported for r600.
460   if (EnableFunctionCalls &&
461       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
462     EnableFunctionCalls = false;
463 }
464 
465 const R600Subtarget *R600TargetMachine::getSubtargetImpl(
466   const Function &F) const {
467   StringRef GPU = getGPUName(F);
468   StringRef FS = getFeatureString(F);
469 
470   SmallString<128> SubtargetKey(GPU);
471   SubtargetKey.append(FS);
472 
473   auto &I = SubtargetMap[SubtargetKey];
474   if (!I) {
475     // This needs to be done before we create a new subtarget since any
476     // creation will depend on the TM and the code generation flags on the
477     // function that reside in TargetOptions.
478     resetTargetOptions(F);
479     I = llvm::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
480   }
481 
482   return I.get();
483 }
484 
485 TargetTransformInfo
486 R600TargetMachine::getTargetTransformInfo(const Function &F) {
487   return TargetTransformInfo(R600TTIImpl(this, F));
488 }
489 
490 //===----------------------------------------------------------------------===//
491 // GCN Target Machine (SI+)
492 //===----------------------------------------------------------------------===//
493 
494 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
495                                    StringRef CPU, StringRef FS,
496                                    TargetOptions Options,
497                                    Optional<Reloc::Model> RM,
498                                    Optional<CodeModel::Model> CM,
499                                    CodeGenOpt::Level OL, bool JIT)
500     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
501 
502 const GCNSubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const {
503   StringRef GPU = getGPUName(F);
504   StringRef FS = getFeatureString(F);
505 
506   SmallString<128> SubtargetKey(GPU);
507   SubtargetKey.append(FS);
508 
509   auto &I = SubtargetMap[SubtargetKey];
510   if (!I) {
511     // This needs to be done before we create a new subtarget since any
512     // creation will depend on the TM and the code generation flags on the
513     // function that reside in TargetOptions.
514     resetTargetOptions(F);
515     I = llvm::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
516   }
517 
518   I->setScalarizeGlobalBehavior(ScalarizeGlobal);
519 
520   return I.get();
521 }
522 
523 TargetTransformInfo
524 GCNTargetMachine::getTargetTransformInfo(const Function &F) {
525   return TargetTransformInfo(GCNTTIImpl(this, F));
526 }
527 
528 //===----------------------------------------------------------------------===//
529 // AMDGPU Pass Setup
530 //===----------------------------------------------------------------------===//
531 
532 namespace {
533 
534 class AMDGPUPassConfig : public TargetPassConfig {
535 public:
536   AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
537     : TargetPassConfig(TM, PM) {
538     // Exceptions and StackMaps are not supported, so these passes will never do
539     // anything.
540     disablePass(&StackMapLivenessID);
541     disablePass(&FuncletLayoutID);
542   }
543 
544   AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
545     return getTM<AMDGPUTargetMachine>();
546   }
547 
548   ScheduleDAGInstrs *
549   createMachineScheduler(MachineSchedContext *C) const override {
550     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
551     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
552     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
553     return DAG;
554   }
555 
556   void addEarlyCSEOrGVNPass();
557   void addStraightLineScalarOptimizationPasses();
558   void addIRPasses() override;
559   void addCodeGenPrepare() override;
560   bool addPreISel() override;
561   bool addInstSelector() override;
562   bool addGCPasses() override;
563 
564   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
565 };
566 
567 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
568   return getStandardCSEConfigForOpt(TM->getOptLevel());
569 }
570 
571 class R600PassConfig final : public AMDGPUPassConfig {
572 public:
573   R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
574     : AMDGPUPassConfig(TM, PM) {}
575 
576   ScheduleDAGInstrs *createMachineScheduler(
577     MachineSchedContext *C) const override {
578     return createR600MachineScheduler(C);
579   }
580 
581   bool addPreISel() override;
582   bool addInstSelector() override;
583   void addPreRegAlloc() override;
584   void addPreSched2() override;
585   void addPreEmitPass() override;
586 };
587 
588 class GCNPassConfig final : public AMDGPUPassConfig {
589 public:
590   GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
591     : AMDGPUPassConfig(TM, PM) {
592     // It is necessary to know the register usage of the entire call graph.  We
593     // allow calls without EnableAMDGPUFunctionCalls if they are marked
594     // noinline, so this is always required.
595     setRequiresCodeGenSCCOrder(true);
596   }
597 
598   GCNTargetMachine &getGCNTargetMachine() const {
599     return getTM<GCNTargetMachine>();
600   }
601 
602   ScheduleDAGInstrs *
603   createMachineScheduler(MachineSchedContext *C) const override;
604 
605   bool addPreISel() override;
606   void addMachineSSAOptimization() override;
607   bool addILPOpts() override;
608   bool addInstSelector() override;
609   bool addIRTranslator() override;
610   bool addLegalizeMachineIR() override;
611   bool addRegBankSelect() override;
612   bool addGlobalInstructionSelect() override;
613   void addFastRegAlloc() override;
614   void addOptimizedRegAlloc() override;
615   void addPreRegAlloc() override;
616   bool addPreRewrite() override;
617   void addPostRegAlloc() override;
618   void addPreSched2() override;
619   void addPreEmitPass() override;
620 };
621 
622 } // end anonymous namespace
623 
624 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
625   if (getOptLevel() == CodeGenOpt::Aggressive)
626     addPass(createGVNPass());
627   else
628     addPass(createEarlyCSEPass());
629 }
630 
631 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
632   addPass(createLICMPass());
633   addPass(createSeparateConstOffsetFromGEPPass());
634   addPass(createSpeculativeExecutionPass());
635   // ReassociateGEPs exposes more opportunites for SLSR. See
636   // the example in reassociate-geps-and-slsr.ll.
637   addPass(createStraightLineStrengthReducePass());
638   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
639   // EarlyCSE can reuse.
640   addEarlyCSEOrGVNPass();
641   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
642   addPass(createNaryReassociatePass());
643   // NaryReassociate on GEPs creates redundant common expressions, so run
644   // EarlyCSE after it.
645   addPass(createEarlyCSEPass());
646 }
647 
648 void AMDGPUPassConfig::addIRPasses() {
649   const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
650 
651   // There is no reason to run these.
652   disablePass(&StackMapLivenessID);
653   disablePass(&FuncletLayoutID);
654   disablePass(&PatchableFunctionID);
655 
656   addPass(createAtomicExpandPass());
657 
658   // This must occur before inlining, as the inliner will not look through
659   // bitcast calls.
660   addPass(createAMDGPUFixFunctionBitcastsPass());
661 
662   addPass(createAMDGPULowerIntrinsicsPass());
663 
664   // Function calls are not supported, so make sure we inline everything.
665   addPass(createAMDGPUAlwaysInlinePass());
666   addPass(createAlwaysInlinerLegacyPass());
667   // We need to add the barrier noop pass, otherwise adding the function
668   // inlining pass will cause all of the PassConfigs passes to be run
669   // one function at a time, which means if we have a nodule with two
670   // functions, then we will generate code for the first function
671   // without ever running any passes on the second.
672   addPass(createBarrierNoopPass());
673 
674   if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
675     // TODO: May want to move later or split into an early and late one.
676 
677     addPass(createAMDGPUCodeGenPreparePass());
678   }
679 
680   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
681   if (TM.getTargetTriple().getArch() == Triple::r600)
682     addPass(createR600OpenCLImageTypeLoweringPass());
683 
684   // Replace OpenCL enqueued block function pointers with global variables.
685   addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass());
686 
687   if (TM.getOptLevel() > CodeGenOpt::None) {
688     addPass(createInferAddressSpacesPass());
689     addPass(createAMDGPUPromoteAlloca());
690 
691     if (EnableSROA)
692       addPass(createSROAPass());
693 
694     if (EnableScalarIRPasses)
695       addStraightLineScalarOptimizationPasses();
696 
697     if (EnableAMDGPUAliasAnalysis) {
698       addPass(createAMDGPUAAWrapperPass());
699       addPass(createExternalAAWrapperPass([](Pass &P, Function &,
700                                              AAResults &AAR) {
701         if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
702           AAR.addAAResult(WrapperPass->getResult());
703         }));
704     }
705   }
706 
707   TargetPassConfig::addIRPasses();
708 
709   // EarlyCSE is not always strong enough to clean up what LSR produces. For
710   // example, GVN can combine
711   //
712   //   %0 = add %a, %b
713   //   %1 = add %b, %a
714   //
715   // and
716   //
717   //   %0 = shl nsw %a, 2
718   //   %1 = shl %a, 2
719   //
720   // but EarlyCSE can do neither of them.
721   if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
722     addEarlyCSEOrGVNPass();
723 }
724 
725 void AMDGPUPassConfig::addCodeGenPrepare() {
726   if (TM->getTargetTriple().getArch() == Triple::amdgcn)
727     addPass(createAMDGPUAnnotateKernelFeaturesPass());
728 
729   if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
730       EnableLowerKernelArguments)
731     addPass(createAMDGPULowerKernelArgumentsPass());
732 
733   TargetPassConfig::addCodeGenPrepare();
734 
735   if (EnableLoadStoreVectorizer)
736     addPass(createLoadStoreVectorizerPass());
737 }
738 
739 bool AMDGPUPassConfig::addPreISel() {
740   addPass(createLowerSwitchPass());
741   addPass(createFlattenCFGPass());
742   return false;
743 }
744 
745 bool AMDGPUPassConfig::addInstSelector() {
746   addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
747   return false;
748 }
749 
750 bool AMDGPUPassConfig::addGCPasses() {
751   // Do nothing. GC is not supported.
752   return false;
753 }
754 
755 //===----------------------------------------------------------------------===//
756 // R600 Pass Setup
757 //===----------------------------------------------------------------------===//
758 
759 bool R600PassConfig::addPreISel() {
760   AMDGPUPassConfig::addPreISel();
761 
762   if (EnableR600StructurizeCFG)
763     addPass(createStructurizeCFGPass());
764   return false;
765 }
766 
767 bool R600PassConfig::addInstSelector() {
768   addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
769   return false;
770 }
771 
772 void R600PassConfig::addPreRegAlloc() {
773   addPass(createR600VectorRegMerger());
774 }
775 
776 void R600PassConfig::addPreSched2() {
777   addPass(createR600EmitClauseMarkers(), false);
778   if (EnableR600IfConvert)
779     addPass(&IfConverterID, false);
780   addPass(createR600ClauseMergePass(), false);
781 }
782 
783 void R600PassConfig::addPreEmitPass() {
784   addPass(createAMDGPUCFGStructurizerPass(), false);
785   addPass(createR600ExpandSpecialInstrsPass(), false);
786   addPass(&FinalizeMachineBundlesID, false);
787   addPass(createR600Packetizer(), false);
788   addPass(createR600ControlFlowFinalizer(), false);
789 }
790 
791 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
792   return new R600PassConfig(*this, PM);
793 }
794 
795 //===----------------------------------------------------------------------===//
796 // GCN Pass Setup
797 //===----------------------------------------------------------------------===//
798 
799 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
800   MachineSchedContext *C) const {
801   const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
802   if (ST.enableSIScheduler())
803     return createSIMachineScheduler(C);
804   return createGCNMaxOccupancyMachineScheduler(C);
805 }
806 
807 bool GCNPassConfig::addPreISel() {
808   AMDGPUPassConfig::addPreISel();
809 
810   if (EnableAtomicOptimizations) {
811     addPass(createAMDGPUAtomicOptimizerPass());
812   }
813 
814   // FIXME: We need to run a pass to propagate the attributes when calls are
815   // supported.
816 
817   // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
818   // regions formed by them.
819   addPass(&AMDGPUUnifyDivergentExitNodesID);
820   if (!LateCFGStructurize) {
821     addPass(createStructurizeCFGPass(true)); // true -> SkipUniformRegions
822   }
823   addPass(createSinkingPass());
824   addPass(createAMDGPUAnnotateUniformValues());
825   if (!LateCFGStructurize) {
826     addPass(createSIAnnotateControlFlowPass());
827   }
828 
829   return false;
830 }
831 
832 void GCNPassConfig::addMachineSSAOptimization() {
833   TargetPassConfig::addMachineSSAOptimization();
834 
835   // We want to fold operands after PeepholeOptimizer has run (or as part of
836   // it), because it will eliminate extra copies making it easier to fold the
837   // real source operand. We want to eliminate dead instructions after, so that
838   // we see fewer uses of the copies. We then need to clean up the dead
839   // instructions leftover after the operands are folded as well.
840   //
841   // XXX - Can we get away without running DeadMachineInstructionElim again?
842   addPass(&SIFoldOperandsID);
843   if (EnableDPPCombine)
844     addPass(&GCNDPPCombineID);
845   addPass(&DeadMachineInstructionElimID);
846   addPass(&SILoadStoreOptimizerID);
847   if (EnableSDWAPeephole) {
848     addPass(&SIPeepholeSDWAID);
849     addPass(&EarlyMachineLICMID);
850     addPass(&MachineCSEID);
851     addPass(&SIFoldOperandsID);
852     addPass(&DeadMachineInstructionElimID);
853   }
854   addPass(createSIShrinkInstructionsPass());
855 }
856 
857 bool GCNPassConfig::addILPOpts() {
858   if (EnableEarlyIfConversion)
859     addPass(&EarlyIfConverterID);
860 
861   TargetPassConfig::addILPOpts();
862   return false;
863 }
864 
865 bool GCNPassConfig::addInstSelector() {
866   AMDGPUPassConfig::addInstSelector();
867   addPass(&SIFixSGPRCopiesID);
868   addPass(createSILowerI1CopiesPass());
869   addPass(createSIFixupVectorISelPass());
870   addPass(createSIAddIMGInitPass());
871   return false;
872 }
873 
874 bool GCNPassConfig::addIRTranslator() {
875   addPass(new IRTranslator());
876   return false;
877 }
878 
879 bool GCNPassConfig::addLegalizeMachineIR() {
880   addPass(new Legalizer());
881   return false;
882 }
883 
884 bool GCNPassConfig::addRegBankSelect() {
885   addPass(new RegBankSelect());
886   return false;
887 }
888 
889 bool GCNPassConfig::addGlobalInstructionSelect() {
890   addPass(new InstructionSelect());
891   return false;
892 }
893 
894 void GCNPassConfig::addPreRegAlloc() {
895   if (LateCFGStructurize) {
896     addPass(createAMDGPUMachineCFGStructurizerPass());
897   }
898   addPass(createSIWholeQuadModePass());
899 }
900 
901 void GCNPassConfig::addFastRegAlloc() {
902   // FIXME: We have to disable the verifier here because of PHIElimination +
903   // TwoAddressInstructions disabling it.
904 
905   // This must be run immediately after phi elimination and before
906   // TwoAddressInstructions, otherwise the processing of the tied operand of
907   // SI_ELSE will introduce a copy of the tied operand source after the else.
908   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
909 
910   // This must be run just after RegisterCoalescing.
911   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
912 
913   TargetPassConfig::addFastRegAlloc();
914 }
915 
916 void GCNPassConfig::addOptimizedRegAlloc() {
917   if (OptExecMaskPreRA) {
918     insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
919     insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
920   } else {
921     insertPass(&MachineSchedulerID, &SIFormMemoryClausesID);
922   }
923 
924   // This must be run immediately after phi elimination and before
925   // TwoAddressInstructions, otherwise the processing of the tied operand of
926   // SI_ELSE will introduce a copy of the tied operand source after the else.
927   insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
928 
929   // This must be run just after RegisterCoalescing.
930   insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
931 
932   if (EnableDCEInRA)
933     insertPass(&RenameIndependentSubregsID, &DeadMachineInstructionElimID);
934 
935   TargetPassConfig::addOptimizedRegAlloc();
936 }
937 
938 bool GCNPassConfig::addPreRewrite() {
939   if (EnableRegReassign) {
940     addPass(&GCNNSAReassignID);
941     addPass(&GCNRegBankReassignID);
942   }
943   return true;
944 }
945 
946 void GCNPassConfig::addPostRegAlloc() {
947   addPass(&SIFixVGPRCopiesID);
948   if (getOptLevel() > CodeGenOpt::None)
949     addPass(&SIOptimizeExecMaskingID);
950   TargetPassConfig::addPostRegAlloc();
951 }
952 
953 void GCNPassConfig::addPreSched2() {
954 }
955 
956 void GCNPassConfig::addPreEmitPass() {
957   addPass(createSIMemoryLegalizerPass());
958   addPass(createSIInsertWaitcntsPass());
959   addPass(createSIShrinkInstructionsPass());
960   addPass(createSIModeRegisterPass());
961 
962   // The hazard recognizer that runs as part of the post-ra scheduler does not
963   // guarantee to be able handle all hazards correctly. This is because if there
964   // are multiple scheduling regions in a basic block, the regions are scheduled
965   // bottom up, so when we begin to schedule a region we don't know what
966   // instructions were emitted directly before it.
967   //
968   // Here we add a stand-alone hazard recognizer pass which can handle all
969   // cases.
970   //
971   // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
972   // be better for it to emit S_NOP <N> when possible.
973   addPass(&PostRAHazardRecognizerID);
974 
975   addPass(&SIInsertSkipsPassID);
976   addPass(&BranchRelaxationPassID);
977 }
978 
979 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
980   return new GCNPassConfig(*this, PM);
981 }
982 
983 yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
984   return new yaml::SIMachineFunctionInfo();
985 }
986 
987 yaml::MachineFunctionInfo *
988 GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
989   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
990   return new yaml::SIMachineFunctionInfo(*MFI,
991                                          *MF.getSubtarget().getRegisterInfo());
992 }
993 
994 bool GCNTargetMachine::parseMachineFunctionInfo(
995     const yaml::MachineFunctionInfo &MFI_, PerFunctionMIParsingState &PFS,
996     SMDiagnostic &Error, SMRange &SourceRange) const {
997   const yaml::SIMachineFunctionInfo &YamlMFI =
998       reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
999   MachineFunction &MF = PFS.MF;
1000   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1001 
1002   MFI->initializeBaseYamlFields(YamlMFI);
1003 
1004   auto parseRegister = [&](const yaml::StringValue &RegName, unsigned &RegVal) {
1005     if (parseNamedRegisterReference(PFS, RegVal, RegName.Value, Error)) {
1006       SourceRange = RegName.SourceRange;
1007       return true;
1008     }
1009 
1010     return false;
1011   };
1012 
1013   auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1014     // Create a diagnostic for a the register string literal.
1015     const MemoryBuffer &Buffer =
1016         *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1017     Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1018                          RegName.Value.size(), SourceMgr::DK_Error,
1019                          "incorrect register class for field", RegName.Value,
1020                          None, None);
1021     SourceRange = RegName.SourceRange;
1022     return true;
1023   };
1024 
1025   if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1026       parseRegister(YamlMFI.ScratchWaveOffsetReg, MFI->ScratchWaveOffsetReg) ||
1027       parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1028       parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1029     return true;
1030 
1031   if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1032       !AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {
1033     return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1034   }
1035 
1036   if (MFI->ScratchWaveOffsetReg != AMDGPU::SCRATCH_WAVE_OFFSET_REG &&
1037       !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
1038     return diagnoseRegisterClass(YamlMFI.ScratchWaveOffsetReg);
1039   }
1040 
1041   if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1042       !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1043     return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1044   }
1045 
1046   if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1047       !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1048     return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1049   }
1050 
1051   return false;
1052 }
1053