1 //=== lib/CodeGen/GlobalISel/AMDGPURegBankCombiner.cpp ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // after register banks are known.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUTargetMachine.h"
15 #include "AMDGPULegalizerInfo.h"
16 #include "llvm/CodeGen/GlobalISel/Combiner.h"
17 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
18 #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
19 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/Support/Debug.h"
25 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
26 
27 #define DEBUG_TYPE "amdgpu-regbank-combiner"
28 
29 using namespace llvm;
30 using namespace MIPatternMatch;
31 
32 
33 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
34 #include "AMDGPUGenRegBankGICombiner.inc"
35 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
36 
37 namespace {
38 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
39 #include "AMDGPUGenRegBankGICombiner.inc"
40 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
41 
42 class AMDGPURegBankCombinerInfo : public CombinerInfo {
43   GISelKnownBits *KB;
44   MachineDominatorTree *MDT;
45 
46 public:
47   AMDGPUGenRegBankCombinerHelper Generated;
48 
49   AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
50                                   const AMDGPULegalizerInfo *LI,
51                                   GISelKnownBits *KB, MachineDominatorTree *MDT)
52       : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
53                      /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
54         KB(KB), MDT(MDT) {
55     if (!Generated.parseCommandLineOption())
56       report_fatal_error("Invalid rule identifier");
57   }
58 
59   bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
60                MachineIRBuilder &B) const override;
61 };
62 
63 bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer,
64                                               MachineInstr &MI,
65                                               MachineIRBuilder &B) const {
66   CombinerHelper Helper(Observer, B, KB, MDT);
67 
68   if (Generated.tryCombineAll(Observer, MI, B, Helper))
69     return true;
70 
71   return false;
72 }
73 
74 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
75 #include "AMDGPUGenRegBankGICombiner.inc"
76 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
77 
78 // Pass boilerplate
79 // ================
80 
81 class AMDGPURegBankCombiner : public MachineFunctionPass {
82 public:
83   static char ID;
84 
85   AMDGPURegBankCombiner(bool IsOptNone = false);
86 
87   StringRef getPassName() const override {
88     return "AMDGPURegBankCombiner";
89   }
90 
91   bool runOnMachineFunction(MachineFunction &MF) override;
92 
93   void getAnalysisUsage(AnalysisUsage &AU) const override;
94 private:
95   bool IsOptNone;
96 };
97 } // end anonymous namespace
98 
99 void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
100   AU.addRequired<TargetPassConfig>();
101   AU.setPreservesCFG();
102   getSelectionDAGFallbackAnalysisUsage(AU);
103   AU.addRequired<GISelKnownBitsAnalysis>();
104   AU.addPreserved<GISelKnownBitsAnalysis>();
105   if (!IsOptNone) {
106     AU.addRequired<MachineDominatorTree>();
107     AU.addPreserved<MachineDominatorTree>();
108   }
109   MachineFunctionPass::getAnalysisUsage(AU);
110 }
111 
112 AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
113   : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
114   initializeAMDGPURegBankCombinerPass(*PassRegistry::getPassRegistry());
115 }
116 
117 bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
118   if (MF.getProperties().hasProperty(
119           MachineFunctionProperties::Property::FailedISel))
120     return false;
121   auto *TPC = &getAnalysis<TargetPassConfig>();
122   const Function &F = MF.getFunction();
123   bool EnableOpt =
124       MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
125 
126   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
127   const AMDGPULegalizerInfo *LI
128     = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
129 
130   GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
131   MachineDominatorTree *MDT =
132       IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
133   AMDGPURegBankCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
134                                          F.hasMinSize(), LI, KB, MDT);
135   Combiner C(PCInfo, TPC);
136   return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
137 }
138 
139 char AMDGPURegBankCombiner::ID = 0;
140 INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE,
141                       "Combine AMDGPU machine instrs after regbankselect",
142                       false, false)
143 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
144 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
145 INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE,
146                     "Combine AMDGPU machine instrs after regbankselect", false,
147                     false)
148 
149 namespace llvm {
150 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone) {
151   return new AMDGPURegBankCombiner(IsOptNone);
152 }
153 } // end namespace llvm
154