1 //===- AMDGPUMachineCFGStructurizer.cpp - Machine code if conversion pass. ===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the machine instruction level CFG structurizer pass.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AMDGPU.h"
14 #include "GCNSubtarget.h"
15 #include "llvm/ADT/DenseSet.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegionInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/InitializePasses.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "amdgpucfgstructurizer"
29 
30 namespace {
31 
32 class PHILinearizeDestIterator;
33 
34 class PHILinearize {
35   friend class PHILinearizeDestIterator;
36 
37 public:
38   using PHISourceT = std::pair<unsigned, MachineBasicBlock *>;
39 
40 private:
41   using PHISourcesT = DenseSet<PHISourceT>;
42   using PHIInfoElementT = struct {
43     unsigned DestReg;
44     DebugLoc DL;
45     PHISourcesT Sources;
46   };
47   using PHIInfoT = SmallPtrSet<PHIInfoElementT *, 2>;
48   PHIInfoT PHIInfo;
49 
50   static unsigned phiInfoElementGetDest(PHIInfoElementT *Info);
51   static void phiInfoElementSetDef(PHIInfoElementT *Info, unsigned NewDef);
52   static PHISourcesT &phiInfoElementGetSources(PHIInfoElementT *Info);
53   static void phiInfoElementAddSource(PHIInfoElementT *Info, unsigned SourceReg,
54                                       MachineBasicBlock *SourceMBB);
55   static void phiInfoElementRemoveSource(PHIInfoElementT *Info,
56                                          unsigned SourceReg,
57                                          MachineBasicBlock *SourceMBB);
58   PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
59   PHIInfoElementT *findPHIInfoElementFromSource(unsigned SourceReg,
60                                                 MachineBasicBlock *SourceMBB);
61 
62 public:
63   bool findSourcesFromMBB(MachineBasicBlock *SourceMBB,
64                           SmallVector<unsigned, 4> &Sources);
65   void addDest(unsigned DestReg, const DebugLoc &DL);
66   void replaceDef(unsigned OldDestReg, unsigned NewDestReg);
67   void deleteDef(unsigned DestReg);
68   void addSource(unsigned DestReg, unsigned SourceReg,
69                  MachineBasicBlock *SourceMBB);
70   void removeSource(unsigned DestReg, unsigned SourceReg,
71                     MachineBasicBlock *SourceMBB = nullptr);
72   bool findDest(unsigned SourceReg, MachineBasicBlock *SourceMBB,
73                 unsigned &DestReg);
74   bool isSource(unsigned Reg, MachineBasicBlock *SourceMBB = nullptr);
75   unsigned getNumSources(unsigned DestReg);
76   void dump(MachineRegisterInfo *MRI);
77   void clear();
78 
79   using source_iterator = PHISourcesT::iterator;
80   using dest_iterator = PHILinearizeDestIterator;
81 
82   dest_iterator dests_begin();
83   dest_iterator dests_end();
84 
85   source_iterator sources_begin(unsigned Reg);
86   source_iterator sources_end(unsigned Reg);
87 };
88 
89 class PHILinearizeDestIterator {
90 private:
91   PHILinearize::PHIInfoT::iterator Iter;
92 
93 public:
94   PHILinearizeDestIterator(PHILinearize::PHIInfoT::iterator I) : Iter(I) {}
95 
96   unsigned operator*() { return PHILinearize::phiInfoElementGetDest(*Iter); }
97   PHILinearizeDestIterator &operator++() {
98     ++Iter;
99     return *this;
100   }
101   bool operator==(const PHILinearizeDestIterator &I) const {
102     return I.Iter == Iter;
103   }
104   bool operator!=(const PHILinearizeDestIterator &I) const {
105     return I.Iter != Iter;
106   }
107 };
108 
109 } // end anonymous namespace
110 
111 unsigned PHILinearize::phiInfoElementGetDest(PHIInfoElementT *Info) {
112   return Info->DestReg;
113 }
114 
115 void PHILinearize::phiInfoElementSetDef(PHIInfoElementT *Info,
116                                         unsigned NewDef) {
117   Info->DestReg = NewDef;
118 }
119 
120 PHILinearize::PHISourcesT &
121 PHILinearize::phiInfoElementGetSources(PHIInfoElementT *Info) {
122   return Info->Sources;
123 }
124 
125 void PHILinearize::phiInfoElementAddSource(PHIInfoElementT *Info,
126                                            unsigned SourceReg,
127                                            MachineBasicBlock *SourceMBB) {
128   // Assertion ensures we don't use the same SourceMBB for the
129   // sources, because we cannot have different registers with
130   // identical predecessors, but we can have the same register for
131   // multiple predecessors.
132 #if !defined(NDEBUG)
133   for (auto SI : phiInfoElementGetSources(Info)) {
134     assert((SI.second != SourceMBB || SourceReg == SI.first));
135   }
136 #endif
137 
138   phiInfoElementGetSources(Info).insert(PHISourceT(SourceReg, SourceMBB));
139 }
140 
141 void PHILinearize::phiInfoElementRemoveSource(PHIInfoElementT *Info,
142                                               unsigned SourceReg,
143                                               MachineBasicBlock *SourceMBB) {
144   auto &Sources = phiInfoElementGetSources(Info);
145   SmallVector<PHISourceT, 4> ElimiatedSources;
146   for (auto SI : Sources) {
147     if (SI.first == SourceReg &&
148         (SI.second == nullptr || SI.second == SourceMBB)) {
149       ElimiatedSources.push_back(PHISourceT(SI.first, SI.second));
150     }
151   }
152 
153   for (auto &Source : ElimiatedSources) {
154     Sources.erase(Source);
155   }
156 }
157 
158 PHILinearize::PHIInfoElementT *
159 PHILinearize::findPHIInfoElement(unsigned DestReg) {
160   for (auto I : PHIInfo) {
161     if (phiInfoElementGetDest(I) == DestReg) {
162       return I;
163     }
164   }
165   return nullptr;
166 }
167 
168 PHILinearize::PHIInfoElementT *
169 PHILinearize::findPHIInfoElementFromSource(unsigned SourceReg,
170                                            MachineBasicBlock *SourceMBB) {
171   for (auto I : PHIInfo) {
172     for (auto SI : phiInfoElementGetSources(I)) {
173       if (SI.first == SourceReg &&
174           (SI.second == nullptr || SI.second == SourceMBB)) {
175         return I;
176       }
177     }
178   }
179   return nullptr;
180 }
181 
182 bool PHILinearize::findSourcesFromMBB(MachineBasicBlock *SourceMBB,
183                                       SmallVector<unsigned, 4> &Sources) {
184   bool FoundSource = false;
185   for (auto I : PHIInfo) {
186     for (auto SI : phiInfoElementGetSources(I)) {
187       if (SI.second == SourceMBB) {
188         FoundSource = true;
189         Sources.push_back(SI.first);
190       }
191     }
192   }
193   return FoundSource;
194 }
195 
196 void PHILinearize::addDest(unsigned DestReg, const DebugLoc &DL) {
197   assert(findPHIInfoElement(DestReg) == nullptr && "Dest already exists");
198   PHISourcesT EmptySet;
199   PHIInfoElementT *NewElement = new PHIInfoElementT();
200   NewElement->DestReg = DestReg;
201   NewElement->DL = DL;
202   NewElement->Sources = EmptySet;
203   PHIInfo.insert(NewElement);
204 }
205 
206 void PHILinearize::replaceDef(unsigned OldDestReg, unsigned NewDestReg) {
207   phiInfoElementSetDef(findPHIInfoElement(OldDestReg), NewDestReg);
208 }
209 
210 void PHILinearize::deleteDef(unsigned DestReg) {
211   PHIInfoElementT *InfoElement = findPHIInfoElement(DestReg);
212   PHIInfo.erase(InfoElement);
213   delete InfoElement;
214 }
215 
216 void PHILinearize::addSource(unsigned DestReg, unsigned SourceReg,
217                              MachineBasicBlock *SourceMBB) {
218   phiInfoElementAddSource(findPHIInfoElement(DestReg), SourceReg, SourceMBB);
219 }
220 
221 void PHILinearize::removeSource(unsigned DestReg, unsigned SourceReg,
222                                 MachineBasicBlock *SourceMBB) {
223   phiInfoElementRemoveSource(findPHIInfoElement(DestReg), SourceReg, SourceMBB);
224 }
225 
226 bool PHILinearize::findDest(unsigned SourceReg, MachineBasicBlock *SourceMBB,
227                             unsigned &DestReg) {
228   PHIInfoElementT *InfoElement =
229       findPHIInfoElementFromSource(SourceReg, SourceMBB);
230   if (InfoElement != nullptr) {
231     DestReg = phiInfoElementGetDest(InfoElement);
232     return true;
233   }
234   return false;
235 }
236 
237 bool PHILinearize::isSource(unsigned Reg, MachineBasicBlock *SourceMBB) {
238   unsigned DestReg;
239   return findDest(Reg, SourceMBB, DestReg);
240 }
241 
242 unsigned PHILinearize::getNumSources(unsigned DestReg) {
243   return phiInfoElementGetSources(findPHIInfoElement(DestReg)).size();
244 }
245 
246 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
247 LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) {
248   const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
249   dbgs() << "=PHIInfo Start=\n";
250   for (auto PII : this->PHIInfo) {
251     PHIInfoElementT &Element = *PII;
252     dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
253            << " Sources: {";
254     for (auto &SI : Element.Sources) {
255       dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second)
256              << "),";
257     }
258     dbgs() << "}\n";
259   }
260   dbgs() << "=PHIInfo End=\n";
261 }
262 #endif
263 
264 void PHILinearize::clear() { PHIInfo = PHIInfoT(); }
265 
266 PHILinearize::dest_iterator PHILinearize::dests_begin() {
267   return PHILinearizeDestIterator(PHIInfo.begin());
268 }
269 
270 PHILinearize::dest_iterator PHILinearize::dests_end() {
271   return PHILinearizeDestIterator(PHIInfo.end());
272 }
273 
274 PHILinearize::source_iterator PHILinearize::sources_begin(unsigned Reg) {
275   auto InfoElement = findPHIInfoElement(Reg);
276   return phiInfoElementGetSources(InfoElement).begin();
277 }
278 
279 PHILinearize::source_iterator PHILinearize::sources_end(unsigned Reg) {
280   auto InfoElement = findPHIInfoElement(Reg);
281   return phiInfoElementGetSources(InfoElement).end();
282 }
283 
284 static unsigned getPHINumInputs(MachineInstr &PHI) {
285   assert(PHI.isPHI());
286   return (PHI.getNumOperands() - 1) / 2;
287 }
288 
289 static MachineBasicBlock *getPHIPred(MachineInstr &PHI, unsigned Index) {
290   assert(PHI.isPHI());
291   return PHI.getOperand(Index * 2 + 2).getMBB();
292 }
293 
294 static void setPhiPred(MachineInstr &PHI, unsigned Index,
295                        MachineBasicBlock *NewPred) {
296   PHI.getOperand(Index * 2 + 2).setMBB(NewPred);
297 }
298 
299 static unsigned getPHISourceReg(MachineInstr &PHI, unsigned Index) {
300   assert(PHI.isPHI());
301   return PHI.getOperand(Index * 2 + 1).getReg();
302 }
303 
304 static unsigned getPHIDestReg(MachineInstr &PHI) {
305   assert(PHI.isPHI());
306   return PHI.getOperand(0).getReg();
307 }
308 
309 namespace {
310 
311 class RegionMRT;
312 class MBBMRT;
313 
314 class LinearizedRegion {
315 protected:
316   MachineBasicBlock *Entry;
317   // The exit block is part of the region, and is the last
318   // merge block before exiting the region.
319   MachineBasicBlock *Exit;
320   DenseSet<unsigned> LiveOuts;
321   SmallPtrSet<MachineBasicBlock *, 1> MBBs;
322   bool HasLoop;
323   LinearizedRegion *Parent;
324   RegionMRT *RMRT;
325 
326   void storeLiveOutReg(MachineBasicBlock *MBB, Register Reg,
327                        MachineInstr *DefInstr, const MachineRegisterInfo *MRI,
328                        const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
329 
330   void storeLiveOutRegRegion(RegionMRT *Region, Register Reg,
331                              MachineInstr *DefInstr,
332                              const MachineRegisterInfo *MRI,
333                              const TargetRegisterInfo *TRI,
334                              PHILinearize &PHIInfo);
335 
336   void storeMBBLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
337                         const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
338                         RegionMRT *TopRegion);
339 
340   void storeLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
341                      const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
342 
343   void storeLiveOuts(RegionMRT *Region, const MachineRegisterInfo *MRI,
344                      const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
345                      RegionMRT *TopRegion = nullptr);
346 
347 public:
348   LinearizedRegion();
349   LinearizedRegion(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
350                    const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
351   ~LinearizedRegion() = default;
352 
353   void setRegionMRT(RegionMRT *Region) { RMRT = Region; }
354 
355   RegionMRT *getRegionMRT() { return RMRT; }
356 
357   void setParent(LinearizedRegion *P) { Parent = P; }
358 
359   LinearizedRegion *getParent() { return Parent; }
360 
361   void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr);
362 
363   void setBBSelectRegIn(unsigned Reg);
364 
365   unsigned getBBSelectRegIn();
366 
367   void setBBSelectRegOut(unsigned Reg, bool IsLiveOut);
368 
369   unsigned getBBSelectRegOut();
370 
371   void setHasLoop(bool Value);
372 
373   bool getHasLoop();
374 
375   void addLiveOut(unsigned VReg);
376 
377   void removeLiveOut(unsigned Reg);
378 
379   void replaceLiveOut(unsigned OldReg, unsigned NewReg);
380 
381   void replaceRegister(unsigned Register, class Register NewRegister,
382                        MachineRegisterInfo *MRI, bool ReplaceInside,
383                        bool ReplaceOutside, bool IncludeLoopPHIs);
384 
385   void replaceRegisterInsideRegion(unsigned Register, unsigned NewRegister,
386                                    bool IncludeLoopPHIs,
387                                    MachineRegisterInfo *MRI);
388 
389   void replaceRegisterOutsideRegion(unsigned Register, unsigned NewRegister,
390                                     bool IncludeLoopPHIs,
391                                     MachineRegisterInfo *MRI);
392 
393   DenseSet<unsigned> *getLiveOuts();
394 
395   void setEntry(MachineBasicBlock *NewEntry);
396 
397   MachineBasicBlock *getEntry();
398 
399   void setExit(MachineBasicBlock *NewExit);
400 
401   MachineBasicBlock *getExit();
402 
403   void addMBB(MachineBasicBlock *MBB);
404 
405   void addMBBs(LinearizedRegion *InnerRegion);
406 
407   bool contains(MachineBasicBlock *MBB);
408 
409   bool isLiveOut(unsigned Reg);
410 
411   bool hasNoDef(unsigned Reg, MachineRegisterInfo *MRI);
412 
413   void removeFalseRegisterKills(MachineRegisterInfo *MRI);
414 
415   void initLiveOut(RegionMRT *Region, const MachineRegisterInfo *MRI,
416                    const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
417 };
418 
419 class MRT {
420 protected:
421   RegionMRT *Parent;
422   unsigned BBSelectRegIn;
423   unsigned BBSelectRegOut;
424 
425 public:
426   virtual ~MRT() = default;
427 
428   unsigned getBBSelectRegIn() { return BBSelectRegIn; }
429 
430   unsigned getBBSelectRegOut() { return BBSelectRegOut; }
431 
432   void setBBSelectRegIn(unsigned Reg) { BBSelectRegIn = Reg; }
433 
434   void setBBSelectRegOut(unsigned Reg) { BBSelectRegOut = Reg; }
435 
436   virtual RegionMRT *getRegionMRT() { return nullptr; }
437 
438   virtual MBBMRT *getMBBMRT() { return nullptr; }
439 
440   bool isRegion() { return getRegionMRT() != nullptr; }
441 
442   bool isMBB() { return getMBBMRT() != nullptr; }
443 
444   bool isRoot() { return Parent == nullptr; }
445 
446   void setParent(RegionMRT *Region) { Parent = Region; }
447 
448   RegionMRT *getParent() { return Parent; }
449 
450   static MachineBasicBlock *
451   initializeMRT(MachineFunction &MF, const MachineRegionInfo *RegionInfo,
452                 DenseMap<MachineRegion *, RegionMRT *> &RegionMap);
453 
454   static RegionMRT *buildMRT(MachineFunction &MF,
455                              const MachineRegionInfo *RegionInfo,
456                              const SIInstrInfo *TII,
457                              MachineRegisterInfo *MRI);
458 
459   virtual void dump(const TargetRegisterInfo *TRI, int depth = 0) = 0;
460 
461   void dumpDepth(int depth) {
462     for (int i = depth; i > 0; --i) {
463       dbgs() << "  ";
464     }
465   }
466 };
467 
468 class MBBMRT : public MRT {
469   MachineBasicBlock *MBB;
470 
471 public:
472   MBBMRT(MachineBasicBlock *BB) : MBB(BB) {
473     setParent(nullptr);
474     setBBSelectRegOut(0);
475     setBBSelectRegIn(0);
476   }
477 
478   MBBMRT *getMBBMRT() override { return this; }
479 
480   MachineBasicBlock *getMBB() { return MBB; }
481 
482   void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
483     dumpDepth(depth);
484     dbgs() << "MBB: " << getMBB()->getNumber();
485     dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
486     dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
487   }
488 };
489 
490 class RegionMRT : public MRT {
491 protected:
492   MachineRegion *Region;
493   LinearizedRegion *LRegion = nullptr;
494   MachineBasicBlock *Succ = nullptr;
495   SetVector<MRT *> Children;
496 
497 public:
498   RegionMRT(MachineRegion *MachineRegion) : Region(MachineRegion) {
499     setParent(nullptr);
500     setBBSelectRegOut(0);
501     setBBSelectRegIn(0);
502   }
503 
504   ~RegionMRT() override {
505     if (LRegion) {
506       delete LRegion;
507     }
508 
509     for (auto CI : Children) {
510       delete &(*CI);
511     }
512   }
513 
514   RegionMRT *getRegionMRT() override { return this; }
515 
516   void setLinearizedRegion(LinearizedRegion *LinearizeRegion) {
517     LRegion = LinearizeRegion;
518   }
519 
520   LinearizedRegion *getLinearizedRegion() { return LRegion; }
521 
522   MachineRegion *getMachineRegion() { return Region; }
523 
524   unsigned getInnerOutputRegister() {
525     return (*(Children.begin()))->getBBSelectRegOut();
526   }
527 
528   void addChild(MRT *Tree) { Children.insert(Tree); }
529 
530   SetVector<MRT *> *getChildren() { return &Children; }
531 
532   void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
533     dumpDepth(depth);
534     dbgs() << "Region: " << (void *)Region;
535     dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
536     dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
537 
538     dumpDepth(depth);
539     if (getSucc())
540       dbgs() << "Succ: " << getSucc()->getNumber() << "\n";
541     else
542       dbgs() << "Succ: none \n";
543     for (auto MRTI : Children) {
544       MRTI->dump(TRI, depth + 1);
545     }
546   }
547 
548   MRT *getEntryTree() { return Children.back(); }
549 
550   MRT *getExitTree() { return Children.front(); }
551 
552   MachineBasicBlock *getEntry() {
553     MRT *Tree = Children.back();
554     return (Tree->isRegion()) ? Tree->getRegionMRT()->getEntry()
555                               : Tree->getMBBMRT()->getMBB();
556   }
557 
558   MachineBasicBlock *getExit() {
559     MRT *Tree = Children.front();
560     return (Tree->isRegion()) ? Tree->getRegionMRT()->getExit()
561                               : Tree->getMBBMRT()->getMBB();
562   }
563 
564   void setSucc(MachineBasicBlock *MBB) { Succ = MBB; }
565 
566   MachineBasicBlock *getSucc() { return Succ; }
567 
568   bool contains(MachineBasicBlock *MBB) {
569     for (auto CI : Children) {
570       if (CI->isMBB()) {
571         if (MBB == CI->getMBBMRT()->getMBB()) {
572           return true;
573         }
574       } else {
575         if (CI->getRegionMRT()->contains(MBB)) {
576           return true;
577         } else if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
578                    CI->getRegionMRT()->getLinearizedRegion()->contains(MBB)) {
579           return true;
580         }
581       }
582     }
583     return false;
584   }
585 
586   void replaceLiveOutReg(unsigned Register, unsigned NewRegister) {
587     LinearizedRegion *LRegion = getLinearizedRegion();
588     LRegion->replaceLiveOut(Register, NewRegister);
589     for (auto &CI : Children) {
590       if (CI->isRegion()) {
591         CI->getRegionMRT()->replaceLiveOutReg(Register, NewRegister);
592       }
593     }
594   }
595 };
596 
597 } // end anonymous namespace
598 
599 static unsigned createBBSelectReg(const SIInstrInfo *TII,
600                                   MachineRegisterInfo *MRI) {
601   return MRI->createVirtualRegister(TII->getPreferredSelectRegClass(32));
602 }
603 
604 MachineBasicBlock *
605 MRT::initializeMRT(MachineFunction &MF, const MachineRegionInfo *RegionInfo,
606                    DenseMap<MachineRegion *, RegionMRT *> &RegionMap) {
607   for (auto &MFI : MF) {
608     MachineBasicBlock *ExitMBB = &MFI;
609     if (ExitMBB->succ_empty()) {
610       return ExitMBB;
611     }
612   }
613   llvm_unreachable("CFG has no exit block");
614   return nullptr;
615 }
616 
617 RegionMRT *MRT::buildMRT(MachineFunction &MF,
618                          const MachineRegionInfo *RegionInfo,
619                          const SIInstrInfo *TII, MachineRegisterInfo *MRI) {
620   SmallPtrSet<MachineRegion *, 4> PlacedRegions;
621   DenseMap<MachineRegion *, RegionMRT *> RegionMap;
622   MachineRegion *TopLevelRegion = RegionInfo->getTopLevelRegion();
623   RegionMRT *Result = new RegionMRT(TopLevelRegion);
624   RegionMap[TopLevelRegion] = Result;
625 
626   // Insert the exit block first, we need it to be the merge node
627   // for the top level region.
628   MachineBasicBlock *Exit = initializeMRT(MF, RegionInfo, RegionMap);
629 
630   unsigned BBSelectRegIn = createBBSelectReg(TII, MRI);
631   MBBMRT *ExitMRT = new MBBMRT(Exit);
632   RegionMap[RegionInfo->getRegionFor(Exit)]->addChild(ExitMRT);
633   ExitMRT->setBBSelectRegIn(BBSelectRegIn);
634 
635   for (auto MBBI : post_order(&(MF.front()))) {
636     MachineBasicBlock *MBB = &(*MBBI);
637 
638     // Skip Exit since we already added it
639     if (MBB == Exit) {
640       continue;
641     }
642 
643     LLVM_DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n");
644     MBBMRT *NewMBB = new MBBMRT(MBB);
645     MachineRegion *Region = RegionInfo->getRegionFor(MBB);
646 
647     // Ensure we have the MRT region
648     if (RegionMap.count(Region) == 0) {
649       RegionMRT *NewMRTRegion = new RegionMRT(Region);
650       RegionMap[Region] = NewMRTRegion;
651 
652       // Ensure all parents are in the RegionMap
653       MachineRegion *Parent = Region->getParent();
654       while (RegionMap.count(Parent) == 0) {
655         RegionMRT *NewMRTParent = new RegionMRT(Parent);
656         NewMRTParent->addChild(NewMRTRegion);
657         NewMRTRegion->setParent(NewMRTParent);
658         RegionMap[Parent] = NewMRTParent;
659         NewMRTRegion = NewMRTParent;
660         Parent = Parent->getParent();
661       }
662       RegionMap[Parent]->addChild(NewMRTRegion);
663       NewMRTRegion->setParent(RegionMap[Parent]);
664     }
665 
666     // Add MBB to Region MRT
667     RegionMap[Region]->addChild(NewMBB);
668     NewMBB->setParent(RegionMap[Region]);
669     RegionMap[Region]->setSucc(Region->getExit());
670   }
671   return Result;
672 }
673 
674 void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, Register Reg,
675                                        MachineInstr *DefInstr,
676                                        const MachineRegisterInfo *MRI,
677                                        const TargetRegisterInfo *TRI,
678                                        PHILinearize &PHIInfo) {
679   if (Reg.isVirtual()) {
680     LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
681                       << "\n");
682     // If this is a source register to a PHI we are chaining, it
683     // must be live out.
684     if (PHIInfo.isSource(Reg)) {
685       LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n");
686       addLiveOut(Reg);
687     } else {
688       // If this is live out of the MBB
689       for (auto &UI : MRI->use_operands(Reg)) {
690         if (UI.getParent()->getParent() != MBB) {
691           LLVM_DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB)
692                             << "): " << printReg(Reg, TRI) << "\n");
693           addLiveOut(Reg);
694         } else {
695           // If the use is in the same MBB we have to make sure
696           // it is after the def, otherwise it is live out in a loop
697           MachineInstr *UseInstr = UI.getParent();
698           for (MachineBasicBlock::instr_iterator
699                    MII = UseInstr->getIterator(),
700                    MIE = UseInstr->getParent()->instr_end();
701                MII != MIE; ++MII) {
702             if ((&(*MII)) == DefInstr) {
703               LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI)
704                                 << "\n");
705               addLiveOut(Reg);
706             }
707           }
708         }
709       }
710     }
711   }
712 }
713 
714 void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, Register Reg,
715                                              MachineInstr *DefInstr,
716                                              const MachineRegisterInfo *MRI,
717                                              const TargetRegisterInfo *TRI,
718                                              PHILinearize &PHIInfo) {
719   if (Reg.isVirtual()) {
720     LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
721                       << "\n");
722     for (auto &UI : MRI->use_operands(Reg)) {
723       if (!Region->contains(UI.getParent()->getParent())) {
724         LLVM_DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region
725                           << "): " << printReg(Reg, TRI) << "\n");
726         addLiveOut(Reg);
727       }
728     }
729   }
730 }
731 
732 void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
733                                      const MachineRegisterInfo *MRI,
734                                      const TargetRegisterInfo *TRI,
735                                      PHILinearize &PHIInfo) {
736   LLVM_DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB)
737                     << ")-\n");
738   for (auto &II : *MBB) {
739     for (auto &RI : II.defs()) {
740       storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
741     }
742     for (auto &IRI : II.implicit_operands()) {
743       if (IRI.isDef()) {
744         storeLiveOutReg(MBB, IRI.getReg(), IRI.getParent(), MRI, TRI, PHIInfo);
745       }
746     }
747   }
748 
749   // If we have a successor with a PHI, source coming from this MBB we have to
750   // add the register as live out
751   for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
752                                         E = MBB->succ_end();
753        SI != E; ++SI) {
754     for (auto &II : *(*SI)) {
755       if (II.isPHI()) {
756         MachineInstr &PHI = II;
757         int numPreds = getPHINumInputs(PHI);
758         for (int i = 0; i < numPreds; ++i) {
759           if (getPHIPred(PHI, i) == MBB) {
760             unsigned PHIReg = getPHISourceReg(PHI, i);
761             LLVM_DEBUG(dbgs()
762                        << "Add LiveOut (PhiSource " << printMBBReference(*MBB)
763                        << " -> " << printMBBReference(*(*SI))
764                        << "): " << printReg(PHIReg, TRI) << "\n");
765             addLiveOut(PHIReg);
766           }
767         }
768       }
769     }
770   }
771 
772   LLVM_DEBUG(dbgs() << "-Store Live Outs Endn-\n");
773 }
774 
775 void LinearizedRegion::storeMBBLiveOuts(MachineBasicBlock *MBB,
776                                         const MachineRegisterInfo *MRI,
777                                         const TargetRegisterInfo *TRI,
778                                         PHILinearize &PHIInfo,
779                                         RegionMRT *TopRegion) {
780   for (auto &II : *MBB) {
781     for (auto &RI : II.defs()) {
782       storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI,
783                             PHIInfo);
784     }
785     for (auto &IRI : II.implicit_operands()) {
786       if (IRI.isDef()) {
787         storeLiveOutRegRegion(TopRegion, IRI.getReg(), IRI.getParent(), MRI,
788                               TRI, PHIInfo);
789       }
790     }
791   }
792 }
793 
794 void LinearizedRegion::storeLiveOuts(RegionMRT *Region,
795                                      const MachineRegisterInfo *MRI,
796                                      const TargetRegisterInfo *TRI,
797                                      PHILinearize &PHIInfo,
798                                      RegionMRT *CurrentTopRegion) {
799   MachineBasicBlock *Exit = Region->getSucc();
800 
801   RegionMRT *TopRegion =
802       CurrentTopRegion == nullptr ? Region : CurrentTopRegion;
803 
804   // Check if exit is end of function, if so, no live outs.
805   if (Exit == nullptr)
806     return;
807 
808   auto Children = Region->getChildren();
809   for (auto CI : *Children) {
810     if (CI->isMBB()) {
811       auto MBB = CI->getMBBMRT()->getMBB();
812       storeMBBLiveOuts(MBB, MRI, TRI, PHIInfo, TopRegion);
813     } else {
814       LinearizedRegion *SubRegion = CI->getRegionMRT()->getLinearizedRegion();
815       // We should be limited to only store registers that are live out from the
816       // linearized region
817       for (auto MBBI : SubRegion->MBBs) {
818         storeMBBLiveOuts(MBBI, MRI, TRI, PHIInfo, TopRegion);
819       }
820     }
821   }
822 
823   if (CurrentTopRegion == nullptr) {
824     auto Succ = Region->getSucc();
825     for (auto &II : *Succ) {
826       if (II.isPHI()) {
827         MachineInstr &PHI = II;
828         int numPreds = getPHINumInputs(PHI);
829         for (int i = 0; i < numPreds; ++i) {
830           if (Region->contains(getPHIPred(PHI, i))) {
831             unsigned PHIReg = getPHISourceReg(PHI, i);
832             LLVM_DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region
833                               << "): " << printReg(PHIReg, TRI) << "\n");
834             addLiveOut(PHIReg);
835           }
836         }
837       }
838     }
839   }
840 }
841 
842 #ifndef NDEBUG
843 void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
844   OS << "Linearized Region {";
845   bool IsFirst = true;
846   for (auto MBB : MBBs) {
847     if (IsFirst) {
848       IsFirst = false;
849     } else {
850       OS << " ,";
851     }
852     OS << MBB->getNumber();
853   }
854   OS << "} (" << Entry->getNumber() << ", "
855      << (Exit == nullptr ? -1 : Exit->getNumber())
856      << "): In:" << printReg(getBBSelectRegIn(), TRI)
857      << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {";
858   for (auto &LI : LiveOuts) {
859     OS << printReg(LI, TRI) << " ";
860   }
861   OS << "} \n";
862 }
863 #endif
864 
865 unsigned LinearizedRegion::getBBSelectRegIn() {
866   return getRegionMRT()->getBBSelectRegIn();
867 }
868 
869 unsigned LinearizedRegion::getBBSelectRegOut() {
870   return getRegionMRT()->getBBSelectRegOut();
871 }
872 
873 void LinearizedRegion::setHasLoop(bool Value) { HasLoop = Value; }
874 
875 bool LinearizedRegion::getHasLoop() { return HasLoop; }
876 
877 void LinearizedRegion::addLiveOut(unsigned VReg) { LiveOuts.insert(VReg); }
878 
879 void LinearizedRegion::removeLiveOut(unsigned Reg) {
880   if (isLiveOut(Reg))
881     LiveOuts.erase(Reg);
882 }
883 
884 void LinearizedRegion::replaceLiveOut(unsigned OldReg, unsigned NewReg) {
885   if (isLiveOut(OldReg)) {
886     removeLiveOut(OldReg);
887     addLiveOut(NewReg);
888   }
889 }
890 
891 void LinearizedRegion::replaceRegister(unsigned Register,
892                                        class Register NewRegister,
893                                        MachineRegisterInfo *MRI,
894                                        bool ReplaceInside, bool ReplaceOutside,
895                                        bool IncludeLoopPHI) {
896   assert(Register != NewRegister && "Cannot replace a reg with itself");
897 
898   LLVM_DEBUG(
899       dbgs() << "Preparing to replace register (region): "
900              << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
901              << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
902 
903   // If we are replacing outside, we also need to update the LiveOuts
904   if (ReplaceOutside &&
905       (isLiveOut(Register) || this->getParent()->isLiveOut(Register))) {
906     LinearizedRegion *Current = this;
907     while (Current != nullptr && Current->getEntry() != nullptr) {
908       LLVM_DEBUG(dbgs() << "Region before register replace\n");
909       LLVM_DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo()));
910       Current->replaceLiveOut(Register, NewRegister);
911       LLVM_DEBUG(dbgs() << "Region after register replace\n");
912       LLVM_DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo()));
913       Current = Current->getParent();
914     }
915   }
916 
917   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
918                                          E = MRI->reg_end();
919        I != E;) {
920     MachineOperand &O = *I;
921     ++I;
922 
923     // We don't rewrite defs.
924     if (O.isDef())
925       continue;
926 
927     bool IsInside = contains(O.getParent()->getParent());
928     bool IsLoopPHI = IsInside && (O.getParent()->isPHI() &&
929                                   O.getParent()->getParent() == getEntry());
930     bool ShouldReplace = (IsInside && ReplaceInside) ||
931                          (!IsInside && ReplaceOutside) ||
932                          (IncludeLoopPHI && IsLoopPHI);
933     if (ShouldReplace) {
934 
935       if (NewRegister.isPhysical()) {
936         LLVM_DEBUG(dbgs() << "Trying to substitute physical register: "
937                           << printReg(NewRegister, MRI->getTargetRegisterInfo())
938                           << "\n");
939         llvm_unreachable("Cannot substitute physical registers");
940       } else {
941         LLVM_DEBUG(dbgs() << "Replacing register (region): "
942                           << printReg(Register, MRI->getTargetRegisterInfo())
943                           << " with "
944                           << printReg(NewRegister, MRI->getTargetRegisterInfo())
945                           << "\n");
946         O.setReg(NewRegister);
947       }
948     }
949   }
950 }
951 
952 void LinearizedRegion::replaceRegisterInsideRegion(unsigned Register,
953                                                    unsigned NewRegister,
954                                                    bool IncludeLoopPHIs,
955                                                    MachineRegisterInfo *MRI) {
956   replaceRegister(Register, NewRegister, MRI, true, false, IncludeLoopPHIs);
957 }
958 
959 void LinearizedRegion::replaceRegisterOutsideRegion(unsigned Register,
960                                                     unsigned NewRegister,
961                                                     bool IncludeLoopPHIs,
962                                                     MachineRegisterInfo *MRI) {
963   replaceRegister(Register, NewRegister, MRI, false, true, IncludeLoopPHIs);
964 }
965 
966 DenseSet<unsigned> *LinearizedRegion::getLiveOuts() { return &LiveOuts; }
967 
968 void LinearizedRegion::setEntry(MachineBasicBlock *NewEntry) {
969   Entry = NewEntry;
970 }
971 
972 MachineBasicBlock *LinearizedRegion::getEntry() { return Entry; }
973 
974 void LinearizedRegion::setExit(MachineBasicBlock *NewExit) { Exit = NewExit; }
975 
976 MachineBasicBlock *LinearizedRegion::getExit() { return Exit; }
977 
978 void LinearizedRegion::addMBB(MachineBasicBlock *MBB) { MBBs.insert(MBB); }
979 
980 void LinearizedRegion::addMBBs(LinearizedRegion *InnerRegion) {
981   for (auto MBB : InnerRegion->MBBs) {
982     addMBB(MBB);
983   }
984 }
985 
986 bool LinearizedRegion::contains(MachineBasicBlock *MBB) {
987   return MBBs.contains(MBB);
988 }
989 
990 bool LinearizedRegion::isLiveOut(unsigned Reg) {
991   return LiveOuts.contains(Reg);
992 }
993 
994 bool LinearizedRegion::hasNoDef(unsigned Reg, MachineRegisterInfo *MRI) {
995   return MRI->def_begin(Reg) == MRI->def_end();
996 }
997 
998 // After the code has been structurized, what was flagged as kills
999 // before are no longer register kills.
1000 void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) {
1001   const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1002   (void)TRI; // It's used by LLVM_DEBUG.
1003 
1004   for (auto MBBI : MBBs) {
1005     MachineBasicBlock *MBB = MBBI;
1006     for (auto &II : *MBB) {
1007       for (auto &RI : II.uses()) {
1008         if (RI.isReg()) {
1009           Register Reg = RI.getReg();
1010           if (Reg.isVirtual()) {
1011             if (hasNoDef(Reg, MRI))
1012               continue;
1013             if (!MRI->hasOneDef(Reg)) {
1014               LLVM_DEBUG(this->getEntry()->getParent()->dump());
1015               LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << "\n");
1016             }
1017 
1018             if (MRI->def_begin(Reg) == MRI->def_end()) {
1019               LLVM_DEBUG(dbgs() << "Register "
1020                                 << printReg(Reg, MRI->getTargetRegisterInfo())
1021                                 << " has NO defs\n");
1022             } else if (!MRI->hasOneDef(Reg)) {
1023               LLVM_DEBUG(dbgs() << "Register "
1024                                 << printReg(Reg, MRI->getTargetRegisterInfo())
1025                                 << " has multiple defs\n");
1026             }
1027 
1028             assert(MRI->hasOneDef(Reg) && "Register has multiple definitions");
1029             MachineOperand *Def = &(*(MRI->def_begin(Reg)));
1030             MachineOperand *UseOperand = &(RI);
1031             bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
1032             if (UseIsOutsideDefMBB && UseOperand->isKill()) {
1033               LLVM_DEBUG(dbgs() << "Removing kill flag on register: "
1034                                 << printReg(Reg, TRI) << "\n");
1035               UseOperand->setIsKill(false);
1036             }
1037           }
1038         }
1039       }
1040     }
1041   }
1042 }
1043 
1044 void LinearizedRegion::initLiveOut(RegionMRT *Region,
1045                                    const MachineRegisterInfo *MRI,
1046                                    const TargetRegisterInfo *TRI,
1047                                    PHILinearize &PHIInfo) {
1048   storeLiveOuts(Region, MRI, TRI, PHIInfo);
1049 }
1050 
1051 LinearizedRegion::LinearizedRegion(MachineBasicBlock *MBB,
1052                                    const MachineRegisterInfo *MRI,
1053                                    const TargetRegisterInfo *TRI,
1054                                    PHILinearize &PHIInfo) {
1055   setEntry(MBB);
1056   setExit(MBB);
1057   storeLiveOuts(MBB, MRI, TRI, PHIInfo);
1058   MBBs.insert(MBB);
1059   Parent = nullptr;
1060 }
1061 
1062 LinearizedRegion::LinearizedRegion() {
1063   setEntry(nullptr);
1064   setExit(nullptr);
1065   Parent = nullptr;
1066 }
1067 
1068 namespace {
1069 
1070 class AMDGPUMachineCFGStructurizer : public MachineFunctionPass {
1071 private:
1072   const MachineRegionInfo *Regions;
1073   const SIInstrInfo *TII;
1074   const TargetRegisterInfo *TRI;
1075   MachineRegisterInfo *MRI;
1076   PHILinearize PHIInfo;
1077   DenseMap<MachineBasicBlock *, MachineBasicBlock *> FallthroughMap;
1078   RegionMRT *RMRT;
1079 
1080   void getPHIRegionIndices(RegionMRT *Region, MachineInstr &PHI,
1081                            SmallVector<unsigned, 2> &RegionIndices);
1082   void getPHIRegionIndices(LinearizedRegion *Region, MachineInstr &PHI,
1083                            SmallVector<unsigned, 2> &RegionIndices);
1084   void getPHINonRegionIndices(LinearizedRegion *Region, MachineInstr &PHI,
1085                               SmallVector<unsigned, 2> &PHINonRegionIndices);
1086 
1087   void storePHILinearizationInfoDest(
1088       unsigned LDestReg, MachineInstr &PHI,
1089       SmallVector<unsigned, 2> *RegionIndices = nullptr);
1090 
1091   unsigned storePHILinearizationInfo(MachineInstr &PHI,
1092                                      SmallVector<unsigned, 2> *RegionIndices);
1093 
1094   void extractKilledPHIs(MachineBasicBlock *MBB);
1095 
1096   bool shrinkPHI(MachineInstr &PHI, SmallVector<unsigned, 2> &PHIIndices,
1097                  unsigned *ReplaceReg);
1098 
1099   bool shrinkPHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1100                  MachineBasicBlock *SourceMBB,
1101                  SmallVector<unsigned, 2> &PHIIndices, unsigned *ReplaceReg);
1102 
1103   void replacePHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1104                   MachineBasicBlock *LastMerge,
1105                   SmallVector<unsigned, 2> &PHIRegionIndices);
1106   void replaceEntryPHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1107                        MachineBasicBlock *IfMBB,
1108                        SmallVector<unsigned, 2> &PHIRegionIndices);
1109   void replaceLiveOutRegs(MachineInstr &PHI,
1110                           SmallVector<unsigned, 2> &PHIRegionIndices,
1111                           unsigned CombinedSourceReg,
1112                           LinearizedRegion *LRegion);
1113   void rewriteRegionExitPHI(RegionMRT *Region, MachineBasicBlock *LastMerge,
1114                             MachineInstr &PHI, LinearizedRegion *LRegion);
1115 
1116   void rewriteRegionExitPHIs(RegionMRT *Region, MachineBasicBlock *LastMerge,
1117                              LinearizedRegion *LRegion);
1118   void rewriteRegionEntryPHI(LinearizedRegion *Region, MachineBasicBlock *IfMBB,
1119                              MachineInstr &PHI);
1120   void rewriteRegionEntryPHIs(LinearizedRegion *Region,
1121                               MachineBasicBlock *IfMBB);
1122 
1123   bool regionIsSimpleIf(RegionMRT *Region);
1124 
1125   void transformSimpleIfRegion(RegionMRT *Region);
1126 
1127   void insertUnconditionalBranch(MachineBasicBlock *MBB,
1128                                  MachineBasicBlock *Dest,
1129                                  const DebugLoc &DL = DebugLoc());
1130 
1131   MachineBasicBlock *createLinearizedExitBlock(RegionMRT *Region);
1132 
1133   void insertMergePHI(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1134                       MachineBasicBlock *MergeBB, unsigned DestRegister,
1135                       unsigned IfSourceRegister, unsigned CodeSourceRegister,
1136                       bool IsUndefIfSource = false);
1137 
1138   MachineBasicBlock *createIfBlock(MachineBasicBlock *MergeBB,
1139                                    MachineBasicBlock *CodeBBStart,
1140                                    MachineBasicBlock *CodeBBEnd,
1141                                    MachineBasicBlock *SelectBB, unsigned IfReg,
1142                                    bool InheritPreds);
1143 
1144   void prunePHIInfo(MachineBasicBlock *MBB);
1145   void createEntryPHI(LinearizedRegion *CurrentRegion, unsigned DestReg);
1146 
1147   void createEntryPHIs(LinearizedRegion *CurrentRegion);
1148   void resolvePHIInfos(MachineBasicBlock *FunctionEntry);
1149 
1150   void replaceRegisterWith(unsigned Register, class Register NewRegister);
1151 
1152   MachineBasicBlock *createIfRegion(MachineBasicBlock *MergeBB,
1153                                     MachineBasicBlock *CodeBB,
1154                                     LinearizedRegion *LRegion,
1155                                     unsigned BBSelectRegIn,
1156                                     unsigned BBSelectRegOut);
1157 
1158   MachineBasicBlock *
1159   createIfRegion(MachineBasicBlock *MergeMBB, LinearizedRegion *InnerRegion,
1160                  LinearizedRegion *CurrentRegion, MachineBasicBlock *SelectBB,
1161                  unsigned BBSelectRegIn, unsigned BBSelectRegOut);
1162   void ensureCondIsNotKilled(SmallVector<MachineOperand, 1> Cond);
1163 
1164   void rewriteCodeBBTerminator(MachineBasicBlock *CodeBB,
1165                                MachineBasicBlock *MergeBB,
1166                                unsigned BBSelectReg);
1167 
1168   MachineInstr *getDefInstr(unsigned Reg);
1169   void insertChainedPHI(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1170                         MachineBasicBlock *MergeBB,
1171                         LinearizedRegion *InnerRegion, unsigned DestReg,
1172                         unsigned SourceReg);
1173   bool containsDef(MachineBasicBlock *MBB, LinearizedRegion *InnerRegion,
1174                    unsigned Register);
1175   void rewriteLiveOutRegs(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1176                           MachineBasicBlock *MergeBB,
1177                           LinearizedRegion *InnerRegion,
1178                           LinearizedRegion *LRegion);
1179 
1180   void splitLoopPHI(MachineInstr &PHI, MachineBasicBlock *Entry,
1181                     MachineBasicBlock *EntrySucc, LinearizedRegion *LRegion);
1182   void splitLoopPHIs(MachineBasicBlock *Entry, MachineBasicBlock *EntrySucc,
1183                      LinearizedRegion *LRegion);
1184 
1185   MachineBasicBlock *splitExit(LinearizedRegion *LRegion);
1186 
1187   MachineBasicBlock *splitEntry(LinearizedRegion *LRegion);
1188 
1189   LinearizedRegion *initLinearizedRegion(RegionMRT *Region);
1190 
1191   bool structurizeComplexRegion(RegionMRT *Region);
1192 
1193   bool structurizeRegion(RegionMRT *Region);
1194 
1195   bool structurizeRegions(RegionMRT *Region, bool isTopRegion);
1196 
1197 public:
1198   static char ID;
1199 
1200   AMDGPUMachineCFGStructurizer() : MachineFunctionPass(ID) {
1201     initializeAMDGPUMachineCFGStructurizerPass(*PassRegistry::getPassRegistry());
1202   }
1203 
1204   void getAnalysisUsage(AnalysisUsage &AU) const override {
1205     AU.addRequired<MachineRegionInfoPass>();
1206     MachineFunctionPass::getAnalysisUsage(AU);
1207   }
1208 
1209   void initFallthroughMap(MachineFunction &MF);
1210 
1211   void createLinearizedRegion(RegionMRT *Region, unsigned SelectOut);
1212 
1213   unsigned initializeSelectRegisters(MRT *MRT, unsigned ExistingExitReg,
1214                                      MachineRegisterInfo *MRI,
1215                                      const SIInstrInfo *TII);
1216 
1217   void setRegionMRT(RegionMRT *RegionTree) { RMRT = RegionTree; }
1218 
1219   RegionMRT *getRegionMRT() { return RMRT; }
1220 
1221   bool runOnMachineFunction(MachineFunction &MF) override;
1222 };
1223 
1224 } // end anonymous namespace
1225 
1226 char AMDGPUMachineCFGStructurizer::ID = 0;
1227 
1228 bool AMDGPUMachineCFGStructurizer::regionIsSimpleIf(RegionMRT *Region) {
1229   MachineBasicBlock *Entry = Region->getEntry();
1230   MachineBasicBlock *Succ = Region->getSucc();
1231   bool FoundBypass = false;
1232   bool FoundIf = false;
1233 
1234   if (Entry->succ_size() != 2) {
1235     return false;
1236   }
1237 
1238   for (MachineBasicBlock::const_succ_iterator SI = Entry->succ_begin(),
1239                                               E = Entry->succ_end();
1240        SI != E; ++SI) {
1241     MachineBasicBlock *Current = *SI;
1242 
1243     if (Current == Succ) {
1244       FoundBypass = true;
1245     } else if ((Current->succ_size() == 1) &&
1246                *(Current->succ_begin()) == Succ) {
1247       FoundIf = true;
1248     }
1249   }
1250 
1251   return FoundIf && FoundBypass;
1252 }
1253 
1254 void AMDGPUMachineCFGStructurizer::transformSimpleIfRegion(RegionMRT *Region) {
1255   MachineBasicBlock *Entry = Region->getEntry();
1256   MachineBasicBlock *Exit = Region->getExit();
1257   TII->convertNonUniformIfRegion(Entry, Exit);
1258 }
1259 
1260 static void fixMBBTerminator(MachineBasicBlock *MBB) {
1261   if (MBB->succ_size() == 1) {
1262     auto *Succ = *(MBB->succ_begin());
1263     for (auto &TI : MBB->terminators()) {
1264       for (auto &UI : TI.uses()) {
1265         if (UI.isMBB() && UI.getMBB() != Succ) {
1266           UI.setMBB(Succ);
1267         }
1268       }
1269     }
1270   }
1271 }
1272 
1273 static void fixRegionTerminator(RegionMRT *Region) {
1274   MachineBasicBlock *InternalSucc = nullptr;
1275   MachineBasicBlock *ExternalSucc = nullptr;
1276   LinearizedRegion *LRegion = Region->getLinearizedRegion();
1277   auto Exit = LRegion->getExit();
1278 
1279   SmallPtrSet<MachineBasicBlock *, 2> Successors;
1280   for (MachineBasicBlock::const_succ_iterator SI = Exit->succ_begin(),
1281                                               SE = Exit->succ_end();
1282        SI != SE; ++SI) {
1283     MachineBasicBlock *Succ = *SI;
1284     if (LRegion->contains(Succ)) {
1285       // Do not allow re-assign
1286       assert(InternalSucc == nullptr);
1287       InternalSucc = Succ;
1288     } else {
1289       // Do not allow re-assign
1290       assert(ExternalSucc == nullptr);
1291       ExternalSucc = Succ;
1292     }
1293   }
1294 
1295   for (auto &TI : Exit->terminators()) {
1296     for (auto &UI : TI.uses()) {
1297       if (UI.isMBB()) {
1298         auto Target = UI.getMBB();
1299         if (Target != InternalSucc && Target != ExternalSucc) {
1300           UI.setMBB(ExternalSucc);
1301         }
1302       }
1303     }
1304   }
1305 }
1306 
1307 // If a region region is just a sequence of regions (and the exit
1308 // block in the case of the top level region), we can simply skip
1309 // linearizing it, because it is already linear
1310 bool regionIsSequence(RegionMRT *Region) {
1311   auto Children = Region->getChildren();
1312   for (auto CI : *Children) {
1313     if (!CI->isRegion()) {
1314       if (CI->getMBBMRT()->getMBB()->succ_size() > 1) {
1315         return false;
1316       }
1317     }
1318   }
1319   return true;
1320 }
1321 
1322 void fixupRegionExits(RegionMRT *Region) {
1323   auto Children = Region->getChildren();
1324   for (auto CI : *Children) {
1325     if (!CI->isRegion()) {
1326       fixMBBTerminator(CI->getMBBMRT()->getMBB());
1327     } else {
1328       fixRegionTerminator(CI->getRegionMRT());
1329     }
1330   }
1331 }
1332 
1333 void AMDGPUMachineCFGStructurizer::getPHIRegionIndices(
1334     RegionMRT *Region, MachineInstr &PHI,
1335     SmallVector<unsigned, 2> &PHIRegionIndices) {
1336   unsigned NumInputs = getPHINumInputs(PHI);
1337   for (unsigned i = 0; i < NumInputs; ++i) {
1338     MachineBasicBlock *Pred = getPHIPred(PHI, i);
1339     if (Region->contains(Pred)) {
1340       PHIRegionIndices.push_back(i);
1341     }
1342   }
1343 }
1344 
1345 void AMDGPUMachineCFGStructurizer::getPHIRegionIndices(
1346     LinearizedRegion *Region, MachineInstr &PHI,
1347     SmallVector<unsigned, 2> &PHIRegionIndices) {
1348   unsigned NumInputs = getPHINumInputs(PHI);
1349   for (unsigned i = 0; i < NumInputs; ++i) {
1350     MachineBasicBlock *Pred = getPHIPred(PHI, i);
1351     if (Region->contains(Pred)) {
1352       PHIRegionIndices.push_back(i);
1353     }
1354   }
1355 }
1356 
1357 void AMDGPUMachineCFGStructurizer::getPHINonRegionIndices(
1358     LinearizedRegion *Region, MachineInstr &PHI,
1359     SmallVector<unsigned, 2> &PHINonRegionIndices) {
1360   unsigned NumInputs = getPHINumInputs(PHI);
1361   for (unsigned i = 0; i < NumInputs; ++i) {
1362     MachineBasicBlock *Pred = getPHIPred(PHI, i);
1363     if (!Region->contains(Pred)) {
1364       PHINonRegionIndices.push_back(i);
1365     }
1366   }
1367 }
1368 
1369 void AMDGPUMachineCFGStructurizer::storePHILinearizationInfoDest(
1370     unsigned LDestReg, MachineInstr &PHI,
1371     SmallVector<unsigned, 2> *RegionIndices) {
1372   if (RegionIndices) {
1373     for (auto i : *RegionIndices) {
1374       PHIInfo.addSource(LDestReg, getPHISourceReg(PHI, i), getPHIPred(PHI, i));
1375     }
1376   } else {
1377     unsigned NumInputs = getPHINumInputs(PHI);
1378     for (unsigned i = 0; i < NumInputs; ++i) {
1379       PHIInfo.addSource(LDestReg, getPHISourceReg(PHI, i), getPHIPred(PHI, i));
1380     }
1381   }
1382 }
1383 
1384 unsigned AMDGPUMachineCFGStructurizer::storePHILinearizationInfo(
1385     MachineInstr &PHI, SmallVector<unsigned, 2> *RegionIndices) {
1386   unsigned DestReg = getPHIDestReg(PHI);
1387   Register LinearizeDestReg =
1388       MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1389   PHIInfo.addDest(LinearizeDestReg, PHI.getDebugLoc());
1390   storePHILinearizationInfoDest(LinearizeDestReg, PHI, RegionIndices);
1391   return LinearizeDestReg;
1392 }
1393 
1394 void AMDGPUMachineCFGStructurizer::extractKilledPHIs(MachineBasicBlock *MBB) {
1395   // We need to create a new chain for the killed phi, but there is no
1396   // need to do the renaming outside or inside the block.
1397   SmallPtrSet<MachineInstr *, 2> PHIs;
1398   for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
1399                                          E = MBB->instr_end();
1400        I != E; ++I) {
1401     MachineInstr &Instr = *I;
1402     if (Instr.isPHI()) {
1403       unsigned PHIDestReg = getPHIDestReg(Instr);
1404       LLVM_DEBUG(dbgs() << "Extracting killed phi:\n");
1405       LLVM_DEBUG(Instr.dump());
1406       PHIs.insert(&Instr);
1407       PHIInfo.addDest(PHIDestReg, Instr.getDebugLoc());
1408       storePHILinearizationInfoDest(PHIDestReg, Instr);
1409     }
1410   }
1411 
1412   for (auto PI : PHIs) {
1413     PI->eraseFromParent();
1414   }
1415 }
1416 
1417 static bool isPHIRegionIndex(SmallVector<unsigned, 2> PHIRegionIndices,
1418                              unsigned Index) {
1419   return llvm::is_contained(PHIRegionIndices, Index);
1420 }
1421 
1422 bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
1423                                        SmallVector<unsigned, 2> &PHIIndices,
1424                                        unsigned *ReplaceReg) {
1425   return shrinkPHI(PHI, 0, nullptr, PHIIndices, ReplaceReg);
1426 }
1427 
1428 bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
1429                                        unsigned CombinedSourceReg,
1430                                        MachineBasicBlock *SourceMBB,
1431                                        SmallVector<unsigned, 2> &PHIIndices,
1432                                        unsigned *ReplaceReg) {
1433   LLVM_DEBUG(dbgs() << "Shrink PHI: ");
1434   LLVM_DEBUG(PHI.dump());
1435   LLVM_DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI)
1436                     << " = PHI(");
1437 
1438   bool Replaced = false;
1439   unsigned NumInputs = getPHINumInputs(PHI);
1440   int SingleExternalEntryIndex = -1;
1441   for (unsigned i = 0; i < NumInputs; ++i) {
1442     if (!isPHIRegionIndex(PHIIndices, i)) {
1443       if (SingleExternalEntryIndex == -1) {
1444         // Single entry
1445         SingleExternalEntryIndex = i;
1446       } else {
1447         // Multiple entries
1448         SingleExternalEntryIndex = -2;
1449       }
1450     }
1451   }
1452 
1453   if (SingleExternalEntryIndex > -1) {
1454     *ReplaceReg = getPHISourceReg(PHI, SingleExternalEntryIndex);
1455     // We should not rewrite the code, we should only pick up the single value
1456     // that represents the shrunk PHI.
1457     Replaced = true;
1458   } else {
1459     MachineBasicBlock *MBB = PHI.getParent();
1460     MachineInstrBuilder MIB =
1461         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1462                 getPHIDestReg(PHI));
1463     if (SourceMBB) {
1464       MIB.addReg(CombinedSourceReg);
1465       MIB.addMBB(SourceMBB);
1466       LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1467                         << printMBBReference(*SourceMBB));
1468     }
1469 
1470     for (unsigned i = 0; i < NumInputs; ++i) {
1471       if (isPHIRegionIndex(PHIIndices, i)) {
1472         continue;
1473       }
1474       unsigned SourceReg = getPHISourceReg(PHI, i);
1475       MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1476       MIB.addReg(SourceReg);
1477       MIB.addMBB(SourcePred);
1478       LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1479                         << printMBBReference(*SourcePred));
1480     }
1481     LLVM_DEBUG(dbgs() << ")\n");
1482   }
1483   PHI.eraseFromParent();
1484   return Replaced;
1485 }
1486 
1487 void AMDGPUMachineCFGStructurizer::replacePHI(
1488     MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *LastMerge,
1489     SmallVector<unsigned, 2> &PHIRegionIndices) {
1490   LLVM_DEBUG(dbgs() << "Replace PHI: ");
1491   LLVM_DEBUG(PHI.dump());
1492   LLVM_DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI)
1493                     << " = PHI(");
1494 
1495   bool HasExternalEdge = false;
1496   unsigned NumInputs = getPHINumInputs(PHI);
1497   for (unsigned i = 0; i < NumInputs; ++i) {
1498     if (!isPHIRegionIndex(PHIRegionIndices, i)) {
1499       HasExternalEdge = true;
1500     }
1501   }
1502 
1503   if (HasExternalEdge) {
1504     MachineBasicBlock *MBB = PHI.getParent();
1505     MachineInstrBuilder MIB =
1506         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1507                 getPHIDestReg(PHI));
1508     MIB.addReg(CombinedSourceReg);
1509     MIB.addMBB(LastMerge);
1510     LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1511                       << printMBBReference(*LastMerge));
1512     for (unsigned i = 0; i < NumInputs; ++i) {
1513       if (isPHIRegionIndex(PHIRegionIndices, i)) {
1514         continue;
1515       }
1516       unsigned SourceReg = getPHISourceReg(PHI, i);
1517       MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1518       MIB.addReg(SourceReg);
1519       MIB.addMBB(SourcePred);
1520       LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1521                         << printMBBReference(*SourcePred));
1522     }
1523     LLVM_DEBUG(dbgs() << ")\n");
1524   } else {
1525     replaceRegisterWith(getPHIDestReg(PHI), CombinedSourceReg);
1526   }
1527   PHI.eraseFromParent();
1528 }
1529 
1530 void AMDGPUMachineCFGStructurizer::replaceEntryPHI(
1531     MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *IfMBB,
1532     SmallVector<unsigned, 2> &PHIRegionIndices) {
1533   LLVM_DEBUG(dbgs() << "Replace entry PHI: ");
1534   LLVM_DEBUG(PHI.dump());
1535   LLVM_DEBUG(dbgs() << " with ");
1536 
1537   unsigned NumInputs = getPHINumInputs(PHI);
1538   unsigned NumNonRegionInputs = NumInputs;
1539   for (unsigned i = 0; i < NumInputs; ++i) {
1540     if (isPHIRegionIndex(PHIRegionIndices, i)) {
1541       NumNonRegionInputs--;
1542     }
1543   }
1544 
1545   if (NumNonRegionInputs == 0) {
1546     auto DestReg = getPHIDestReg(PHI);
1547     replaceRegisterWith(DestReg, CombinedSourceReg);
1548     LLVM_DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI)
1549                       << "\n");
1550     PHI.eraseFromParent();
1551   } else {
1552     LLVM_DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI(");
1553     MachineBasicBlock *MBB = PHI.getParent();
1554     MachineInstrBuilder MIB =
1555         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1556                 getPHIDestReg(PHI));
1557     MIB.addReg(CombinedSourceReg);
1558     MIB.addMBB(IfMBB);
1559     LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1560                       << printMBBReference(*IfMBB));
1561     unsigned NumInputs = getPHINumInputs(PHI);
1562     for (unsigned i = 0; i < NumInputs; ++i) {
1563       if (isPHIRegionIndex(PHIRegionIndices, i)) {
1564         continue;
1565       }
1566       unsigned SourceReg = getPHISourceReg(PHI, i);
1567       MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1568       MIB.addReg(SourceReg);
1569       MIB.addMBB(SourcePred);
1570       LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1571                         << printMBBReference(*SourcePred));
1572     }
1573     LLVM_DEBUG(dbgs() << ")\n");
1574     PHI.eraseFromParent();
1575   }
1576 }
1577 
1578 void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs(
1579     MachineInstr &PHI, SmallVector<unsigned, 2> &PHIRegionIndices,
1580     unsigned CombinedSourceReg, LinearizedRegion *LRegion) {
1581   bool WasLiveOut = false;
1582   for (auto PII : PHIRegionIndices) {
1583     unsigned Reg = getPHISourceReg(PHI, PII);
1584     if (LRegion->isLiveOut(Reg)) {
1585       bool IsDead = true;
1586 
1587       // Check if register is live out of the basic block
1588       MachineBasicBlock *DefMBB = getDefInstr(Reg)->getParent();
1589       for (auto UI = MRI->use_begin(Reg), E = MRI->use_end(); UI != E; ++UI) {
1590         if ((*UI).getParent()->getParent() != DefMBB) {
1591           IsDead = false;
1592         }
1593       }
1594 
1595       LLVM_DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is "
1596                         << (IsDead ? "dead" : "alive")
1597                         << " after PHI replace\n");
1598       if (IsDead) {
1599         LRegion->removeLiveOut(Reg);
1600       }
1601       WasLiveOut = true;
1602     }
1603   }
1604 
1605   if (WasLiveOut)
1606     LRegion->addLiveOut(CombinedSourceReg);
1607 }
1608 
1609 void AMDGPUMachineCFGStructurizer::rewriteRegionExitPHI(RegionMRT *Region,
1610                                                   MachineBasicBlock *LastMerge,
1611                                                   MachineInstr &PHI,
1612                                                   LinearizedRegion *LRegion) {
1613   SmallVector<unsigned, 2> PHIRegionIndices;
1614   getPHIRegionIndices(Region, PHI, PHIRegionIndices);
1615   unsigned LinearizedSourceReg =
1616       storePHILinearizationInfo(PHI, &PHIRegionIndices);
1617 
1618   replacePHI(PHI, LinearizedSourceReg, LastMerge, PHIRegionIndices);
1619   replaceLiveOutRegs(PHI, PHIRegionIndices, LinearizedSourceReg, LRegion);
1620 }
1621 
1622 void AMDGPUMachineCFGStructurizer::rewriteRegionEntryPHI(LinearizedRegion *Region,
1623                                                    MachineBasicBlock *IfMBB,
1624                                                    MachineInstr &PHI) {
1625   SmallVector<unsigned, 2> PHINonRegionIndices;
1626   getPHINonRegionIndices(Region, PHI, PHINonRegionIndices);
1627   unsigned LinearizedSourceReg =
1628       storePHILinearizationInfo(PHI, &PHINonRegionIndices);
1629   replaceEntryPHI(PHI, LinearizedSourceReg, IfMBB, PHINonRegionIndices);
1630 }
1631 
1632 static void collectPHIs(MachineBasicBlock *MBB,
1633                         SmallVector<MachineInstr *, 2> &PHIs) {
1634   for (auto &BBI : *MBB) {
1635     if (BBI.isPHI()) {
1636       PHIs.push_back(&BBI);
1637     }
1638   }
1639 }
1640 
1641 void AMDGPUMachineCFGStructurizer::rewriteRegionExitPHIs(RegionMRT *Region,
1642                                                    MachineBasicBlock *LastMerge,
1643                                                    LinearizedRegion *LRegion) {
1644   SmallVector<MachineInstr *, 2> PHIs;
1645   auto Exit = Region->getSucc();
1646   if (Exit == nullptr)
1647     return;
1648 
1649   collectPHIs(Exit, PHIs);
1650 
1651   for (auto PHII : PHIs) {
1652     rewriteRegionExitPHI(Region, LastMerge, *PHII, LRegion);
1653   }
1654 }
1655 
1656 void AMDGPUMachineCFGStructurizer::rewriteRegionEntryPHIs(LinearizedRegion *Region,
1657                                                     MachineBasicBlock *IfMBB) {
1658   SmallVector<MachineInstr *, 2> PHIs;
1659   auto Entry = Region->getEntry();
1660 
1661   collectPHIs(Entry, PHIs);
1662 
1663   for (auto PHII : PHIs) {
1664     rewriteRegionEntryPHI(Region, IfMBB, *PHII);
1665   }
1666 }
1667 
1668 void AMDGPUMachineCFGStructurizer::insertUnconditionalBranch(MachineBasicBlock *MBB,
1669                                                        MachineBasicBlock *Dest,
1670                                                        const DebugLoc &DL) {
1671   LLVM_DEBUG(dbgs() << "Inserting unconditional branch: " << MBB->getNumber()
1672                     << " -> " << Dest->getNumber() << "\n");
1673   MachineBasicBlock::instr_iterator Terminator = MBB->getFirstInstrTerminator();
1674   bool HasTerminator = Terminator != MBB->instr_end();
1675   if (HasTerminator) {
1676     TII->ReplaceTailWithBranchTo(Terminator, Dest);
1677   }
1678   if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(Dest)) {
1679     TII->insertUnconditionalBranch(*MBB, Dest, DL);
1680   }
1681 }
1682 
1683 static MachineBasicBlock *getSingleExitNode(MachineFunction &MF) {
1684   MachineBasicBlock *result = nullptr;
1685   for (auto &MFI : MF) {
1686     if (MFI.succ_empty()) {
1687       if (result == nullptr) {
1688         result = &MFI;
1689       } else {
1690         return nullptr;
1691       }
1692     }
1693   }
1694 
1695   return result;
1696 }
1697 
1698 static bool hasOneExitNode(MachineFunction &MF) {
1699   return getSingleExitNode(MF) != nullptr;
1700 }
1701 
1702 MachineBasicBlock *
1703 AMDGPUMachineCFGStructurizer::createLinearizedExitBlock(RegionMRT *Region) {
1704   auto Exit = Region->getSucc();
1705 
1706   // If the exit is the end of the function, we just use the existing
1707   MachineFunction *MF = Region->getEntry()->getParent();
1708   if (Exit == nullptr && hasOneExitNode(*MF)) {
1709     return &(*(--(Region->getEntry()->getParent()->end())));
1710   }
1711 
1712   MachineBasicBlock *LastMerge = MF->CreateMachineBasicBlock();
1713   if (Exit == nullptr) {
1714     MachineFunction::iterator ExitIter = MF->end();
1715     MF->insert(ExitIter, LastMerge);
1716   } else {
1717     MachineFunction::iterator ExitIter = Exit->getIterator();
1718     MF->insert(ExitIter, LastMerge);
1719     LastMerge->addSuccessor(Exit);
1720     insertUnconditionalBranch(LastMerge, Exit);
1721     LLVM_DEBUG(dbgs() << "Created exit block: " << LastMerge->getNumber()
1722                       << "\n");
1723   }
1724   return LastMerge;
1725 }
1726 
1727 void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB,
1728                                             MachineBasicBlock *CodeBB,
1729                                             MachineBasicBlock *MergeBB,
1730                                             unsigned DestRegister,
1731                                             unsigned IfSourceRegister,
1732                                             unsigned CodeSourceRegister,
1733                                             bool IsUndefIfSource) {
1734   // If this is the function exit block, we don't need a phi.
1735   if (MergeBB->succ_begin() == MergeBB->succ_end()) {
1736     return;
1737   }
1738   LLVM_DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB)
1739                     << "): " << printReg(DestRegister, TRI) << " = PHI("
1740                     << printReg(IfSourceRegister, TRI) << ", "
1741                     << printMBBReference(*IfBB)
1742                     << printReg(CodeSourceRegister, TRI) << ", "
1743                     << printMBBReference(*CodeBB) << ")\n");
1744   const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin());
1745   MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
1746                                     TII->get(TargetOpcode::PHI), DestRegister);
1747   if (IsUndefIfSource && false) {
1748     MIB.addReg(IfSourceRegister, RegState::Undef);
1749   } else {
1750     MIB.addReg(IfSourceRegister);
1751   }
1752   MIB.addMBB(IfBB);
1753   MIB.addReg(CodeSourceRegister);
1754   MIB.addMBB(CodeBB);
1755 }
1756 
1757 static void removeExternalCFGSuccessors(MachineBasicBlock *MBB) {
1758   for (MachineBasicBlock::succ_iterator PI = MBB->succ_begin(),
1759                                         E = MBB->succ_end();
1760        PI != E; ++PI) {
1761     if ((*PI) != MBB) {
1762       (MBB)->removeSuccessor(*PI);
1763     }
1764   }
1765 }
1766 
1767 static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
1768                                    MachineBasicBlock *EndMBB) {
1769 
1770   // We have to check against the StartMBB successor because a
1771   // structurized region with a loop will have the entry block split,
1772   // and the backedge will go to the entry successor.
1773   DenseSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>> Succs;
1774   unsigned SuccSize = StartMBB->succ_size();
1775   if (SuccSize > 0) {
1776     MachineBasicBlock *StartMBBSucc = *(StartMBB->succ_begin());
1777     for (MachineBasicBlock::succ_iterator PI = EndMBB->succ_begin(),
1778                                           E = EndMBB->succ_end();
1779          PI != E; ++PI) {
1780       // Either we have a back-edge to the entry block, or a back-edge to the
1781       // successor of the entry block since the block may be split.
1782       if ((*PI) != StartMBB &&
1783           !((*PI) == StartMBBSucc && StartMBB != EndMBB && SuccSize == 1)) {
1784         Succs.insert(
1785             std::pair<MachineBasicBlock *, MachineBasicBlock *>(EndMBB, *PI));
1786       }
1787     }
1788   }
1789 
1790   for (MachineBasicBlock::pred_iterator PI = StartMBB->pred_begin(),
1791                                         E = StartMBB->pred_end();
1792        PI != E; ++PI) {
1793     if ((*PI) != EndMBB) {
1794       Succs.insert(
1795           std::pair<MachineBasicBlock *, MachineBasicBlock *>(*PI, StartMBB));
1796     }
1797   }
1798 
1799   for (auto SI : Succs) {
1800     std::pair<MachineBasicBlock *, MachineBasicBlock *> Edge = SI;
1801     LLVM_DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first)
1802                       << " -> " << printMBBReference(*Edge.second) << "\n");
1803     Edge.first->removeSuccessor(Edge.second);
1804   }
1805 }
1806 
1807 MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock(
1808     MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBBStart,
1809     MachineBasicBlock *CodeBBEnd, MachineBasicBlock *SelectBB, unsigned IfReg,
1810     bool InheritPreds) {
1811   MachineFunction *MF = MergeBB->getParent();
1812   MachineBasicBlock *IfBB = MF->CreateMachineBasicBlock();
1813 
1814   if (InheritPreds) {
1815     for (MachineBasicBlock::pred_iterator PI = CodeBBStart->pred_begin(),
1816                                           E = CodeBBStart->pred_end();
1817          PI != E; ++PI) {
1818       if ((*PI) != CodeBBEnd) {
1819         MachineBasicBlock *Pred = (*PI);
1820         Pred->addSuccessor(IfBB);
1821       }
1822     }
1823   }
1824 
1825   removeExternalCFGEdges(CodeBBStart, CodeBBEnd);
1826 
1827   auto CodeBBStartI = CodeBBStart->getIterator();
1828   auto CodeBBEndI = CodeBBEnd->getIterator();
1829   auto MergeIter = MergeBB->getIterator();
1830   MF->insert(MergeIter, IfBB);
1831   MF->splice(MergeIter, CodeBBStartI, ++CodeBBEndI);
1832   IfBB->addSuccessor(MergeBB);
1833   IfBB->addSuccessor(CodeBBStart);
1834 
1835   LLVM_DEBUG(dbgs() << "Created If block: " << IfBB->getNumber() << "\n");
1836   // Ensure that the MergeBB is a successor of the CodeEndBB.
1837   if (!CodeBBEnd->isSuccessor(MergeBB))
1838     CodeBBEnd->addSuccessor(MergeBB);
1839 
1840   LLVM_DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart)
1841                     << " through " << printMBBReference(*CodeBBEnd) << "\n");
1842 
1843   // If we have a single predecessor we can find a reasonable debug location
1844   MachineBasicBlock *SinglePred =
1845       CodeBBStart->pred_size() == 1 ? *(CodeBBStart->pred_begin()) : nullptr;
1846   const DebugLoc &DL = SinglePred
1847                     ? SinglePred->findDebugLoc(SinglePred->getFirstTerminator())
1848                     : DebugLoc();
1849 
1850   Register Reg =
1851       TII->insertEQ(IfBB, IfBB->begin(), DL, IfReg,
1852                     SelectBB->getNumber() /* CodeBBStart->getNumber() */);
1853   if (&(*(IfBB->getParent()->begin())) == IfBB) {
1854     TII->materializeImmediate(*IfBB, IfBB->begin(), DL, IfReg,
1855                               CodeBBStart->getNumber());
1856   }
1857   MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1858   ArrayRef<MachineOperand> Cond(RegOp);
1859   TII->insertBranch(*IfBB, MergeBB, CodeBBStart, Cond, DL);
1860 
1861   return IfBB;
1862 }
1863 
1864 void AMDGPUMachineCFGStructurizer::ensureCondIsNotKilled(
1865     SmallVector<MachineOperand, 1> Cond) {
1866   if (Cond.size() != 1)
1867     return;
1868   if (!Cond[0].isReg())
1869     return;
1870 
1871   Register CondReg = Cond[0].getReg();
1872   for (auto UI = MRI->use_begin(CondReg), E = MRI->use_end(); UI != E; ++UI) {
1873     (*UI).setIsKill(false);
1874   }
1875 }
1876 
1877 void AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(MachineBasicBlock *CodeBB,
1878                                                      MachineBasicBlock *MergeBB,
1879                                                      unsigned BBSelectReg) {
1880   MachineBasicBlock *TrueBB = nullptr;
1881   MachineBasicBlock *FalseBB = nullptr;
1882   SmallVector<MachineOperand, 1> Cond;
1883   MachineBasicBlock *FallthroughBB = FallthroughMap[CodeBB];
1884   TII->analyzeBranch(*CodeBB, TrueBB, FalseBB, Cond);
1885 
1886   const DebugLoc &DL = CodeBB->findDebugLoc(CodeBB->getFirstTerminator());
1887 
1888   if (FalseBB == nullptr && TrueBB == nullptr && FallthroughBB == nullptr) {
1889     // This is an exit block, hence no successors. We will assign the
1890     // bb select register to the entry block.
1891     TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1892                               BBSelectReg,
1893                               CodeBB->getParent()->begin()->getNumber());
1894     insertUnconditionalBranch(CodeBB, MergeBB, DL);
1895     return;
1896   }
1897 
1898   if (FalseBB == nullptr && TrueBB == nullptr) {
1899     TrueBB = FallthroughBB;
1900   } else if (TrueBB != nullptr) {
1901     FalseBB =
1902         (FallthroughBB && (FallthroughBB != TrueBB)) ? FallthroughBB : FalseBB;
1903   }
1904 
1905   if ((TrueBB != nullptr && FalseBB == nullptr) || (TrueBB == FalseBB)) {
1906     TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1907                               BBSelectReg, TrueBB->getNumber());
1908   } else {
1909     const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
1910     Register TrueBBReg = MRI->createVirtualRegister(RegClass);
1911     Register FalseBBReg = MRI->createVirtualRegister(RegClass);
1912     TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1913                               TrueBBReg, TrueBB->getNumber());
1914     TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1915                               FalseBBReg, FalseBB->getNumber());
1916     ensureCondIsNotKilled(Cond);
1917     TII->insertVectorSelect(*CodeBB, CodeBB->getFirstTerminator(), DL,
1918                             BBSelectReg, Cond, TrueBBReg, FalseBBReg);
1919   }
1920 
1921   insertUnconditionalBranch(CodeBB, MergeBB, DL);
1922 }
1923 
1924 MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) {
1925   if (MRI->def_begin(Reg) == MRI->def_end()) {
1926     LLVM_DEBUG(dbgs() << "Register "
1927                       << printReg(Reg, MRI->getTargetRegisterInfo())
1928                       << " has NO defs\n");
1929   } else if (!MRI->hasOneDef(Reg)) {
1930     LLVM_DEBUG(dbgs() << "Register "
1931                       << printReg(Reg, MRI->getTargetRegisterInfo())
1932                       << " has multiple defs\n");
1933     LLVM_DEBUG(dbgs() << "DEFS BEGIN:\n");
1934     for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) {
1935       LLVM_DEBUG(DI->getParent()->dump());
1936     }
1937     LLVM_DEBUG(dbgs() << "DEFS END\n");
1938   }
1939 
1940   assert(MRI->hasOneDef(Reg) && "Register has multiple definitions");
1941   return (*(MRI->def_begin(Reg))).getParent();
1942 }
1943 
1944 void AMDGPUMachineCFGStructurizer::insertChainedPHI(MachineBasicBlock *IfBB,
1945                                               MachineBasicBlock *CodeBB,
1946                                               MachineBasicBlock *MergeBB,
1947                                               LinearizedRegion *InnerRegion,
1948                                               unsigned DestReg,
1949                                               unsigned SourceReg) {
1950   // In this function we know we are part of a chain already, so we need
1951   // to add the registers to the existing chain, and rename the register
1952   // inside the region.
1953   bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit();
1954   MachineInstr *DefInstr = getDefInstr(SourceReg);
1955   if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) {
1956     // Handle the case where the def is a PHI-def inside a basic
1957     // block, then we only need to do renaming. Special care needs to
1958     // be taken if the PHI-def is part of an existing chain, or if a
1959     // new one needs to be created.
1960     InnerRegion->replaceRegisterInsideRegion(SourceReg, DestReg, true, MRI);
1961 
1962     // We collect all PHI Information, and if we are at the region entry,
1963     // all PHIs will be removed, and then re-introduced if needed.
1964     storePHILinearizationInfoDest(DestReg, *DefInstr);
1965     // We have picked up all the information we need now and can remove
1966     // the PHI
1967     PHIInfo.removeSource(DestReg, SourceReg, CodeBB);
1968     DefInstr->eraseFromParent();
1969   } else {
1970     // If this is not a phi-def, or it is a phi-def but from a linearized region
1971     if (IsSingleBB && DefInstr->getParent() == InnerRegion->getEntry()) {
1972       // If this is a single BB and the definition is in this block we
1973       // need to replace any uses outside the region.
1974       InnerRegion->replaceRegisterOutsideRegion(SourceReg, DestReg, false, MRI);
1975     }
1976     const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
1977     Register NextDestReg = MRI->createVirtualRegister(RegClass);
1978     bool IsLastDef = PHIInfo.getNumSources(DestReg) == 1;
1979     LLVM_DEBUG(dbgs() << "Insert Chained PHI\n");
1980     insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, DestReg, NextDestReg,
1981                    SourceReg, IsLastDef);
1982 
1983     PHIInfo.removeSource(DestReg, SourceReg, CodeBB);
1984     if (IsLastDef) {
1985       const DebugLoc &DL = IfBB->findDebugLoc(IfBB->getFirstTerminator());
1986       TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DL,
1987                                 NextDestReg, 0);
1988       PHIInfo.deleteDef(DestReg);
1989     } else {
1990       PHIInfo.replaceDef(DestReg, NextDestReg);
1991     }
1992   }
1993 }
1994 
1995 bool AMDGPUMachineCFGStructurizer::containsDef(MachineBasicBlock *MBB,
1996                                          LinearizedRegion *InnerRegion,
1997                                          unsigned Register) {
1998   return getDefInstr(Register)->getParent() == MBB ||
1999          InnerRegion->contains(getDefInstr(Register)->getParent());
2000 }
2001 
2002 void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB,
2003                                                 MachineBasicBlock *CodeBB,
2004                                                 MachineBasicBlock *MergeBB,
2005                                                 LinearizedRegion *InnerRegion,
2006                                                 LinearizedRegion *LRegion) {
2007   DenseSet<unsigned> *LiveOuts = InnerRegion->getLiveOuts();
2008   SmallVector<unsigned, 4> OldLiveOuts;
2009   bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit();
2010   for (auto OLI : *LiveOuts) {
2011     OldLiveOuts.push_back(OLI);
2012   }
2013 
2014   for (auto LI : OldLiveOuts) {
2015     LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
2016     if (!containsDef(CodeBB, InnerRegion, LI) ||
2017         (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
2018       // If the register simply lives through the CodeBB, we don't have
2019       // to rewrite anything since the register is not defined in this
2020       // part of the code.
2021       LLVM_DEBUG(dbgs() << "- through");
2022       continue;
2023     }
2024     LLVM_DEBUG(dbgs() << "\n");
2025     unsigned Reg = LI;
2026     if (/*!PHIInfo.isSource(Reg) &&*/ Reg != InnerRegion->getBBSelectRegOut()) {
2027       // If the register is live out, we do want to create a phi,
2028       // unless it is from the Exit block, because in that case there
2029       // is already a PHI, and no need to create a new one.
2030 
2031       // If the register is just a live out def and not part of a phi
2032       // chain, we need to create a PHI node to handle the if region,
2033       // and replace all uses outside of the region with the new dest
2034       // register, unless it is the outgoing BB select register. We have
2035       // already created phi nodes for these.
2036       const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2037       Register PHIDestReg = MRI->createVirtualRegister(RegClass);
2038       Register IfSourceReg = MRI->createVirtualRegister(RegClass);
2039       // Create initializer, this value is never used, but is needed
2040       // to satisfy SSA.
2041       LLVM_DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
2042       TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(),
2043                         IfSourceReg, 0);
2044 
2045       InnerRegion->replaceRegisterOutsideRegion(Reg, PHIDestReg, true, MRI);
2046       LLVM_DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n");
2047       insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, PHIDestReg,
2048                      IfSourceReg, Reg, true);
2049     }
2050   }
2051 
2052   // Handle the chained definitions in PHIInfo, checking if this basic block
2053   // is a source block for a definition.
2054   SmallVector<unsigned, 4> Sources;
2055   if (PHIInfo.findSourcesFromMBB(CodeBB, Sources)) {
2056     LLVM_DEBUG(dbgs() << "Inserting PHI Live Out from "
2057                       << printMBBReference(*CodeBB) << "\n");
2058     for (auto SI : Sources) {
2059       unsigned DestReg;
2060       PHIInfo.findDest(SI, CodeBB, DestReg);
2061       insertChainedPHI(IfBB, CodeBB, MergeBB, InnerRegion, DestReg, SI);
2062     }
2063     LLVM_DEBUG(dbgs() << "Insertion done.\n");
2064   }
2065 
2066   LLVM_DEBUG(PHIInfo.dump(MRI));
2067 }
2068 
2069 void AMDGPUMachineCFGStructurizer::prunePHIInfo(MachineBasicBlock *MBB) {
2070   LLVM_DEBUG(dbgs() << "Before PHI Prune\n");
2071   LLVM_DEBUG(PHIInfo.dump(MRI));
2072   SmallVector<std::tuple<unsigned, unsigned, MachineBasicBlock *>, 4>
2073       ElimiatedSources;
2074   for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2075        ++DRI) {
2076 
2077     unsigned DestReg = *DRI;
2078     auto SE = PHIInfo.sources_end(DestReg);
2079 
2080     bool MBBContainsPHISource = false;
2081     // Check if there is a PHI source in this MBB
2082     for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2083       unsigned SourceReg = (*SRI).first;
2084       MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2085       if (Def->getParent()->getParent() == MBB) {
2086         MBBContainsPHISource = true;
2087       }
2088     }
2089 
2090     // If so, all other sources are useless since we know this block
2091     // is always executed when the region is executed.
2092     if (MBBContainsPHISource) {
2093       for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2094         PHILinearize::PHISourceT Source = *SRI;
2095         unsigned SourceReg = Source.first;
2096         MachineBasicBlock *SourceMBB = Source.second;
2097         MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2098         if (Def->getParent()->getParent() != MBB) {
2099           ElimiatedSources.push_back(
2100               std::make_tuple(DestReg, SourceReg, SourceMBB));
2101         }
2102       }
2103     }
2104   }
2105 
2106   // Remove the PHI sources that are in the given MBB
2107   for (auto &SourceInfo : ElimiatedSources) {
2108     PHIInfo.removeSource(std::get<0>(SourceInfo), std::get<1>(SourceInfo),
2109                          std::get<2>(SourceInfo));
2110   }
2111   LLVM_DEBUG(dbgs() << "After PHI Prune\n");
2112   LLVM_DEBUG(PHIInfo.dump(MRI));
2113 }
2114 
2115 void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegion,
2116                                             unsigned DestReg) {
2117   MachineBasicBlock *Entry = CurrentRegion->getEntry();
2118   MachineBasicBlock *Exit = CurrentRegion->getExit();
2119 
2120   LLVM_DEBUG(dbgs() << "RegionExit: " << Exit->getNumber() << " Pred: "
2121                     << (*(Entry->pred_begin()))->getNumber() << "\n");
2122 
2123   int NumSources = 0;
2124   auto SE = PHIInfo.sources_end(DestReg);
2125 
2126   for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2127     NumSources++;
2128   }
2129 
2130   if (NumSources == 1) {
2131     auto SRI = PHIInfo.sources_begin(DestReg);
2132     unsigned SourceReg = (*SRI).first;
2133     replaceRegisterWith(DestReg, SourceReg);
2134   } else {
2135     const DebugLoc &DL = Entry->findDebugLoc(Entry->begin());
2136     MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL,
2137                                       TII->get(TargetOpcode::PHI), DestReg);
2138     LLVM_DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI(");
2139 
2140     unsigned CurrentBackedgeReg = 0;
2141 
2142     for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2143       unsigned SourceReg = (*SRI).first;
2144 
2145       if (CurrentRegion->contains((*SRI).second)) {
2146         if (CurrentBackedgeReg == 0) {
2147           CurrentBackedgeReg = SourceReg;
2148         } else {
2149           MachineInstr *PHIDefInstr = getDefInstr(SourceReg);
2150           MachineBasicBlock *PHIDefMBB = PHIDefInstr->getParent();
2151           const TargetRegisterClass *RegClass =
2152               MRI->getRegClass(CurrentBackedgeReg);
2153           Register NewBackedgeReg = MRI->createVirtualRegister(RegClass);
2154           MachineInstrBuilder BackedgePHI =
2155               BuildMI(*PHIDefMBB, PHIDefMBB->instr_begin(), DL,
2156                       TII->get(TargetOpcode::PHI), NewBackedgeReg);
2157           BackedgePHI.addReg(CurrentBackedgeReg);
2158           BackedgePHI.addMBB(getPHIPred(*PHIDefInstr, 0));
2159           BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1));
2160           BackedgePHI.addMBB((*SRI).second);
2161           CurrentBackedgeReg = NewBackedgeReg;
2162           LLVM_DEBUG(dbgs()
2163                      << "Inserting backedge PHI: "
2164                      << printReg(NewBackedgeReg, TRI) << " = PHI("
2165                      << printReg(CurrentBackedgeReg, TRI) << ", "
2166                      << printMBBReference(*getPHIPred(*PHIDefInstr, 0)) << ", "
2167                      << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", "
2168                      << printMBBReference(*(*SRI).second));
2169         }
2170       } else {
2171         MIB.addReg(SourceReg);
2172         MIB.addMBB((*SRI).second);
2173         LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
2174                           << printMBBReference(*(*SRI).second) << ", ");
2175       }
2176     }
2177 
2178     // Add the final backedge register source to the entry phi
2179     if (CurrentBackedgeReg != 0) {
2180       MIB.addReg(CurrentBackedgeReg);
2181       MIB.addMBB(Exit);
2182       LLVM_DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", "
2183                         << printMBBReference(*Exit) << ")\n");
2184     } else {
2185       LLVM_DEBUG(dbgs() << ")\n");
2186     }
2187   }
2188 }
2189 
2190 void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegion) {
2191   LLVM_DEBUG(PHIInfo.dump(MRI));
2192 
2193   for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2194        ++DRI) {
2195 
2196     unsigned DestReg = *DRI;
2197     createEntryPHI(CurrentRegion, DestReg);
2198   }
2199   PHIInfo.clear();
2200 }
2201 
2202 void AMDGPUMachineCFGStructurizer::replaceRegisterWith(
2203     unsigned Register, class Register NewRegister) {
2204   assert(Register != NewRegister && "Cannot replace a reg with itself");
2205 
2206   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
2207                                          E = MRI->reg_end();
2208        I != E;) {
2209     MachineOperand &O = *I;
2210     ++I;
2211     if (NewRegister.isPhysical()) {
2212       LLVM_DEBUG(dbgs() << "Trying to substitute physical register: "
2213                         << printReg(NewRegister, MRI->getTargetRegisterInfo())
2214                         << "\n");
2215       llvm_unreachable("Cannot substitute physical registers");
2216       // We don't handle physical registers, but if we need to
2217       // in the future This is how we do it:
2218       // O.substPhysReg(NewRegister, *TRI);
2219     } else {
2220       LLVM_DEBUG(dbgs() << "Replacing register: "
2221                         << printReg(Register, MRI->getTargetRegisterInfo())
2222                         << " with "
2223                         << printReg(NewRegister, MRI->getTargetRegisterInfo())
2224                         << "\n");
2225       O.setReg(NewRegister);
2226     }
2227   }
2228   PHIInfo.deleteDef(Register);
2229 
2230   getRegionMRT()->replaceLiveOutReg(Register, NewRegister);
2231 
2232   LLVM_DEBUG(PHIInfo.dump(MRI));
2233 }
2234 
2235 void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEntry) {
2236   LLVM_DEBUG(dbgs() << "Resolve PHI Infos\n");
2237   LLVM_DEBUG(PHIInfo.dump(MRI));
2238   for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2239        ++DRI) {
2240     unsigned DestReg = *DRI;
2241     LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n");
2242     auto SRI = PHIInfo.sources_begin(DestReg);
2243     unsigned SourceReg = (*SRI).first;
2244     LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI)
2245                       << " SourceReg: " << printReg(SourceReg, TRI) << "\n");
2246 
2247     assert(PHIInfo.sources_end(DestReg) == ++SRI &&
2248            "More than one phi source in entry node");
2249     replaceRegisterWith(DestReg, SourceReg);
2250   }
2251 }
2252 
2253 static bool isFunctionEntryBlock(MachineBasicBlock *MBB) {
2254   return ((&(*(MBB->getParent()->begin()))) == MBB);
2255 }
2256 
2257 MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
2258     MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBB,
2259     LinearizedRegion *CurrentRegion, unsigned BBSelectRegIn,
2260     unsigned BBSelectRegOut) {
2261   if (isFunctionEntryBlock(CodeBB) && !CurrentRegion->getHasLoop()) {
2262     // Handle non-loop function entry block.
2263     // We need to allow loops to the entry block and then
2264     rewriteCodeBBTerminator(CodeBB, MergeBB, BBSelectRegOut);
2265     resolvePHIInfos(CodeBB);
2266     removeExternalCFGSuccessors(CodeBB);
2267     CodeBB->addSuccessor(MergeBB);
2268     CurrentRegion->addMBB(CodeBB);
2269     return nullptr;
2270   }
2271   if (CurrentRegion->getEntry() == CodeBB && !CurrentRegion->getHasLoop()) {
2272     // Handle non-loop region entry block.
2273     MachineFunction *MF = MergeBB->getParent();
2274     auto MergeIter = MergeBB->getIterator();
2275     auto CodeBBStartIter = CodeBB->getIterator();
2276     auto CodeBBEndIter = ++(CodeBB->getIterator());
2277     if (CodeBBEndIter != MergeIter) {
2278       MF->splice(MergeIter, CodeBBStartIter, CodeBBEndIter);
2279     }
2280     rewriteCodeBBTerminator(CodeBB, MergeBB, BBSelectRegOut);
2281     prunePHIInfo(CodeBB);
2282     createEntryPHIs(CurrentRegion);
2283     removeExternalCFGSuccessors(CodeBB);
2284     CodeBB->addSuccessor(MergeBB);
2285     CurrentRegion->addMBB(CodeBB);
2286     return nullptr;
2287   } else {
2288     // Handle internal block.
2289     const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2290     Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2291     rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
2292     bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
2293     MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
2294                                             BBSelectRegIn, IsRegionEntryBB);
2295     CurrentRegion->addMBB(IfBB);
2296     // If this is the entry block we need to make the If block the new
2297     // linearized region entry.
2298     if (IsRegionEntryBB) {
2299       CurrentRegion->setEntry(IfBB);
2300 
2301       if (CurrentRegion->getHasLoop()) {
2302         MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2303         MachineBasicBlock *ETrueBB = nullptr;
2304         MachineBasicBlock *EFalseBB = nullptr;
2305         SmallVector<MachineOperand, 1> ECond;
2306 
2307         const DebugLoc &DL = DebugLoc();
2308         TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2309         TII->removeBranch(*RegionExit);
2310 
2311         // We need to create a backedge if there is a loop
2312         Register Reg = TII->insertNE(
2313             RegionExit, RegionExit->instr_end(), DL,
2314             CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2315             CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2316         MachineOperand RegOp =
2317             MachineOperand::CreateReg(Reg, false, false, true);
2318         ArrayRef<MachineOperand> Cond(RegOp);
2319         LLVM_DEBUG(dbgs() << "RegionExitReg: ");
2320         LLVM_DEBUG(Cond[0].print(dbgs(), TRI));
2321         LLVM_DEBUG(dbgs() << "\n");
2322         TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2323                           Cond, DebugLoc());
2324         RegionExit->addSuccessor(CurrentRegion->getEntry());
2325       }
2326     }
2327     CurrentRegion->addMBB(CodeBB);
2328     LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
2329 
2330     InnerRegion.setParent(CurrentRegion);
2331     LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n");
2332     insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2333                    CodeBBSelectReg);
2334     InnerRegion.addMBB(MergeBB);
2335 
2336     LLVM_DEBUG(InnerRegion.print(dbgs(), TRI));
2337     rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
2338     extractKilledPHIs(CodeBB);
2339     if (IsRegionEntryBB) {
2340       createEntryPHIs(CurrentRegion);
2341     }
2342     return IfBB;
2343   }
2344 }
2345 
2346 MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
2347     MachineBasicBlock *MergeBB, LinearizedRegion *InnerRegion,
2348     LinearizedRegion *CurrentRegion, MachineBasicBlock *SelectBB,
2349     unsigned BBSelectRegIn, unsigned BBSelectRegOut) {
2350   unsigned CodeBBSelectReg =
2351       InnerRegion->getRegionMRT()->getInnerOutputRegister();
2352   MachineBasicBlock *CodeEntryBB = InnerRegion->getEntry();
2353   MachineBasicBlock *CodeExitBB = InnerRegion->getExit();
2354   MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeEntryBB, CodeExitBB,
2355                                           SelectBB, BBSelectRegIn, true);
2356   CurrentRegion->addMBB(IfBB);
2357   bool isEntry = CurrentRegion->getEntry() == InnerRegion->getEntry();
2358   if (isEntry) {
2359 
2360     if (CurrentRegion->getHasLoop()) {
2361       MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2362       MachineBasicBlock *ETrueBB = nullptr;
2363       MachineBasicBlock *EFalseBB = nullptr;
2364       SmallVector<MachineOperand, 1> ECond;
2365 
2366       const DebugLoc &DL = DebugLoc();
2367       TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2368       TII->removeBranch(*RegionExit);
2369 
2370       // We need to create a backedge if there is a loop
2371       Register Reg =
2372           TII->insertNE(RegionExit, RegionExit->instr_end(), DL,
2373                         CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2374                         CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2375       MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2376       ArrayRef<MachineOperand> Cond(RegOp);
2377       LLVM_DEBUG(dbgs() << "RegionExitReg: ");
2378       LLVM_DEBUG(Cond[0].print(dbgs(), TRI));
2379       LLVM_DEBUG(dbgs() << "\n");
2380       TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2381                         Cond, DebugLoc());
2382       RegionExit->addSuccessor(IfBB);
2383     }
2384   }
2385   CurrentRegion->addMBBs(InnerRegion);
2386   LLVM_DEBUG(dbgs() << "Insert BB Select PHI (region)\n");
2387   insertMergePHI(IfBB, CodeExitBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2388                  CodeBBSelectReg);
2389 
2390   rewriteLiveOutRegs(IfBB, /* CodeEntryBB */ CodeExitBB, MergeBB, InnerRegion,
2391                      CurrentRegion);
2392 
2393   rewriteRegionEntryPHIs(InnerRegion, IfBB);
2394 
2395   if (isEntry) {
2396     CurrentRegion->setEntry(IfBB);
2397   }
2398 
2399   if (isEntry) {
2400     createEntryPHIs(CurrentRegion);
2401   }
2402 
2403   return IfBB;
2404 }
2405 
2406 void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI,
2407                                           MachineBasicBlock *Entry,
2408                                           MachineBasicBlock *EntrySucc,
2409                                           LinearizedRegion *LRegion) {
2410   SmallVector<unsigned, 2> PHIRegionIndices;
2411   getPHIRegionIndices(LRegion, PHI, PHIRegionIndices);
2412 
2413   assert(PHIRegionIndices.size() == 1);
2414 
2415   unsigned RegionIndex = PHIRegionIndices[0];
2416   unsigned RegionSourceReg = getPHISourceReg(PHI, RegionIndex);
2417   MachineBasicBlock *RegionSourceMBB = getPHIPred(PHI, RegionIndex);
2418   unsigned PHIDest = getPHIDestReg(PHI);
2419   unsigned PHISource = PHIDest;
2420   unsigned ReplaceReg;
2421 
2422   if (shrinkPHI(PHI, PHIRegionIndices, &ReplaceReg)) {
2423     PHISource = ReplaceReg;
2424   }
2425 
2426   const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
2427   Register NewDestReg = MRI->createVirtualRegister(RegClass);
2428   LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI);
2429   MachineInstrBuilder MIB =
2430       BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(),
2431               TII->get(TargetOpcode::PHI), NewDestReg);
2432   LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
2433                     << " = PHI(");
2434   MIB.addReg(PHISource);
2435   MIB.addMBB(Entry);
2436   LLVM_DEBUG(dbgs() << printReg(PHISource, TRI) << ", "
2437                     << printMBBReference(*Entry));
2438   MIB.addReg(RegionSourceReg);
2439   MIB.addMBB(RegionSourceMBB);
2440   LLVM_DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", "
2441                     << printMBBReference(*RegionSourceMBB) << ")\n");
2442 }
2443 
2444 void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry,
2445                                            MachineBasicBlock *EntrySucc,
2446                                            LinearizedRegion *LRegion) {
2447   SmallVector<MachineInstr *, 2> PHIs;
2448   collectPHIs(Entry, PHIs);
2449 
2450   for (auto PHII : PHIs) {
2451     splitLoopPHI(*PHII, Entry, EntrySucc, LRegion);
2452   }
2453 }
2454 
2455 // Split the exit block so that we can insert a end control flow
2456 MachineBasicBlock *
2457 AMDGPUMachineCFGStructurizer::splitExit(LinearizedRegion *LRegion) {
2458   auto MRTRegion = LRegion->getRegionMRT();
2459   auto Exit = LRegion->getExit();
2460   auto MF = Exit->getParent();
2461   auto Succ = MRTRegion->getSucc();
2462 
2463   auto NewExit = MF->CreateMachineBasicBlock();
2464   auto AfterExitIter = Exit->getIterator();
2465   AfterExitIter++;
2466   MF->insert(AfterExitIter, NewExit);
2467   Exit->removeSuccessor(Succ);
2468   Exit->addSuccessor(NewExit);
2469   NewExit->addSuccessor(Succ);
2470   insertUnconditionalBranch(NewExit, Succ);
2471   LRegion->addMBB(NewExit);
2472   LRegion->setExit(NewExit);
2473 
2474   LLVM_DEBUG(dbgs() << "Created new exit block: " << NewExit->getNumber()
2475                     << "\n");
2476 
2477   // Replace any PHI Predecessors in the successor with NewExit
2478   for (auto &II : *Succ) {
2479     MachineInstr &Instr = II;
2480 
2481     // If we are past the PHI instructions we are done
2482     if (!Instr.isPHI())
2483       break;
2484 
2485     int numPreds = getPHINumInputs(Instr);
2486     for (int i = 0; i < numPreds; ++i) {
2487       auto Pred = getPHIPred(Instr, i);
2488       if (Pred == Exit) {
2489         setPhiPred(Instr, i, NewExit);
2490       }
2491     }
2492   }
2493 
2494   return NewExit;
2495 }
2496 
2497 static MachineBasicBlock *split(MachineBasicBlock::iterator I) {
2498   // Create the fall-through block.
2499   MachineBasicBlock *MBB = (*I).getParent();
2500   MachineFunction *MF = MBB->getParent();
2501   MachineBasicBlock *SuccMBB = MF->CreateMachineBasicBlock();
2502   auto MBBIter = ++(MBB->getIterator());
2503   MF->insert(MBBIter, SuccMBB);
2504   SuccMBB->transferSuccessorsAndUpdatePHIs(MBB);
2505   MBB->addSuccessor(SuccMBB);
2506 
2507   // Splice the code over.
2508   SuccMBB->splice(SuccMBB->end(), MBB, I, MBB->end());
2509 
2510   return SuccMBB;
2511 }
2512 
2513 // Split the entry block separating PHI-nodes and the rest of the code
2514 // This is needed to insert an initializer for the bb select register
2515 // inloop regions.
2516 
2517 MachineBasicBlock *
2518 AMDGPUMachineCFGStructurizer::splitEntry(LinearizedRegion *LRegion) {
2519   MachineBasicBlock *Entry = LRegion->getEntry();
2520   MachineBasicBlock *EntrySucc = split(Entry->getFirstNonPHI());
2521   MachineBasicBlock *Exit = LRegion->getExit();
2522 
2523   LLVM_DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to "
2524                     << printMBBReference(*Entry) << " -> "
2525                     << printMBBReference(*EntrySucc) << "\n");
2526   LRegion->addMBB(EntrySucc);
2527 
2528   // Make the backedge go to Entry Succ
2529   if (Exit->isSuccessor(Entry)) {
2530     Exit->removeSuccessor(Entry);
2531   }
2532   Exit->addSuccessor(EntrySucc);
2533   MachineInstr &Branch = *(Exit->instr_rbegin());
2534   for (auto &UI : Branch.uses()) {
2535     if (UI.isMBB() && UI.getMBB() == Entry) {
2536       UI.setMBB(EntrySucc);
2537     }
2538   }
2539 
2540   splitLoopPHIs(Entry, EntrySucc, LRegion);
2541 
2542   return EntrySucc;
2543 }
2544 
2545 LinearizedRegion *
2546 AMDGPUMachineCFGStructurizer::initLinearizedRegion(RegionMRT *Region) {
2547   LinearizedRegion *LRegion = Region->getLinearizedRegion();
2548   LRegion->initLiveOut(Region, MRI, TRI, PHIInfo);
2549   LRegion->setEntry(Region->getEntry());
2550   return LRegion;
2551 }
2552 
2553 static void removeOldExitPreds(RegionMRT *Region) {
2554   MachineBasicBlock *Exit = Region->getSucc();
2555   if (Exit == nullptr) {
2556     return;
2557   }
2558   for (MachineBasicBlock::pred_iterator PI = Exit->pred_begin(),
2559                                         E = Exit->pred_end();
2560        PI != E; ++PI) {
2561     if (Region->contains(*PI)) {
2562       (*PI)->removeSuccessor(Exit);
2563     }
2564   }
2565 }
2566 
2567 static bool mbbHasBackEdge(MachineBasicBlock *MBB,
2568                            SmallPtrSet<MachineBasicBlock *, 8> &MBBs) {
2569   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2570     if (MBBs.contains(*SI)) {
2571       return true;
2572     }
2573   }
2574   return false;
2575 }
2576 
2577 static bool containsNewBackedge(MRT *Tree,
2578                                 SmallPtrSet<MachineBasicBlock *, 8> &MBBs) {
2579   // Need to traverse this in reverse since it is in post order.
2580   if (Tree == nullptr)
2581     return false;
2582 
2583   if (Tree->isMBB()) {
2584     MachineBasicBlock *MBB = Tree->getMBBMRT()->getMBB();
2585     MBBs.insert(MBB);
2586     if (mbbHasBackEdge(MBB, MBBs)) {
2587       return true;
2588     }
2589   } else {
2590     RegionMRT *Region = Tree->getRegionMRT();
2591     SetVector<MRT *> *Children = Region->getChildren();
2592     for (auto CI = Children->rbegin(), CE = Children->rend(); CI != CE; ++CI) {
2593       if (containsNewBackedge(*CI, MBBs))
2594         return true;
2595     }
2596   }
2597   return false;
2598 }
2599 
2600 static bool containsNewBackedge(RegionMRT *Region) {
2601   SmallPtrSet<MachineBasicBlock *, 8> MBBs;
2602   return containsNewBackedge(Region, MBBs);
2603 }
2604 
2605 bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) {
2606   auto *LRegion = initLinearizedRegion(Region);
2607   LRegion->setHasLoop(containsNewBackedge(Region));
2608   MachineBasicBlock *LastMerge = createLinearizedExitBlock(Region);
2609   MachineBasicBlock *CurrentMerge = LastMerge;
2610   LRegion->addMBB(LastMerge);
2611   LRegion->setExit(LastMerge);
2612 
2613   rewriteRegionExitPHIs(Region, LastMerge, LRegion);
2614   removeOldExitPreds(Region);
2615 
2616   LLVM_DEBUG(PHIInfo.dump(MRI));
2617 
2618   SetVector<MRT *> *Children = Region->getChildren();
2619   LLVM_DEBUG(dbgs() << "===========If Region Start===============\n");
2620   if (LRegion->getHasLoop()) {
2621     LLVM_DEBUG(dbgs() << "Has Backedge: Yes\n");
2622   } else {
2623     LLVM_DEBUG(dbgs() << "Has Backedge: No\n");
2624   }
2625 
2626   unsigned BBSelectRegIn;
2627   unsigned BBSelectRegOut;
2628   for (auto CI = Children->begin(), CE = Children->end(); CI != CE; ++CI) {
2629     LLVM_DEBUG(dbgs() << "CurrentRegion: \n");
2630     LLVM_DEBUG(LRegion->print(dbgs(), TRI));
2631 
2632     auto CNI = CI;
2633     ++CNI;
2634 
2635     MRT *Child = (*CI);
2636 
2637     if (Child->isRegion()) {
2638 
2639       LinearizedRegion *InnerLRegion =
2640           Child->getRegionMRT()->getLinearizedRegion();
2641       // We found the block is the exit of an inner region, we need
2642       // to put it in the current linearized region.
2643 
2644       LLVM_DEBUG(dbgs() << "Linearizing region: ");
2645       LLVM_DEBUG(InnerLRegion->print(dbgs(), TRI));
2646       LLVM_DEBUG(dbgs() << "\n");
2647 
2648       MachineBasicBlock *InnerEntry = InnerLRegion->getEntry();
2649       if ((&(*(InnerEntry->getParent()->begin()))) == InnerEntry) {
2650         // Entry has already been linearized, no need to do this region.
2651         unsigned OuterSelect = InnerLRegion->getBBSelectRegOut();
2652         unsigned InnerSelectReg =
2653             InnerLRegion->getRegionMRT()->getInnerOutputRegister();
2654         replaceRegisterWith(InnerSelectReg, OuterSelect),
2655             resolvePHIInfos(InnerEntry);
2656         if (!InnerLRegion->getExit()->isSuccessor(CurrentMerge))
2657           InnerLRegion->getExit()->addSuccessor(CurrentMerge);
2658         continue;
2659       }
2660 
2661       BBSelectRegOut = Child->getBBSelectRegOut();
2662       BBSelectRegIn = Child->getBBSelectRegIn();
2663 
2664       LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2665                         << "\n");
2666       LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2667                         << "\n");
2668 
2669       MachineBasicBlock *IfEnd = CurrentMerge;
2670       CurrentMerge = createIfRegion(CurrentMerge, InnerLRegion, LRegion,
2671                                     Child->getRegionMRT()->getEntry(),
2672                                     BBSelectRegIn, BBSelectRegOut);
2673       TII->convertNonUniformIfRegion(CurrentMerge, IfEnd);
2674     } else {
2675       MachineBasicBlock *MBB = Child->getMBBMRT()->getMBB();
2676       LLVM_DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n");
2677 
2678       if (MBB == getSingleExitNode(*(MBB->getParent()))) {
2679         // If this is the exit block then we need to skip to the next.
2680         // The "in" register will be transferred to "out" in the next
2681         // iteration.
2682         continue;
2683       }
2684 
2685       BBSelectRegOut = Child->getBBSelectRegOut();
2686       BBSelectRegIn = Child->getBBSelectRegIn();
2687 
2688       LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2689                         << "\n");
2690       LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2691                         << "\n");
2692 
2693       MachineBasicBlock *IfEnd = CurrentMerge;
2694       // This is a basic block that is not part of an inner region, we
2695       // need to put it in the current linearized region.
2696       CurrentMerge = createIfRegion(CurrentMerge, MBB, LRegion, BBSelectRegIn,
2697                                     BBSelectRegOut);
2698       if (CurrentMerge) {
2699         TII->convertNonUniformIfRegion(CurrentMerge, IfEnd);
2700       }
2701 
2702       LLVM_DEBUG(PHIInfo.dump(MRI));
2703     }
2704   }
2705 
2706   LRegion->removeFalseRegisterKills(MRI);
2707 
2708   if (LRegion->getHasLoop()) {
2709     MachineBasicBlock *NewSucc = splitEntry(LRegion);
2710     if (isFunctionEntryBlock(LRegion->getEntry())) {
2711       resolvePHIInfos(LRegion->getEntry());
2712     }
2713     const DebugLoc &DL = NewSucc->findDebugLoc(NewSucc->getFirstNonPHI());
2714     unsigned InReg = LRegion->getBBSelectRegIn();
2715     Register InnerSelectReg =
2716         MRI->createVirtualRegister(MRI->getRegClass(InReg));
2717     Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
2718     TII->materializeImmediate(*(LRegion->getEntry()),
2719                               LRegion->getEntry()->getFirstTerminator(), DL,
2720                               NewInReg, Region->getEntry()->getNumber());
2721     // Need to be careful about updating the registers inside the region.
2722     LRegion->replaceRegisterInsideRegion(InReg, InnerSelectReg, false, MRI);
2723     LLVM_DEBUG(dbgs() << "Loop BBSelect Merge PHI:\n");
2724     insertMergePHI(LRegion->getEntry(), LRegion->getExit(), NewSucc,
2725                    InnerSelectReg, NewInReg,
2726                    LRegion->getRegionMRT()->getInnerOutputRegister());
2727     splitExit(LRegion);
2728     TII->convertNonUniformLoopRegion(NewSucc, LastMerge);
2729   }
2730 
2731   if (Region->isRoot()) {
2732     TII->insertReturn(*LastMerge);
2733   }
2734 
2735   LLVM_DEBUG(Region->getEntry()->getParent()->dump());
2736   LLVM_DEBUG(LRegion->print(dbgs(), TRI));
2737   LLVM_DEBUG(PHIInfo.dump(MRI));
2738 
2739   LLVM_DEBUG(dbgs() << "===========If Region End===============\n");
2740 
2741   Region->setLinearizedRegion(LRegion);
2742   return true;
2743 }
2744 
2745 bool AMDGPUMachineCFGStructurizer::structurizeRegion(RegionMRT *Region) {
2746   if (false && regionIsSimpleIf(Region)) {
2747     transformSimpleIfRegion(Region);
2748     return true;
2749   } else if (regionIsSequence(Region)) {
2750     fixupRegionExits(Region);
2751     return false;
2752   } else {
2753     structurizeComplexRegion(Region);
2754   }
2755   return false;
2756 }
2757 
2758 static int structurize_once = 0;
2759 
2760 bool AMDGPUMachineCFGStructurizer::structurizeRegions(RegionMRT *Region,
2761                                                 bool isTopRegion) {
2762   bool Changed = false;
2763 
2764   auto Children = Region->getChildren();
2765   for (auto CI : *Children) {
2766     if (CI->isRegion()) {
2767       Changed |= structurizeRegions(CI->getRegionMRT(), false);
2768     }
2769   }
2770 
2771   if (structurize_once < 2 || true) {
2772     Changed |= structurizeRegion(Region);
2773     structurize_once++;
2774   }
2775   return Changed;
2776 }
2777 
2778 void AMDGPUMachineCFGStructurizer::initFallthroughMap(MachineFunction &MF) {
2779   LLVM_DEBUG(dbgs() << "Fallthrough Map:\n");
2780   for (auto &MBBI : MF) {
2781     MachineBasicBlock *MBB = MBBI.getFallThrough();
2782     if (MBB != nullptr) {
2783       LLVM_DEBUG(dbgs() << "Fallthrough: " << MBBI.getNumber() << " -> "
2784                         << MBB->getNumber() << "\n");
2785     }
2786     FallthroughMap[&MBBI] = MBB;
2787   }
2788 }
2789 
2790 void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region,
2791                                                     unsigned SelectOut) {
2792   LinearizedRegion *LRegion = new LinearizedRegion();
2793   if (SelectOut) {
2794     LRegion->addLiveOut(SelectOut);
2795     LLVM_DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI)
2796                       << "\n");
2797   }
2798   LRegion->setRegionMRT(Region);
2799   Region->setLinearizedRegion(LRegion);
2800   LRegion->setParent(Region->getParent()
2801                          ? Region->getParent()->getLinearizedRegion()
2802                          : nullptr);
2803 }
2804 
2805 unsigned
2806 AMDGPUMachineCFGStructurizer::initializeSelectRegisters(MRT *MRT, unsigned SelectOut,
2807                                                   MachineRegisterInfo *MRI,
2808                                                   const SIInstrInfo *TII) {
2809   if (MRT->isRegion()) {
2810     RegionMRT *Region = MRT->getRegionMRT();
2811     Region->setBBSelectRegOut(SelectOut);
2812     unsigned InnerSelectOut = createBBSelectReg(TII, MRI);
2813 
2814     // Fixme: Move linearization creation to the original spot
2815     createLinearizedRegion(Region, SelectOut);
2816 
2817     for (auto CI = Region->getChildren()->begin(),
2818               CE = Region->getChildren()->end();
2819          CI != CE; ++CI) {
2820       InnerSelectOut =
2821           initializeSelectRegisters((*CI), InnerSelectOut, MRI, TII);
2822     }
2823     MRT->setBBSelectRegIn(InnerSelectOut);
2824     return InnerSelectOut;
2825   } else {
2826     MRT->setBBSelectRegOut(SelectOut);
2827     unsigned NewSelectIn = createBBSelectReg(TII, MRI);
2828     MRT->setBBSelectRegIn(NewSelectIn);
2829     return NewSelectIn;
2830   }
2831 }
2832 
2833 static void checkRegOnlyPHIInputs(MachineFunction &MF) {
2834   for (auto &MBBI : MF) {
2835     for (MachineBasicBlock::instr_iterator I = MBBI.instr_begin(),
2836                                            E = MBBI.instr_end();
2837          I != E; ++I) {
2838       MachineInstr &Instr = *I;
2839       if (Instr.isPHI()) {
2840         int numPreds = getPHINumInputs(Instr);
2841         for (int i = 0; i < numPreds; ++i) {
2842           assert(Instr.getOperand(i * 2 + 1).isReg() &&
2843                  "PHI Operand not a register");
2844         }
2845       }
2846     }
2847   }
2848 }
2849 
2850 bool AMDGPUMachineCFGStructurizer::runOnMachineFunction(MachineFunction &MF) {
2851   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2852   const SIInstrInfo *TII = ST.getInstrInfo();
2853   TRI = ST.getRegisterInfo();
2854   MRI = &(MF.getRegInfo());
2855   initFallthroughMap(MF);
2856 
2857   checkRegOnlyPHIInputs(MF);
2858   LLVM_DEBUG(dbgs() << "----STRUCTURIZER START----\n");
2859   LLVM_DEBUG(MF.dump());
2860 
2861   Regions = &(getAnalysis<MachineRegionInfoPass>().getRegionInfo());
2862   LLVM_DEBUG(Regions->dump());
2863 
2864   RegionMRT *RTree = MRT::buildMRT(MF, Regions, TII, MRI);
2865   setRegionMRT(RTree);
2866   initializeSelectRegisters(RTree, 0, MRI, TII);
2867   LLVM_DEBUG(RTree->dump(TRI));
2868   bool result = structurizeRegions(RTree, true);
2869   delete RTree;
2870   LLVM_DEBUG(dbgs() << "----STRUCTURIZER END----\n");
2871   initFallthroughMap(MF);
2872   return result;
2873 }
2874 
2875 char AMDGPUMachineCFGStructurizerID = AMDGPUMachineCFGStructurizer::ID;
2876 
2877 INITIALIZE_PASS_BEGIN(AMDGPUMachineCFGStructurizer, "amdgpu-machine-cfg-structurizer",
2878                       "AMDGPU Machine CFG Structurizer", false, false)
2879 INITIALIZE_PASS_DEPENDENCY(MachineRegionInfoPass)
2880 INITIALIZE_PASS_END(AMDGPUMachineCFGStructurizer, "amdgpu-machine-cfg-structurizer",
2881                     "AMDGPU Machine CFG Structurizer", false, false)
2882 
2883 FunctionPass *llvm::createAMDGPUMachineCFGStructurizerPass() {
2884   return new AMDGPUMachineCFGStructurizer();
2885 }
2886