1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "InstPrinter/AMDGPUInstPrinter.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCObjectStreamer.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/Format.h"
35 #include <algorithm>
36 
37 using namespace llvm;
38 
39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
40                                      const AsmPrinter &ap):
41   Ctx(ctx), ST(st), AP(ap) { }
42 
43 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
44   switch (MOFlags) {
45   default: return MCSymbolRefExpr::VK_None;
46   case SIInstrInfo::MO_GOTPCREL: return MCSymbolRefExpr::VK_GOTPCREL;
47   }
48 }
49 
50 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
51 
52   int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
53 
54   if (MCOpcode == -1) {
55     LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
56     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
57                 "a target-specific version: " + Twine(MI->getOpcode()));
58   }
59 
60   OutMI.setOpcode(MCOpcode);
61 
62   for (const MachineOperand &MO : MI->explicit_operands()) {
63     MCOperand MCOp;
64     switch (MO.getType()) {
65     default:
66       llvm_unreachable("unknown operand type");
67     case MachineOperand::MO_Immediate:
68       MCOp = MCOperand::createImm(MO.getImm());
69       break;
70     case MachineOperand::MO_Register:
71       MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
72       break;
73     case MachineOperand::MO_MachineBasicBlock:
74       MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
75                                    MO.getMBB()->getSymbol(), Ctx));
76       break;
77     case MachineOperand::MO_GlobalAddress: {
78       const GlobalValue *GV = MO.getGlobal();
79       SmallString<128> SymbolName;
80       AP.getNameWithPrefix(SymbolName, GV);
81       MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
82       const MCExpr *SymExpr =
83           MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
84       const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
85           MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
86       MCOp = MCOperand::createExpr(Expr);
87       break;
88     }
89     case MachineOperand::MO_ExternalSymbol: {
90       MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
91       Sym->setExternal(true);
92       const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
93       MCOp = MCOperand::createExpr(Expr);
94       break;
95     }
96     }
97     OutMI.addOperand(MCOp);
98   }
99 }
100 
101 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
102   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
103   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
104 
105   StringRef Err;
106   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
107     LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
108     C.emitError("Illegal instruction detected: " + Err);
109     MI->dump();
110   }
111 
112   if (MI->isBundle()) {
113     const MachineBasicBlock *MBB = MI->getParent();
114     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
115     while (I != MBB->instr_end() && I->isInsideBundle()) {
116       EmitInstruction(&*I);
117       ++I;
118     }
119   } else {
120     // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder
121     // terminator instructions and should only be printed as comments.
122     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
123       if (isVerbose()) {
124         SmallVector<char, 16> BBStr;
125         raw_svector_ostream Str(BBStr);
126 
127         const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
128         const MCSymbolRefExpr *Expr
129           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
130         Expr->print(Str, MAI);
131         OutStreamer->emitRawComment(" mask branch " + BBStr);
132       }
133 
134       return;
135     }
136 
137     if (MI->getOpcode() == AMDGPU::SI_RETURN) {
138       if (isVerbose())
139         OutStreamer->emitRawComment(" return");
140       return;
141     }
142 
143     MCInst TmpInst;
144     MCInstLowering.lower(MI, TmpInst);
145     EmitToStreamer(*OutStreamer, TmpInst);
146 
147     if (STI.dumpCode()) {
148       // Disassemble instruction/operands to text.
149       DisasmLines.resize(DisasmLines.size() + 1);
150       std::string &DisasmLine = DisasmLines.back();
151       raw_string_ostream DisasmStream(DisasmLine);
152 
153       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
154                                     *STI.getInstrInfo(),
155                                     *STI.getRegisterInfo());
156       InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
157 
158       // Disassemble instruction/operands to hex representation.
159       SmallVector<MCFixup, 4> Fixups;
160       SmallVector<char, 16> CodeBytes;
161       raw_svector_ostream CodeStream(CodeBytes);
162 
163       auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
164       MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
165       InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
166                                     MF->getSubtarget<MCSubtargetInfo>());
167       HexLines.resize(HexLines.size() + 1);
168       std::string &HexLine = HexLines.back();
169       raw_string_ostream HexStream(HexLine);
170 
171       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
172         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
173         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
174       }
175 
176       DisasmStream.flush();
177       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
178     }
179   }
180 }
181