1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "InstPrinter/AMDGPUInstPrinter.h"
21 #include "SIInstrInfo.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCObjectStreamer.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/Format.h"
35 #include <algorithm>
36 
37 using namespace llvm;
38 
39 #include "AMDGPUGenMCPseudoLowering.inc"
40 
41 
42 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
43                                      const AsmPrinter &ap):
44   Ctx(ctx), ST(st), AP(ap) { }
45 
46 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
47   switch (MOFlags) {
48   default:
49     return MCSymbolRefExpr::VK_None;
50   case SIInstrInfo::MO_GOTPCREL:
51     return MCSymbolRefExpr::VK_GOTPCREL;
52   case SIInstrInfo::MO_GOTPCREL32_LO:
53     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
54   case SIInstrInfo::MO_GOTPCREL32_HI:
55     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
56   case SIInstrInfo::MO_REL32_LO:
57     return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
58   case SIInstrInfo::MO_REL32_HI:
59     return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
60   }
61 }
62 
63 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
64   const MachineBasicBlock &SrcBB,
65   const MachineOperand &MO) const {
66   const MCExpr *DestBBSym
67     = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
68   const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
69 
70   assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
71          ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
72 
73   // s_getpc_b64 returns the address of next instruction.
74   const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
75   SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
76 
77   if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
78     return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
79 
80   assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
81   return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
82 }
83 
84 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
85                                      MCOperand &MCOp) const {
86   switch (MO.getType()) {
87   default:
88     llvm_unreachable("unknown operand type");
89   case MachineOperand::MO_Immediate:
90     MCOp = MCOperand::createImm(MO.getImm());
91     return true;
92   case MachineOperand::MO_Register:
93     MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
94     return true;
95   case MachineOperand::MO_MachineBasicBlock: {
96     if (MO.getTargetFlags() != 0) {
97       MCOp = MCOperand::createExpr(
98         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
99     } else {
100       MCOp = MCOperand::createExpr(
101         MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
102     }
103 
104     return true;
105   }
106   case MachineOperand::MO_GlobalAddress: {
107     const GlobalValue *GV = MO.getGlobal();
108     SmallString<128> SymbolName;
109     AP.getNameWithPrefix(SymbolName, GV);
110     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
111     const MCExpr *SymExpr =
112       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
113     const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
114       MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
115     MCOp = MCOperand::createExpr(Expr);
116     return true;
117   }
118   case MachineOperand::MO_ExternalSymbol: {
119     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
120     Sym->setExternal(true);
121     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
122     MCOp = MCOperand::createExpr(Expr);
123     return true;
124   }
125   }
126 }
127 
128 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
129   unsigned Opcode = MI->getOpcode();
130 
131   // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
132   // need to select it to the subtarget specific version, and there's no way to
133   // do that with a single pseudo source operation.
134   if (Opcode == AMDGPU::S_SETPC_B64_return)
135     Opcode = AMDGPU::S_SETPC_B64;
136 
137   int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(Opcode);
138   if (MCOpcode == -1) {
139     LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
140     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
141                 "a target-specific version: " + Twine(MI->getOpcode()));
142   }
143 
144   OutMI.setOpcode(MCOpcode);
145 
146   for (const MachineOperand &MO : MI->explicit_operands()) {
147     MCOperand MCOp;
148     lowerOperand(MO, MCOp);
149     OutMI.addOperand(MCOp);
150   }
151 }
152 
153 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
154                                     MCOperand &MCOp) const {
155   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
156   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
157   return MCInstLowering.lowerOperand(MO, MCOp);
158 }
159 
160 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
161   // TargetMachine does not support llvm-style cast. Use C++-style cast.
162   // This is safe since TM is always of type AMDGPUTargetMachine or its
163   // derived class.
164   auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
165   auto *CE = dyn_cast<ConstantExpr>(CV);
166 
167   // Lower null pointers in private and local address space.
168   // Clang generates addrspacecast for null pointers in private and local
169   // address space, which needs to be lowered.
170   if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
171     auto Op = CE->getOperand(0);
172     auto SrcAddr = Op->getType()->getPointerAddressSpace();
173     if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
174       auto DstAddr = CE->getType()->getPointerAddressSpace();
175       return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
176         OutContext);
177     }
178   }
179   return AsmPrinter::lowerConstant(CV);
180 }
181 
182 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
183   if (emitPseudoExpansionLowering(*OutStreamer, MI))
184     return;
185 
186   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
187   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
188 
189   StringRef Err;
190   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
191     LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
192     C.emitError("Illegal instruction detected: " + Err);
193     MI->print(errs());
194   }
195 
196   if (MI->isBundle()) {
197     const MachineBasicBlock *MBB = MI->getParent();
198     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
199     while (I != MBB->instr_end() && I->isInsideBundle()) {
200       EmitInstruction(&*I);
201       ++I;
202     }
203   } else {
204     // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
205     // placeholder terminator instructions and should only be printed as
206     // comments.
207     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
208       if (isVerbose()) {
209         SmallVector<char, 16> BBStr;
210         raw_svector_ostream Str(BBStr);
211 
212         const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
213         const MCSymbolRefExpr *Expr
214           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
215         Expr->print(Str, MAI);
216         OutStreamer->emitRawComment(" mask branch " + BBStr);
217       }
218 
219       return;
220     }
221 
222     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
223       if (isVerbose())
224         OutStreamer->emitRawComment(" return to shader part epilog");
225       return;
226     }
227 
228     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
229       if (isVerbose())
230         OutStreamer->emitRawComment(" wave barrier");
231       return;
232     }
233 
234     if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
235       if (isVerbose())
236         OutStreamer->emitRawComment(" divergent unreachable");
237       return;
238     }
239 
240     MCInst TmpInst;
241     MCInstLowering.lower(MI, TmpInst);
242     EmitToStreamer(*OutStreamer, TmpInst);
243 
244     if (STI.dumpCode()) {
245       // Disassemble instruction/operands to text.
246       DisasmLines.resize(DisasmLines.size() + 1);
247       std::string &DisasmLine = DisasmLines.back();
248       raw_string_ostream DisasmStream(DisasmLine);
249 
250       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
251                                     *STI.getInstrInfo(),
252                                     *STI.getRegisterInfo());
253       InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
254 
255       // Disassemble instruction/operands to hex representation.
256       SmallVector<MCFixup, 4> Fixups;
257       SmallVector<char, 16> CodeBytes;
258       raw_svector_ostream CodeStream(CodeBytes);
259 
260       auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
261       MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
262       InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
263                                     MF->getSubtarget<MCSubtargetInfo>());
264       HexLines.resize(HexLines.size() + 1);
265       std::string &HexLine = HexLines.back();
266       raw_string_ostream HexStream(HexLine);
267 
268       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
269         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
270         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
271       }
272 
273       DisasmStream.flush();
274       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
275     }
276   }
277 }
278