1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "InstPrinter/AMDGPUInstPrinter.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIInstrInfo.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/MC/MCCodeEmitter.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCObjectStreamer.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include <algorithm>
37 
38 using namespace llvm;
39 
40 #include "AMDGPUGenMCPseudoLowering.inc"
41 
42 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st,
43                                      const AsmPrinter &ap):
44   Ctx(ctx), ST(st), AP(ap) { }
45 
46 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
47   switch (MOFlags) {
48   default:
49     return MCSymbolRefExpr::VK_None;
50   case SIInstrInfo::MO_GOTPCREL:
51     return MCSymbolRefExpr::VK_GOTPCREL;
52   case SIInstrInfo::MO_GOTPCREL32_LO:
53     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
54   case SIInstrInfo::MO_GOTPCREL32_HI:
55     return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
56   case SIInstrInfo::MO_REL32_LO:
57     return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
58   case SIInstrInfo::MO_REL32_HI:
59     return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
60   }
61 }
62 
63 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
64   const MachineBasicBlock &SrcBB,
65   const MachineOperand &MO) const {
66   const MCExpr *DestBBSym
67     = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
68   const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
69 
70   assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
71          ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
72 
73   // s_getpc_b64 returns the address of next instruction.
74   const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
75   SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
76 
77   if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
78     return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
79 
80   assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
81   return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
82 }
83 
84 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
85                                      MCOperand &MCOp) const {
86   switch (MO.getType()) {
87   default:
88     llvm_unreachable("unknown operand type");
89   case MachineOperand::MO_Immediate:
90     MCOp = MCOperand::createImm(MO.getImm());
91     return true;
92   case MachineOperand::MO_Register:
93     MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
94     return true;
95   case MachineOperand::MO_MachineBasicBlock: {
96     if (MO.getTargetFlags() != 0) {
97       MCOp = MCOperand::createExpr(
98         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
99     } else {
100       MCOp = MCOperand::createExpr(
101         MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
102     }
103 
104     return true;
105   }
106   case MachineOperand::MO_GlobalAddress: {
107     const GlobalValue *GV = MO.getGlobal();
108     SmallString<128> SymbolName;
109     AP.getNameWithPrefix(SymbolName, GV);
110     MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
111     const MCExpr *SymExpr =
112       MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
113     const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
114       MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
115     MCOp = MCOperand::createExpr(Expr);
116     return true;
117   }
118   case MachineOperand::MO_ExternalSymbol: {
119     MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
120     Sym->setExternal(true);
121     const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
122     MCOp = MCOperand::createExpr(Expr);
123     return true;
124   }
125   case MachineOperand::MO_RegisterMask:
126     // Regmasks are like implicit defs.
127     return false;
128   }
129 }
130 
131 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
132   unsigned Opcode = MI->getOpcode();
133   const auto *TII = ST.getInstrInfo();
134 
135   // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
136   // need to select it to the subtarget specific version, and there's no way to
137   // do that with a single pseudo source operation.
138   if (Opcode == AMDGPU::S_SETPC_B64_return)
139     Opcode = AMDGPU::S_SETPC_B64;
140   else if (Opcode == AMDGPU::SI_CALL) {
141     // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
142     // called function (which we need to remove here).
143     OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
144     MCOperand Dest, Src;
145     lowerOperand(MI->getOperand(0), Dest);
146     lowerOperand(MI->getOperand(1), Src);
147     OutMI.addOperand(Dest);
148     OutMI.addOperand(Src);
149     return;
150   } else if (Opcode == AMDGPU::SI_TCRETURN) {
151     // TODO: How to use branch immediate and avoid register+add?
152     Opcode = AMDGPU::S_SETPC_B64;
153   }
154 
155   int MCOpcode = TII->pseudoToMCOpcode(Opcode);
156   if (MCOpcode == -1) {
157     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
158     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
159                 "a target-specific version: " + Twine(MI->getOpcode()));
160   }
161 
162   OutMI.setOpcode(MCOpcode);
163 
164   for (const MachineOperand &MO : MI->explicit_operands()) {
165     MCOperand MCOp;
166     lowerOperand(MO, MCOp);
167     OutMI.addOperand(MCOp);
168   }
169 }
170 
171 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
172                                     MCOperand &MCOp) const {
173   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
174   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
175   return MCInstLowering.lowerOperand(MO, MCOp);
176 }
177 
178 const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
179   // TargetMachine does not support llvm-style cast. Use C++-style cast.
180   // This is safe since TM is always of type AMDGPUTargetMachine or its
181   // derived class.
182   auto *AT = static_cast<AMDGPUTargetMachine*>(&TM);
183   auto *CE = dyn_cast<ConstantExpr>(CV);
184 
185   // Lower null pointers in private and local address space.
186   // Clang generates addrspacecast for null pointers in private and local
187   // address space, which needs to be lowered.
188   if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
189     auto Op = CE->getOperand(0);
190     auto SrcAddr = Op->getType()->getPointerAddressSpace();
191     if (Op->isNullValue() && AT->getNullPointerValue(SrcAddr) == 0) {
192       auto DstAddr = CE->getType()->getPointerAddressSpace();
193       return MCConstantExpr::create(AT->getNullPointerValue(DstAddr),
194         OutContext);
195     }
196   }
197   return AsmPrinter::lowerConstant(CV);
198 }
199 
200 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
201   if (emitPseudoExpansionLowering(*OutStreamer, MI))
202     return;
203 
204   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
205   AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
206 
207   StringRef Err;
208   if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
209     LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
210     C.emitError("Illegal instruction detected: " + Err);
211     MI->print(errs());
212   }
213 
214   if (MI->isBundle()) {
215     const MachineBasicBlock *MBB = MI->getParent();
216     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
217     while (I != MBB->instr_end() && I->isInsideBundle()) {
218       EmitInstruction(&*I);
219       ++I;
220     }
221   } else {
222     // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
223     // placeholder terminator instructions and should only be printed as
224     // comments.
225     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
226       if (isVerbose()) {
227         SmallVector<char, 16> BBStr;
228         raw_svector_ostream Str(BBStr);
229 
230         const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
231         const MCSymbolRefExpr *Expr
232           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
233         Expr->print(Str, MAI);
234         OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
235       }
236 
237       return;
238     }
239 
240     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
241       if (isVerbose())
242         OutStreamer->emitRawComment(" return to shader part epilog");
243       return;
244     }
245 
246     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
247       if (isVerbose())
248         OutStreamer->emitRawComment(" wave barrier");
249       return;
250     }
251 
252     if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
253       if (isVerbose())
254         OutStreamer->emitRawComment(" divergent unreachable");
255       return;
256     }
257 
258     MCInst TmpInst;
259     MCInstLowering.lower(MI, TmpInst);
260     EmitToStreamer(*OutStreamer, TmpInst);
261 
262     if (STI.dumpCode()) {
263       // Disassemble instruction/operands to text.
264       DisasmLines.resize(DisasmLines.size() + 1);
265       std::string &DisasmLine = DisasmLines.back();
266       raw_string_ostream DisasmStream(DisasmLine);
267 
268       AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
269                                     *STI.getInstrInfo(),
270                                     *STI.getRegisterInfo());
271       InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
272 
273       // Disassemble instruction/operands to hex representation.
274       SmallVector<MCFixup, 4> Fixups;
275       SmallVector<char, 16> CodeBytes;
276       raw_svector_ostream CodeStream(CodeBytes);
277 
278       auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
279       MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
280       InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
281                                     MF->getSubtarget<MCSubtargetInfo>());
282       HexLines.resize(HexLines.size() + 1);
283       std::string &HexLine = HexLines.back();
284       raw_string_ostream HexStream(HexLine);
285 
286       for (size_t i = 0; i < CodeBytes.size(); i += 4) {
287         unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
288         HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
289       }
290 
291       DisasmStream.flush();
292       DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
293     }
294   }
295 }
296