1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "AMDGPUArgumentUsageInfo.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32   const GCNSubtarget &ST;
33 
34 public:
35   AMDGPULegalizerInfo(const GCNSubtarget &ST,
36                       const GCNTargetMachine &TM);
37 
38   bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40   Register getSegmentAperture(unsigned AddrSpace,
41                               MachineRegisterInfo &MRI,
42                               MachineIRBuilder &B) const;
43 
44   bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45                              MachineIRBuilder &B) const;
46   bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47                      MachineIRBuilder &B) const;
48   bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49                      MachineIRBuilder &B) const;
50   bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
51                     MachineIRBuilder &B) const;
52   bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
53                               MachineIRBuilder &B) const;
54   bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
55                      MachineIRBuilder &B, bool Signed) const;
56   bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
57                      MachineIRBuilder &B, bool Signed) const;
58   bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
60                                 MachineIRBuilder &B) const;
61   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
62                                MachineIRBuilder &B) const;
63   bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
64                              MachineIRBuilder &B) const;
65 
66   bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
67                       MachineIRBuilder &B) const;
68 
69   bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
70                                const GlobalValue *GV, int64_t Offset,
71                                unsigned GAFlags = SIInstrInfo::MO_NONE) const;
72 
73   bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
74                            MachineIRBuilder &B) const;
75   bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
76 
77   bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
78                     MachineIRBuilder &B) const;
79 
80   bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
81                              MachineIRBuilder &B) const;
82   bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
83                     double Log2BaseInverted) const;
84   bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
85   bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
86   bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
87                       MachineIRBuilder &B) const;
88 
89   bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
90                            MachineIRBuilder &B) const;
91   bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI,
92                          MachineIRBuilder &B) const;
93 
94   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
95                       const ArgDescriptor *Arg,
96                       const TargetRegisterClass *ArgRC, LLT ArgTy) const;
97   bool loadInputValue(Register DstReg, MachineIRBuilder &B,
98                       AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
99 
100   bool legalizePreloadedArgIntrin(
101     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
102     AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
103   bool legalizeWorkitemIDIntrinsic(
104       MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
105       unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
106 
107   Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const;
108   bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B,
109                                    uint64_t Offset,
110                                    Align Alignment = Align(4)) const;
111 
112   bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
113                                MachineIRBuilder &B) const;
114 
115   void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg,
116                                      Register DstRemReg, Register Num,
117                                      Register Den) const;
118 
119   void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg,
120                                      Register DstRemReg, Register Num,
121                                      Register Den) const;
122 
123   bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
124                              MachineIRBuilder &B) const;
125 
126   bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
127                     MachineIRBuilder &B) const;
128   bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
129                       MachineIRBuilder &B) const;
130   bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
131                       MachineIRBuilder &B) const;
132   bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
133                       MachineIRBuilder &B) const;
134   bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
135                               MachineIRBuilder &B) const;
136   bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
137                                 MachineIRBuilder &B) const;
138   bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
139                               MachineIRBuilder &B) const;
140 
141   bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
142                                  MachineIRBuilder &B) const;
143 
144   bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
145                                    MachineInstr &MI, Intrinsic::ID IID) const;
146 
147   bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI,
148                          MachineIRBuilder &B) const;
149 
150   bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
151                               MachineIRBuilder &B) const;
152   bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
153                            MachineIRBuilder &B, unsigned AddrSpace) const;
154 
155   std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
156                                                    Register OrigOffset) const;
157   void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
158                        Register SOffset, unsigned ImmOffset, Register VIndex,
159                        MachineRegisterInfo &MRI) const;
160 
161   Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
162                           Register Reg, bool ImageStore = false) const;
163   bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
164                               MachineIRBuilder &B, bool IsFormat) const;
165   bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
166                              MachineIRBuilder &B, bool IsFormat) const;
167   Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
168                               bool IsFormat) const;
169 
170   bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
171                            MachineIRBuilder &B, bool IsTyped,
172                            bool IsFormat) const;
173   bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
174                           MachineIRBuilder &B, bool IsFormat,
175                           bool IsTyped) const;
176   bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
177                             Intrinsic::ID IID) const;
178 
179   bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const;
180 
181   bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const;
182 
183   bool legalizeImageIntrinsic(
184       MachineInstr &MI, MachineIRBuilder &B,
185       GISelChangeObserver &Observer,
186       const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
187 
188   bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
189 
190   bool legalizeAtomicIncDec(MachineInstr &MI,  MachineIRBuilder &B,
191                             bool IsInc) const;
192 
193   bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
194                              MachineIRBuilder &B) const;
195   bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI,
196                           MachineIRBuilder &B) const;
197   bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI,
198                                MachineIRBuilder &B) const;
199   bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
200                        MachineIRBuilder &B) const;
201   bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
202                                   MachineIRBuilder &B) const;
203 
204   bool legalizeIntrinsic(LegalizerHelper &Helper,
205                          MachineInstr &MI) const override;
206 };
207 } // End llvm namespace.
208 #endif
209