1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class LLVMContext; 25 class GCNSubtarget; 26 27 /// This class provides the information for the target register banks. 28 class AMDGPULegalizerInfo final : public LegalizerInfo { 29 const GCNSubtarget &ST; 30 31 public: 32 AMDGPULegalizerInfo(const GCNSubtarget &ST, 33 const GCNTargetMachine &TM); 34 35 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; 36 37 Register getSegmentAperture(unsigned AddrSpace, 38 MachineRegisterInfo &MRI, 39 MachineIRBuilder &B) const; 40 41 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 42 MachineIRBuilder &B) const; 43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 44 MachineIRBuilder &B) const; 45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 46 MachineIRBuilder &B) const; 47 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, 48 MachineIRBuilder &B) const; 49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 50 MachineIRBuilder &B) const; 51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 52 MachineIRBuilder &B, bool Signed) const; 53 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 54 MachineIRBuilder &B, bool Signed) const; 55 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const; 56 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 57 MachineIRBuilder &B) const; 58 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 59 MachineIRBuilder &B) const; 60 bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, 61 MachineIRBuilder &B) const; 62 63 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 64 MachineIRBuilder &B) const; 65 66 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, 67 const GlobalValue *GV, int64_t Offset, 68 unsigned GAFlags = SIInstrInfo::MO_NONE) const; 69 70 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 71 MachineIRBuilder &B) const; 72 bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 73 74 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 75 MachineIRBuilder &B) const; 76 77 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 78 MachineIRBuilder &B) const; 79 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 80 double Log2BaseInverted) const; 81 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 82 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 83 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 84 MachineIRBuilder &B) const; 85 86 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 87 MachineIRBuilder &B) const; 88 89 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 90 const ArgDescriptor *Arg, 91 const TargetRegisterClass *ArgRC, LLT ArgTy) const; 92 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 93 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 94 bool legalizePreloadedArgIntrin( 95 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 96 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 97 98 bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, 99 MachineIRBuilder &B) const; 100 101 void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, 102 Register DstReg, Register Num, Register Den, 103 bool IsRem) const; 104 bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 105 MachineIRBuilder &B) const; 106 bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 107 MachineIRBuilder &B) const; 108 109 void legalizeUDIV_UREM64Impl(MachineIRBuilder &B, 110 Register DstReg, Register Numer, Register Denom, 111 bool IsDiv) const; 112 113 bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, 114 MachineIRBuilder &B) const; 115 bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, 116 MachineIRBuilder &B) const; 117 118 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 119 MachineIRBuilder &B) const; 120 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 121 MachineIRBuilder &B) const; 122 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 123 MachineIRBuilder &B) const; 124 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 125 MachineIRBuilder &B) const; 126 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 127 MachineIRBuilder &B) const; 128 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 129 MachineIRBuilder &B) const; 130 131 bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 132 MachineIRBuilder &B) const; 133 134 bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, 135 MachineInstr &MI, Intrinsic::ID IID) const; 136 137 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, 138 MachineIRBuilder &B) const; 139 140 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 141 MachineIRBuilder &B) const; 142 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 143 MachineIRBuilder &B, unsigned AddrSpace) const; 144 145 std::tuple<Register, unsigned, unsigned> 146 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; 147 148 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 149 Register Reg, bool ImageStore = false) const; 150 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 151 MachineIRBuilder &B, bool IsFormat) const; 152 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 153 MachineIRBuilder &B, bool IsFormat) const; 154 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 155 bool IsFormat) const; 156 157 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 158 MachineIRBuilder &B, bool IsTyped, 159 bool IsFormat) const; 160 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 161 MachineIRBuilder &B, bool IsFormat, 162 bool IsTyped) const; 163 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 164 Intrinsic::ID IID) const; 165 166 bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const; 167 168 bool legalizeImageIntrinsic( 169 MachineInstr &MI, MachineIRBuilder &B, 170 GISelChangeObserver &Observer, 171 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 172 173 bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const; 174 175 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 176 bool IsInc) const; 177 178 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 179 MachineIRBuilder &B) const; 180 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 181 MachineIRBuilder &B) const; 182 183 bool legalizeIntrinsic(LegalizerHelper &Helper, 184 MachineInstr &MI) const override; 185 }; 186 } // End llvm namespace. 187 #endif 188