1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class LLVMContext; 25 class GCNSubtarget; 26 27 /// This class provides the information for the target register banks. 28 class AMDGPULegalizerInfo final : public LegalizerInfo { 29 const GCNSubtarget &ST; 30 31 public: 32 AMDGPULegalizerInfo(const GCNSubtarget &ST, 33 const GCNTargetMachine &TM); 34 35 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; 36 37 Register getSegmentAperture(unsigned AddrSpace, 38 MachineRegisterInfo &MRI, 39 MachineIRBuilder &B) const; 40 41 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 42 MachineIRBuilder &B) const; 43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 44 MachineIRBuilder &B) const; 45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 46 MachineIRBuilder &B) const; 47 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 48 MachineIRBuilder &B) const; 49 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 50 MachineIRBuilder &B, bool Signed) const; 51 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 52 MachineIRBuilder &B, bool Signed) const; 53 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const; 54 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 55 MachineIRBuilder &B) const; 56 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 57 MachineIRBuilder &B) const; 58 bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, 59 MachineIRBuilder &B) const; 60 61 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 62 MachineIRBuilder &B) const; 63 64 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, 65 const GlobalValue *GV, int64_t Offset, 66 unsigned GAFlags = SIInstrInfo::MO_NONE) const; 67 68 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 69 MachineIRBuilder &B) const; 70 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 71 MachineIRBuilder &B, 72 GISelChangeObserver &Observer) const; 73 74 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 75 MachineIRBuilder &B) const; 76 77 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 78 MachineIRBuilder &B) const; 79 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 80 double Log2BaseInverted) const; 81 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 82 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 83 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 84 MachineIRBuilder &B) const; 85 86 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 87 MachineIRBuilder &B) const; 88 89 Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI, 90 Register PhyReg, LLT Ty, 91 bool InsertLiveInCopy = true) const; 92 Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI, 93 Register LiveIn, Register PhyReg) const; 94 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 95 const ArgDescriptor *Arg, 96 const TargetRegisterClass *ArgRC, LLT ArgTy) const; 97 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 98 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 99 bool legalizePreloadedArgIntrin( 100 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 101 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 102 103 bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, 104 MachineIRBuilder &B) const; 105 106 void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, 107 Register DstReg, Register Num, Register Den, 108 bool IsRem) const; 109 bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 110 MachineIRBuilder &B) const; 111 bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 112 MachineIRBuilder &B) const; 113 114 void legalizeUDIV_UREM64Impl(MachineIRBuilder &B, 115 Register DstReg, Register Numer, Register Denom, 116 bool IsDiv) const; 117 118 bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, 119 MachineIRBuilder &B) const; 120 bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, 121 MachineIRBuilder &B) const; 122 123 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 124 MachineIRBuilder &B) const; 125 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 126 MachineIRBuilder &B) const; 127 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 128 MachineIRBuilder &B) const; 129 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 130 MachineIRBuilder &B) const; 131 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 132 MachineIRBuilder &B) const; 133 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 134 MachineIRBuilder &B) const; 135 136 bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, 137 MachineIRBuilder &B) const; 138 139 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 140 MachineIRBuilder &B) const; 141 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 142 MachineIRBuilder &B, unsigned AddrSpace) const; 143 144 std::tuple<Register, unsigned, unsigned> 145 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; 146 147 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 148 Register Reg) const; 149 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 150 MachineIRBuilder &B, bool IsFormat) const; 151 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 152 MachineIRBuilder &B, bool IsFormat) const; 153 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 154 bool IsFormat) const; 155 156 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 157 MachineIRBuilder &B, bool IsTyped, 158 bool IsFormat) const; 159 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 160 MachineIRBuilder &B, bool IsTyped, 161 bool IsFormat) const; 162 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 163 Intrinsic::ID IID) const; 164 165 bool legalizeImageIntrinsic( 166 MachineInstr &MI, MachineIRBuilder &B, 167 GISelChangeObserver &Observer, 168 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 169 170 bool legalizeSBufferLoad( 171 MachineInstr &MI, MachineIRBuilder &B, 172 GISelChangeObserver &Observer) const; 173 174 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 175 bool IsInc) const; 176 177 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 178 MachineIRBuilder &B) const; 179 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 180 MachineIRBuilder &B) const; 181 182 bool legalizeIntrinsic(LegalizerHelper &Helper, 183 MachineInstr &MI) const override; 184 }; 185 } // End llvm namespace. 186 #endif 187