1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the Machinelegalizer class for 10 /// AMDGPU. 11 /// \todo This should be generated by TableGen. 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H 16 17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class GCNTargetMachine; 24 class LLVMContext; 25 class GCNSubtarget; 26 27 /// This class provides the information for the target register banks. 28 class AMDGPULegalizerInfo : public LegalizerInfo { 29 const GCNSubtarget &ST; 30 31 public: 32 AMDGPULegalizerInfo(const GCNSubtarget &ST, 33 const GCNTargetMachine &TM); 34 35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, 36 MachineIRBuilder &B, 37 GISelChangeObserver &Observer) const override; 38 39 Register getSegmentAperture(unsigned AddrSpace, 40 MachineRegisterInfo &MRI, 41 MachineIRBuilder &B) const; 42 43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, 44 MachineIRBuilder &B) const; 45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, 46 MachineIRBuilder &B) const; 47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, 48 MachineIRBuilder &B) const; 49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, 50 MachineIRBuilder &B) const; 51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, 52 MachineIRBuilder &B, bool Signed) const; 53 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, 54 MachineIRBuilder &B, bool Signed) const; 55 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI, 56 MachineIRBuilder &B) const; 57 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 58 MachineIRBuilder &B) const; 59 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, 60 MachineIRBuilder &B) const; 61 bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, 62 MachineIRBuilder &B) const; 63 64 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, 65 MachineIRBuilder &B) const; 66 67 bool buildPCRelGlobalAddress( 68 Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, 69 unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const; 70 71 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, 72 MachineIRBuilder &B) const; 73 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 74 MachineIRBuilder &B, 75 GISelChangeObserver &Observer) const; 76 77 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, 78 MachineIRBuilder &B) const; 79 80 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, 81 MachineIRBuilder &B) const; 82 bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, 83 double Log2BaseInverted) const; 84 bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const; 85 bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const; 86 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, 87 MachineIRBuilder &B) const; 88 89 bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, 90 MachineIRBuilder &B) const; 91 92 Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI, 93 Register PhyReg, LLT Ty, 94 bool InsertLiveInCopy = true) const; 95 Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI, 96 Register LiveIn, Register PhyReg) const; 97 const ArgDescriptor * 98 getArgDescriptor(MachineIRBuilder &B, 99 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 100 bool loadInputValue(Register DstReg, MachineIRBuilder &B, 101 const ArgDescriptor *Arg) const; 102 bool legalizePreloadedArgIntrin( 103 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, 104 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const; 105 106 bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, 107 MachineIRBuilder &B) const; 108 109 void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, 110 Register DstReg, Register Num, Register Den, 111 bool IsRem) const; 112 bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 113 MachineIRBuilder &B) const; 114 115 bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI, 116 MachineIRBuilder &B) const; 117 bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, 118 MachineIRBuilder &B) const; 119 120 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 121 MachineIRBuilder &B) const; 122 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, 123 MachineIRBuilder &B) const; 124 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, 125 MachineIRBuilder &B) const; 126 bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, 127 MachineIRBuilder &B) const; 128 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, 129 MachineIRBuilder &B) const; 130 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, 131 MachineIRBuilder &B) const; 132 133 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, 134 MachineIRBuilder &B) const; 135 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, 136 MachineIRBuilder &B, unsigned AddrSpace) const; 137 138 std::tuple<Register, unsigned, unsigned> 139 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; 140 141 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 142 Register Reg) const; 143 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 144 MachineIRBuilder &B, bool IsFormat) const; 145 bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 146 MachineIRBuilder &B, bool IsFormat) const; 147 Register fixStoreSourceType(MachineIRBuilder &B, Register VData, 148 bool IsFormat) const; 149 150 bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, 151 MachineIRBuilder &B, bool IsTyped, 152 bool IsFormat) const; 153 bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, 154 MachineIRBuilder &B, bool IsTyped, 155 bool IsFormat) const; 156 bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, 157 Intrinsic::ID IID) const; 158 159 bool legalizeImageIntrinsic( 160 MachineInstr &MI, MachineIRBuilder &B, 161 GISelChangeObserver &Observer, 162 const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const; 163 164 bool legalizeSBufferLoad( 165 MachineInstr &MI, MachineIRBuilder &B, 166 GISelChangeObserver &Observer) const; 167 168 bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, 169 bool IsInc) const; 170 171 bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 172 MachineIRBuilder &B) const; 173 bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, 174 MachineIRBuilder &B) const; 175 176 bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &B, 177 GISelChangeObserver &Observer) const override; 178 }; 179 } // End llvm namespace. 180 #endif 181