1 //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPU.h"
16 #include "AMDGPULegalizerInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "llvm/CodeGen/TargetOpcodes.h"
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/IR/DerivedTypes.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 using namespace LegalizeActions;
26 
27 AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
28                                          const GCNTargetMachine &TM) {
29   using namespace TargetOpcode;
30 
31   auto GetAddrSpacePtr = [&TM](unsigned AS) {
32     return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
33   };
34 
35   const LLT S1 = LLT::scalar(1);
36   const LLT V2S16 = LLT::vector(2, 16);
37   const LLT V2S32 = LLT::vector(2, 32);
38 
39   const LLT S32 = LLT::scalar(32);
40   const LLT S64 = LLT::scalar(64);
41   const LLT S512 = LLT::scalar(512);
42 
43   const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
44   const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
45   const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
46   const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
47   const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
48 
49   const LLT CodePtr = FlatPtr;
50 
51   const LLT AddrSpaces[] = {
52     GlobalPtr,
53     ConstantPtr,
54     LocalPtr,
55     FlatPtr,
56     PrivatePtr
57   };
58 
59   setAction({G_ADD, S32}, Legal);
60   setAction({G_ASHR, S32}, Legal);
61   setAction({G_SUB, S32}, Legal);
62   setAction({G_MUL, S32}, Legal);
63 
64   // FIXME: 64-bit ones only legal for scalar
65   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
66     .legalFor({S32, S1, S64, V2S32});
67 
68   setAction({G_BITCAST, V2S16}, Legal);
69   setAction({G_BITCAST, 1, S32}, Legal);
70 
71   setAction({G_BITCAST, S32}, Legal);
72   setAction({G_BITCAST, 1, V2S16}, Legal);
73 
74   getActionDefinitionsBuilder(G_FCONSTANT)
75     .legalFor({S32, S64});
76 
77   // G_IMPLICIT_DEF is a no-op so we can make it legal for any value type that
78   // can fit in a register.
79   // FIXME: We need to legalize several more operations before we can add
80   // a test case for size > 512.
81   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
82     .legalIf([=](const LegalityQuery &Query) {
83         return Query.Types[0].getSizeInBits() <= 512;
84     })
85     .clampScalar(0, S1, S512);
86 
87   getActionDefinitionsBuilder(G_CONSTANT)
88     .legalFor({S1, S32, S64});
89 
90   // FIXME: i1 operands to intrinsics should always be legal, but other i1
91   // values may not be legal.  We need to figure out how to distinguish
92   // between these two scenarios.
93   setAction({G_CONSTANT, S1}, Legal);
94 
95   setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
96 
97   getActionDefinitionsBuilder(
98     { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
99     .legalFor({S32, S64});
100 
101   getActionDefinitionsBuilder(G_FPTRUNC)
102     .legalFor({{S32, S64}});
103 
104   // Use actual fsub instruction
105   setAction({G_FSUB, S32}, Legal);
106 
107   // Must use fadd + fneg
108   setAction({G_FSUB, S64}, Lower);
109 
110   setAction({G_FCMP, S1}, Legal);
111   setAction({G_FCMP, 1, S32}, Legal);
112   setAction({G_FCMP, 1, S64}, Legal);
113 
114   setAction({G_ZEXT, S64}, Legal);
115   setAction({G_ZEXT, 1, S32}, Legal);
116 
117   setAction({G_SEXT, S64}, Legal);
118   setAction({G_SEXT, 1, S32}, Legal);
119 
120   setAction({G_ANYEXT, S64}, Legal);
121   setAction({G_ANYEXT, 1, S32}, Legal);
122 
123   setAction({G_FPTOSI, S32}, Legal);
124   setAction({G_FPTOSI, 1, S32}, Legal);
125 
126   setAction({G_SITOFP, S32}, Legal);
127   setAction({G_SITOFP, 1, S32}, Legal);
128 
129   setAction({G_UITOFP, S32}, Legal);
130   setAction({G_UITOFP, 1, S32}, Legal);
131 
132   setAction({G_FPTOUI, S32}, Legal);
133   setAction({G_FPTOUI, 1, S32}, Legal);
134 
135   for (LLT PtrTy : AddrSpaces) {
136     LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
137     setAction({G_GEP, PtrTy}, Legal);
138     setAction({G_GEP, 1, IdxTy}, Legal);
139   }
140 
141   setAction({G_BLOCK_ADDR, CodePtr}, Legal);
142 
143   setAction({G_ICMP, S1}, Legal);
144   setAction({G_ICMP, 1, S32}, Legal);
145 
146   setAction({G_CTLZ, S32}, Legal);
147   setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);
148   setAction({G_CTTZ, S32}, Legal);
149   setAction({G_CTTZ_ZERO_UNDEF, S32}, Legal);
150   setAction({G_BSWAP, S32}, Legal);
151   setAction({G_CTPOP, S32}, Legal);
152 
153   getActionDefinitionsBuilder(G_INTTOPTR)
154     .legalIf([](const LegalityQuery &Query) {
155       return true;
156     });
157 
158   getActionDefinitionsBuilder(G_PTRTOINT)
159     .legalIf([](const LegalityQuery &Query) {
160       return true;
161     });
162 
163   getActionDefinitionsBuilder({G_LOAD, G_STORE})
164     .legalIf([=, &ST](const LegalityQuery &Query) {
165         const LLT &Ty0 = Query.Types[0];
166 
167         // TODO: Decompose private loads into 4-byte components.
168         // TODO: Illegal flat loads on SI
169         switch (Ty0.getSizeInBits()) {
170         case 32:
171         case 64:
172         case 128:
173           return true;
174 
175         case 96:
176           // XXX hasLoadX3
177           return (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
178 
179         case 256:
180         case 512:
181           // TODO: constant loads
182         default:
183           return false;
184         }
185       });
186 
187 
188   auto &Atomics = getActionDefinitionsBuilder(
189     {G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB,
190      G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR,
191      G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
192      G_ATOMICRMW_UMIN, G_ATOMIC_CMPXCHG})
193     .legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
194                {S64, GlobalPtr}, {S64, LocalPtr}});
195   if (ST.hasFlatAddressSpace()) {
196     Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
197   }
198 
199   setAction({G_SELECT, S32}, Legal);
200   setAction({G_SELECT, 1, S1}, Legal);
201 
202   setAction({G_SHL, S32}, Legal);
203 
204 
205   // FIXME: When RegBankSelect inserts copies, it will only create new
206   // registers with scalar types.  This means we can end up with
207   // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
208   // operands.  In assert builds, the instruction selector will assert
209   // if it sees a generic instruction which isn't legal, so we need to
210   // tell it that scalar types are legal for pointer operands
211   setAction({G_GEP, S64}, Legal);
212 
213   for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
214     getActionDefinitionsBuilder(Op)
215       .legalIf([=](const LegalityQuery &Query) {
216           const LLT &VecTy = Query.Types[1];
217           const LLT &IdxTy = Query.Types[2];
218           return VecTy.getSizeInBits() % 32 == 0 &&
219             VecTy.getSizeInBits() <= 512 &&
220             IdxTy.getSizeInBits() == 32;
221         });
222   }
223 
224   // FIXME: Doesn't handle extract of illegal sizes.
225   getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
226     .legalIf([=](const LegalityQuery &Query) {
227         const LLT &Ty0 = Query.Types[0];
228         const LLT &Ty1 = Query.Types[1];
229         return (Ty0.getSizeInBits() % 32 == 0) &&
230                (Ty1.getSizeInBits() % 32 == 0);
231       });
232 
233   getActionDefinitionsBuilder(G_BUILD_VECTOR)
234       .legalIf([=](const LegalityQuery &Query) {
235         const LLT &VecTy = Query.Types[0];
236         const LLT &ScalarTy = Query.Types[1];
237         return VecTy.getSizeInBits() % 32 == 0 &&
238                ScalarTy.getSizeInBits() % 32 == 0 &&
239                VecTy.getSizeInBits() <= 512;
240       });
241   // Merge/Unmerge
242   for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
243     unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
244     unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
245 
246     getActionDefinitionsBuilder(Op)
247       .legalIf([=](const LegalityQuery &Query) {
248           const LLT &BigTy = Query.Types[BigTyIdx];
249           const LLT &LitTy = Query.Types[LitTyIdx];
250           return BigTy.getSizeInBits() % 32 == 0 &&
251                  LitTy.getSizeInBits() % 32 == 0 &&
252                  BigTy.getSizeInBits() <= 512;
253         })
254       // Any vectors left are the wrong size. Scalarize them.
255       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
256                        [](const LegalityQuery &Query) {
257                          return std::make_pair(
258                            0, Query.Types[0].getElementType());
259                        })
260       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
261                        [](const LegalityQuery &Query) {
262                          return std::make_pair(
263                            1, Query.Types[1].getElementType());
264                        });
265 
266   }
267 
268   computeTables();
269   verify(*ST.getInstrInfo());
270 }
271