1 //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the Machinelegalizer class for 11 /// AMDGPU. 12 /// \todo This should be generated by TableGen. 13 //===----------------------------------------------------------------------===// 14 15 #include "AMDGPU.h" 16 #include "AMDGPULegalizerInfo.h" 17 #include "llvm/CodeGen/TargetOpcodes.h" 18 #include "llvm/CodeGen/ValueTypes.h" 19 #include "llvm/IR/DerivedTypes.h" 20 #include "llvm/IR/Type.h" 21 #include "llvm/Support/Debug.h" 22 23 using namespace llvm; 24 using namespace LegalizeActions; 25 26 AMDGPULegalizerInfo::AMDGPULegalizerInfo() { 27 using namespace TargetOpcode; 28 29 const LLT S1= LLT::scalar(1); 30 const LLT V2S16 = LLT::vector(2, 16); 31 const LLT S32 = LLT::scalar(32); 32 const LLT S64 = LLT::scalar(64); 33 const LLT P1 = LLT::pointer(AMDGPUAS::GLOBAL_ADDRESS, 64); 34 const LLT P2 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64); 35 36 setAction({G_ADD, S32}, Legal); 37 setAction({G_AND, S32}, Legal); 38 39 setAction({G_BITCAST, V2S16}, Legal); 40 setAction({G_BITCAST, 1, S32}, Legal); 41 42 setAction({G_BITCAST, S32}, Legal); 43 setAction({G_BITCAST, 1, V2S16}, Legal); 44 45 // FIXME: i1 operands to intrinsics should always be legal, but other i1 46 // values may not be legal. We need to figure out how to distinguish 47 // between these two scenarios. 48 setAction({G_CONSTANT, S1}, Legal); 49 setAction({G_CONSTANT, S32}, Legal); 50 setAction({G_CONSTANT, S64}, Legal); 51 52 setAction({G_FCONSTANT, S32}, Legal); 53 54 setAction({G_FADD, S32}, Legal); 55 56 setAction({G_FMUL, S32}, Legal); 57 58 setAction({G_FPTOUI, S32}, Legal); 59 setAction({G_FPTOUI, 1, S32}, Legal); 60 61 setAction({G_GEP, P1}, Legal); 62 setAction({G_GEP, P2}, Legal); 63 setAction({G_GEP, 1, S64}, Legal); 64 65 setAction({G_ICMP, S1}, Legal); 66 setAction({G_ICMP, 1, S32}, Legal); 67 68 setAction({G_LOAD, P1}, Legal); 69 setAction({G_LOAD, P2}, Legal); 70 setAction({G_LOAD, S32}, Legal); 71 setAction({G_LOAD, 1, P1}, Legal); 72 setAction({G_LOAD, 1, P2}, Legal); 73 74 setAction({G_OR, S32}, Legal); 75 76 setAction({G_SELECT, S32}, Legal); 77 setAction({G_SELECT, 1, S1}, Legal); 78 79 setAction({G_SHL, S32}, Legal); 80 81 setAction({G_STORE, S32}, Legal); 82 setAction({G_STORE, 1, P1}, Legal); 83 84 // FIXME: When RegBankSelect inserts copies, it will only create new 85 // registers with scalar types. This means we can end up with 86 // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer 87 // operands. In assert builds, the instruction selector will assert 88 // if it sees a generic instruction which isn't legal, so we need to 89 // tell it that scalar types are legal for pointer operands 90 setAction({G_GEP, S64}, Legal); 91 setAction({G_LOAD, 1, S64}, Legal); 92 setAction({G_STORE, 1, S64}, Legal); 93 94 computeTables(); 95 } 96