1 //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the Machinelegalizer class for
11 /// AMDGPU.
12 /// \todo This should be generated by TableGen.
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPU.h"
16 #include "AMDGPULegalizerInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "llvm/CodeGen/TargetOpcodes.h"
19 #include "llvm/CodeGen/ValueTypes.h"
20 #include "llvm/IR/DerivedTypes.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 using namespace LegalizeActions;
26 
27 AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
28                                          const GCNTargetMachine &TM) {
29   using namespace TargetOpcode;
30 
31   auto GetAddrSpacePtr = [&TM](unsigned AS) {
32     return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
33   };
34 
35   const LLT S1 = LLT::scalar(1);
36   const LLT S32 = LLT::scalar(32);
37   const LLT S64 = LLT::scalar(64);
38   const LLT S512 = LLT::scalar(512);
39 
40   const LLT V2S16 = LLT::vector(2, 16);
41 
42   const LLT V2S32 = LLT::vector(2, 32);
43   const LLT V3S32 = LLT::vector(3, 32);
44   const LLT V4S32 = LLT::vector(4, 32);
45   const LLT V5S32 = LLT::vector(5, 32);
46   const LLT V6S32 = LLT::vector(6, 32);
47   const LLT V7S32 = LLT::vector(7, 32);
48   const LLT V8S32 = LLT::vector(8, 32);
49   const LLT V9S32 = LLT::vector(9, 32);
50   const LLT V10S32 = LLT::vector(10, 32);
51   const LLT V11S32 = LLT::vector(11, 32);
52   const LLT V12S32 = LLT::vector(12, 32);
53   const LLT V13S32 = LLT::vector(13, 32);
54   const LLT V14S32 = LLT::vector(14, 32);
55   const LLT V15S32 = LLT::vector(15, 32);
56   const LLT V16S32 = LLT::vector(16, 32);
57 
58   const LLT V2S64 = LLT::vector(2, 64);
59   const LLT V3S64 = LLT::vector(3, 64);
60   const LLT V4S64 = LLT::vector(4, 64);
61   const LLT V5S64 = LLT::vector(5, 64);
62   const LLT V6S64 = LLT::vector(6, 64);
63   const LLT V7S64 = LLT::vector(7, 64);
64   const LLT V8S64 = LLT::vector(8, 64);
65 
66   std::initializer_list<LLT> AllS32Vectors =
67     {V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
68      V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32};
69   std::initializer_list<LLT> AllS64Vectors =
70     {V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64};
71 
72   const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
73   const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
74   const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
75   const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
76   const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
77 
78   const LLT CodePtr = FlatPtr;
79 
80   const LLT AddrSpaces[] = {
81     GlobalPtr,
82     ConstantPtr,
83     LocalPtr,
84     FlatPtr,
85     PrivatePtr
86   };
87 
88   setAction({G_ADD, S32}, Legal);
89   setAction({G_ASHR, S32}, Legal);
90   setAction({G_SUB, S32}, Legal);
91   setAction({G_MUL, S32}, Legal);
92 
93   // FIXME: 64-bit ones only legal for scalar
94   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
95     .legalFor({S32, S1, S64, V2S32});
96 
97   setAction({G_BITCAST, V2S16}, Legal);
98   setAction({G_BITCAST, 1, S32}, Legal);
99 
100   setAction({G_BITCAST, S32}, Legal);
101   setAction({G_BITCAST, 1, V2S16}, Legal);
102 
103   getActionDefinitionsBuilder(G_FCONSTANT)
104     .legalFor({S32, S64});
105 
106   // G_IMPLICIT_DEF is a no-op so we can make it legal for any value type that
107   // can fit in a register.
108   // FIXME: We need to legalize several more operations before we can add
109   // a test case for size > 512.
110   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
111     .legalIf([=](const LegalityQuery &Query) {
112         return Query.Types[0].getSizeInBits() <= 512;
113     })
114     .clampScalar(0, S1, S512);
115 
116   getActionDefinitionsBuilder(G_CONSTANT)
117     .legalFor({S1, S32, S64});
118 
119   // FIXME: i1 operands to intrinsics should always be legal, but other i1
120   // values may not be legal.  We need to figure out how to distinguish
121   // between these two scenarios.
122   setAction({G_CONSTANT, S1}, Legal);
123 
124   setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
125 
126   getActionDefinitionsBuilder(
127     { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
128     .legalFor({S32, S64});
129 
130   getActionDefinitionsBuilder(G_FPTRUNC)
131     .legalFor({{S32, S64}});
132 
133   // Use actual fsub instruction
134   setAction({G_FSUB, S32}, Legal);
135 
136   // Must use fadd + fneg
137   setAction({G_FSUB, S64}, Lower);
138 
139   setAction({G_FCMP, S1}, Legal);
140   setAction({G_FCMP, 1, S32}, Legal);
141   setAction({G_FCMP, 1, S64}, Legal);
142 
143   setAction({G_ZEXT, S64}, Legal);
144   setAction({G_ZEXT, 1, S32}, Legal);
145 
146   setAction({G_SEXT, S64}, Legal);
147   setAction({G_SEXT, 1, S32}, Legal);
148 
149   setAction({G_ANYEXT, S64}, Legal);
150   setAction({G_ANYEXT, 1, S32}, Legal);
151 
152   setAction({G_FPTOSI, S32}, Legal);
153   setAction({G_FPTOSI, 1, S32}, Legal);
154 
155   setAction({G_SITOFP, S32}, Legal);
156   setAction({G_SITOFP, 1, S32}, Legal);
157 
158   setAction({G_UITOFP, S32}, Legal);
159   setAction({G_UITOFP, 1, S32}, Legal);
160 
161   setAction({G_FPTOUI, S32}, Legal);
162   setAction({G_FPTOUI, 1, S32}, Legal);
163 
164   setAction({G_FPOW, S32}, Legal);
165   setAction({G_FEXP2, S32}, Legal);
166   setAction({G_FLOG2, S32}, Legal);
167 
168   getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
169     .legalFor({S32, S64});
170 
171   for (LLT PtrTy : AddrSpaces) {
172     LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
173     setAction({G_GEP, PtrTy}, Legal);
174     setAction({G_GEP, 1, IdxTy}, Legal);
175   }
176 
177   setAction({G_BLOCK_ADDR, CodePtr}, Legal);
178 
179   setAction({G_ICMP, S1}, Legal);
180   setAction({G_ICMP, 1, S32}, Legal);
181 
182   setAction({G_CTLZ, S32}, Legal);
183   setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);
184   setAction({G_CTTZ, S32}, Legal);
185   setAction({G_CTTZ_ZERO_UNDEF, S32}, Legal);
186   setAction({G_BSWAP, S32}, Legal);
187   setAction({G_CTPOP, S32}, Legal);
188 
189   getActionDefinitionsBuilder(G_INTTOPTR)
190     .legalIf([](const LegalityQuery &Query) {
191       return true;
192     });
193 
194   getActionDefinitionsBuilder(G_PTRTOINT)
195     .legalIf([](const LegalityQuery &Query) {
196       return true;
197     });
198 
199   getActionDefinitionsBuilder({G_LOAD, G_STORE})
200     .legalIf([=, &ST](const LegalityQuery &Query) {
201         const LLT &Ty0 = Query.Types[0];
202 
203         // TODO: Decompose private loads into 4-byte components.
204         // TODO: Illegal flat loads on SI
205         switch (Ty0.getSizeInBits()) {
206         case 32:
207         case 64:
208         case 128:
209           return true;
210 
211         case 96:
212           // XXX hasLoadX3
213           return (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
214 
215         case 256:
216         case 512:
217           // TODO: constant loads
218         default:
219           return false;
220         }
221       });
222 
223 
224   auto &Atomics = getActionDefinitionsBuilder(
225     {G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB,
226      G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR,
227      G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
228      G_ATOMICRMW_UMIN, G_ATOMIC_CMPXCHG})
229     .legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
230                {S64, GlobalPtr}, {S64, LocalPtr}});
231   if (ST.hasFlatAddressSpace()) {
232     Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
233   }
234 
235   setAction({G_SELECT, S32}, Legal);
236   setAction({G_SELECT, 1, S1}, Legal);
237 
238   setAction({G_SHL, S32}, Legal);
239 
240 
241   // FIXME: When RegBankSelect inserts copies, it will only create new
242   // registers with scalar types.  This means we can end up with
243   // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
244   // operands.  In assert builds, the instruction selector will assert
245   // if it sees a generic instruction which isn't legal, so we need to
246   // tell it that scalar types are legal for pointer operands
247   setAction({G_GEP, S64}, Legal);
248 
249   for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
250     getActionDefinitionsBuilder(Op)
251       .legalIf([=](const LegalityQuery &Query) {
252           const LLT &VecTy = Query.Types[1];
253           const LLT &IdxTy = Query.Types[2];
254           return VecTy.getSizeInBits() % 32 == 0 &&
255             VecTy.getSizeInBits() <= 512 &&
256             IdxTy.getSizeInBits() == 32;
257         });
258   }
259 
260   // FIXME: Doesn't handle extract of illegal sizes.
261   getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
262     .legalIf([=](const LegalityQuery &Query) {
263         const LLT &Ty0 = Query.Types[0];
264         const LLT &Ty1 = Query.Types[1];
265         return (Ty0.getSizeInBits() % 32 == 0) &&
266                (Ty1.getSizeInBits() % 32 == 0);
267       });
268 
269   getActionDefinitionsBuilder(G_BUILD_VECTOR)
270     .legalForCartesianProduct(AllS32Vectors, {S32})
271     .legalForCartesianProduct(AllS64Vectors, {S64})
272     .clampNumElements(0, V16S32, V16S32)
273     .clampNumElements(0, V2S64, V8S64)
274     .minScalarSameAs(1, 0);
275 
276   // Merge/Unmerge
277   for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
278     unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
279     unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
280 
281     getActionDefinitionsBuilder(Op)
282       .legalIf([=](const LegalityQuery &Query) {
283           const LLT &BigTy = Query.Types[BigTyIdx];
284           const LLT &LitTy = Query.Types[LitTyIdx];
285           return BigTy.getSizeInBits() % 32 == 0 &&
286                  LitTy.getSizeInBits() % 32 == 0 &&
287                  BigTy.getSizeInBits() <= 512;
288         })
289       // Any vectors left are the wrong size. Scalarize them.
290       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
291                        [](const LegalityQuery &Query) {
292                          return std::make_pair(
293                            0, Query.Types[0].getElementType());
294                        })
295       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
296                        [](const LegalityQuery &Query) {
297                          return std::make_pair(
298                            1, Query.Types[1].getElementType());
299                        });
300 
301   }
302 
303   computeTables();
304   verify(*ST.getInstrInfo());
305 }
306