1 //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPU.h"
15 #include "AMDGPULegalizerInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/IR/DerivedTypes.h"
20 #include "llvm/IR/Type.h"
21 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 using namespace LegalizeActions;
25 
26 AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
27                                          const GCNTargetMachine &TM) {
28   using namespace TargetOpcode;
29 
30   auto GetAddrSpacePtr = [&TM](unsigned AS) {
31     return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
32   };
33 
34   const LLT S1 = LLT::scalar(1);
35   const LLT S16 = LLT::scalar(16);
36   const LLT S32 = LLT::scalar(32);
37   const LLT S64 = LLT::scalar(64);
38   const LLT S512 = LLT::scalar(512);
39 
40   const LLT V2S16 = LLT::vector(2, 16);
41   const LLT V4S16 = LLT::vector(4, 16);
42   const LLT V8S16 = LLT::vector(8, 16);
43 
44   const LLT V2S32 = LLT::vector(2, 32);
45   const LLT V3S32 = LLT::vector(3, 32);
46   const LLT V4S32 = LLT::vector(4, 32);
47   const LLT V5S32 = LLT::vector(5, 32);
48   const LLT V6S32 = LLT::vector(6, 32);
49   const LLT V7S32 = LLT::vector(7, 32);
50   const LLT V8S32 = LLT::vector(8, 32);
51   const LLT V9S32 = LLT::vector(9, 32);
52   const LLT V10S32 = LLT::vector(10, 32);
53   const LLT V11S32 = LLT::vector(11, 32);
54   const LLT V12S32 = LLT::vector(12, 32);
55   const LLT V13S32 = LLT::vector(13, 32);
56   const LLT V14S32 = LLT::vector(14, 32);
57   const LLT V15S32 = LLT::vector(15, 32);
58   const LLT V16S32 = LLT::vector(16, 32);
59 
60   const LLT V2S64 = LLT::vector(2, 64);
61   const LLT V3S64 = LLT::vector(3, 64);
62   const LLT V4S64 = LLT::vector(4, 64);
63   const LLT V5S64 = LLT::vector(5, 64);
64   const LLT V6S64 = LLT::vector(6, 64);
65   const LLT V7S64 = LLT::vector(7, 64);
66   const LLT V8S64 = LLT::vector(8, 64);
67 
68   std::initializer_list<LLT> AllS32Vectors =
69     {V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
70      V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32};
71   std::initializer_list<LLT> AllS64Vectors =
72     {V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64};
73 
74   const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
75   const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
76   const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
77   const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
78   const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
79 
80   const LLT CodePtr = FlatPtr;
81 
82   const LLT AddrSpaces[] = {
83     GlobalPtr,
84     ConstantPtr,
85     LocalPtr,
86     FlatPtr,
87     PrivatePtr
88   };
89 
90   setAction({G_BRCOND, S1}, Legal);
91 
92   setAction({G_ADD, S32}, Legal);
93   setAction({G_ASHR, S32}, Legal);
94   setAction({G_SUB, S32}, Legal);
95   setAction({G_MUL, S32}, Legal);
96 
97   // FIXME: 64-bit ones only legal for scalar
98   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
99     .legalFor({S32, S1, S64, V2S32});
100 
101   getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
102                                G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
103     .legalFor({{S32, S1}});
104 
105   setAction({G_BITCAST, V2S16}, Legal);
106   setAction({G_BITCAST, 1, S32}, Legal);
107 
108   setAction({G_BITCAST, S32}, Legal);
109   setAction({G_BITCAST, 1, V2S16}, Legal);
110 
111   getActionDefinitionsBuilder(G_FCONSTANT)
112     .legalFor({S32, S64, S16});
113 
114   // G_IMPLICIT_DEF is a no-op so we can make it legal for any value type that
115   // can fit in a register.
116   // FIXME: We need to legalize several more operations before we can add
117   // a test case for size > 512.
118   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
119     .legalIf([=](const LegalityQuery &Query) {
120         return Query.Types[0].getSizeInBits() <= 512;
121     })
122     .clampScalar(0, S1, S512);
123 
124 
125   // FIXME: i1 operands to intrinsics should always be legal, but other i1
126   // values may not be legal.  We need to figure out how to distinguish
127   // between these two scenarios.
128   // FIXME: Pointer types
129   getActionDefinitionsBuilder(G_CONSTANT)
130     .legalFor({S1, S32, S64, V2S32, V2S16})
131     .clampScalar(0, S32, S64)
132     .widenScalarToNextPow2(0);
133 
134   setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
135 
136   getActionDefinitionsBuilder(
137     { G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA})
138     .legalFor({S32, S64});
139 
140   getActionDefinitionsBuilder(G_FPTRUNC)
141     .legalFor({{S32, S64}});
142 
143   // Use actual fsub instruction
144   setAction({G_FSUB, S32}, Legal);
145 
146   // Must use fadd + fneg
147   setAction({G_FSUB, S64}, Lower);
148 
149   setAction({G_FCMP, S1}, Legal);
150   setAction({G_FCMP, 1, S32}, Legal);
151   setAction({G_FCMP, 1, S64}, Legal);
152 
153   setAction({G_ZEXT, S64}, Legal);
154   setAction({G_ZEXT, 1, S32}, Legal);
155 
156   setAction({G_SEXT, S64}, Legal);
157   setAction({G_SEXT, 1, S32}, Legal);
158 
159   setAction({G_ANYEXT, S64}, Legal);
160   setAction({G_ANYEXT, S32}, Legal);
161   setAction({G_ANYEXT, 1, S32}, Legal);
162   setAction({G_ANYEXT, 1, S16}, Legal);
163 
164   setAction({G_FPTOSI, S32}, Legal);
165   setAction({G_FPTOSI, 1, S32}, Legal);
166 
167   setAction({G_SITOFP, S32}, Legal);
168   setAction({G_SITOFP, 1, S32}, Legal);
169 
170   setAction({G_UITOFP, S32}, Legal);
171   setAction({G_UITOFP, 1, S32}, Legal);
172 
173   setAction({G_FPTOUI, S32}, Legal);
174   setAction({G_FPTOUI, 1, S32}, Legal);
175 
176   setAction({G_FPOW, S32}, Legal);
177   setAction({G_FEXP2, S32}, Legal);
178   setAction({G_FLOG2, S32}, Legal);
179 
180   getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
181     .legalFor({S32, S64});
182 
183   for (LLT PtrTy : AddrSpaces) {
184     LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
185     setAction({G_GEP, PtrTy}, Legal);
186     setAction({G_GEP, 1, IdxTy}, Legal);
187   }
188 
189   setAction({G_BLOCK_ADDR, CodePtr}, Legal);
190 
191   setAction({G_ICMP, S1}, Legal);
192   setAction({G_ICMP, 1, S32}, Legal);
193 
194   setAction({G_CTLZ, S32}, Legal);
195   setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);
196   setAction({G_CTTZ, S32}, Legal);
197   setAction({G_CTTZ_ZERO_UNDEF, S32}, Legal);
198   setAction({G_BSWAP, S32}, Legal);
199   setAction({G_CTPOP, S32}, Legal);
200 
201   getActionDefinitionsBuilder(G_INTTOPTR)
202     .legalIf([](const LegalityQuery &Query) {
203       return true;
204     });
205 
206   getActionDefinitionsBuilder(G_PTRTOINT)
207     .legalIf([](const LegalityQuery &Query) {
208       return true;
209     });
210 
211   getActionDefinitionsBuilder({G_LOAD, G_STORE})
212     .legalIf([=, &ST](const LegalityQuery &Query) {
213         const LLT &Ty0 = Query.Types[0];
214 
215         // TODO: Decompose private loads into 4-byte components.
216         // TODO: Illegal flat loads on SI
217         switch (Ty0.getSizeInBits()) {
218         case 32:
219         case 64:
220         case 128:
221           return true;
222 
223         case 96:
224           // XXX hasLoadX3
225           return (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
226 
227         case 256:
228         case 512:
229           // TODO: constant loads
230         default:
231           return false;
232         }
233       });
234 
235 
236   auto &Atomics = getActionDefinitionsBuilder(
237     {G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB,
238      G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR,
239      G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
240      G_ATOMICRMW_UMIN, G_ATOMIC_CMPXCHG})
241     .legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
242                {S64, GlobalPtr}, {S64, LocalPtr}});
243   if (ST.hasFlatAddressSpace()) {
244     Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
245   }
246 
247   // TODO: Pointer types, any 32-bit or 64-bit vector
248   getActionDefinitionsBuilder(G_SELECT)
249     .legalFor({{S32, S1}, {S64, S1}, {V2S32, S1}, {V2S16, S1}})
250     .clampScalar(0, S32, S64);
251 
252   setAction({G_SHL, S32}, Legal);
253 
254 
255   // FIXME: When RegBankSelect inserts copies, it will only create new
256   // registers with scalar types.  This means we can end up with
257   // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
258   // operands.  In assert builds, the instruction selector will assert
259   // if it sees a generic instruction which isn't legal, so we need to
260   // tell it that scalar types are legal for pointer operands
261   setAction({G_GEP, S64}, Legal);
262 
263   for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
264     getActionDefinitionsBuilder(Op)
265       .legalIf([=](const LegalityQuery &Query) {
266           const LLT &VecTy = Query.Types[1];
267           const LLT &IdxTy = Query.Types[2];
268           return VecTy.getSizeInBits() % 32 == 0 &&
269             VecTy.getSizeInBits() <= 512 &&
270             IdxTy.getSizeInBits() == 32;
271         });
272   }
273 
274   // FIXME: Doesn't handle extract of illegal sizes.
275   getActionDefinitionsBuilder({G_EXTRACT, G_INSERT})
276     .legalIf([=](const LegalityQuery &Query) {
277         const LLT &Ty0 = Query.Types[0];
278         const LLT &Ty1 = Query.Types[1];
279         return (Ty0.getSizeInBits() % 32 == 0) &&
280                (Ty1.getSizeInBits() % 32 == 0);
281       });
282 
283   getActionDefinitionsBuilder(G_BUILD_VECTOR)
284     .legalForCartesianProduct(AllS32Vectors, {S32})
285     .legalForCartesianProduct(AllS64Vectors, {S64})
286     .clampNumElements(0, V16S32, V16S32)
287     .clampNumElements(0, V2S64, V8S64)
288     .minScalarSameAs(1, 0);
289 
290   // TODO: Support any combination of v2s32
291   getActionDefinitionsBuilder(G_CONCAT_VECTORS)
292     .legalFor({{V4S32, V2S32},
293                {V8S32, V2S32},
294                {V8S32, V4S32},
295                {V4S64, V2S64},
296                {V4S16, V2S16},
297                {V8S16, V2S16},
298                {V8S16, V4S16}});
299 
300   // Merge/Unmerge
301   for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
302     unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
303     unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
304 
305     getActionDefinitionsBuilder(Op)
306       .legalIf([=](const LegalityQuery &Query) {
307           const LLT &BigTy = Query.Types[BigTyIdx];
308           const LLT &LitTy = Query.Types[LitTyIdx];
309           return BigTy.getSizeInBits() % 32 == 0 &&
310                  LitTy.getSizeInBits() % 32 == 0 &&
311                  BigTy.getSizeInBits() <= 512;
312         })
313       // Any vectors left are the wrong size. Scalarize them.
314       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
315                        [](const LegalityQuery &Query) {
316                          return std::make_pair(
317                            0, Query.Types[0].getElementType());
318                        })
319       .fewerElementsIf([](const LegalityQuery &Query) { return true; },
320                        [](const LegalityQuery &Query) {
321                          return std::make_pair(
322                            1, Query.Types[1].getElementType());
323                        });
324 
325   }
326 
327   computeTables();
328   verify(*ST.getInstrInfo());
329 }
330