1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 17 #include "llvm/CodeGen/Register.h" 18 #include "llvm/IR/InstrTypes.h" 19 #include "llvm/IR/Intrinsics.h" 20 #include "llvm/IR/IntrinsicsAMDGPU.h" 21 22 namespace { 23 #define GET_GLOBALISEL_PREDICATE_BITSET 24 #define AMDGPUSubtarget GCNSubtarget 25 #include "AMDGPUGenGlobalISel.inc" 26 #undef GET_GLOBALISEL_PREDICATE_BITSET 27 #undef AMDGPUSubtarget 28 } 29 30 namespace llvm { 31 32 namespace AMDGPU { 33 struct ImageDimIntrinsicInfo; 34 } 35 36 class AMDGPUInstrInfo; 37 class AMDGPURegisterBankInfo; 38 class AMDGPUTargetMachine; 39 class GCNSubtarget; 40 class MachineInstr; 41 class MachineIRBuilder; 42 class MachineOperand; 43 class MachineRegisterInfo; 44 class RegisterBank; 45 class SIInstrInfo; 46 class SIMachineFunctionInfo; 47 class SIRegisterInfo; 48 class TargetRegisterClass; 49 50 class AMDGPUInstructionSelector final : public InstructionSelector { 51 private: 52 MachineRegisterInfo *MRI; 53 const GCNSubtarget *Subtarget; 54 55 public: 56 AMDGPUInstructionSelector(const GCNSubtarget &STI, 57 const AMDGPURegisterBankInfo &RBI, 58 const AMDGPUTargetMachine &TM); 59 60 bool select(MachineInstr &I) override; 61 static const char *getName(); 62 63 void setupMF(MachineFunction &MF, GISelKnownBits &KB, 64 CodeGenCoverage &CoverageInfo) override; 65 66 private: 67 struct GEPInfo { 68 const MachineInstr &GEP; 69 SmallVector<unsigned, 2> SgprParts; 70 SmallVector<unsigned, 2> VgprParts; 71 int64_t Imm; 72 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } 73 }; 74 75 bool isSGPR(Register Reg) const; 76 77 bool isInstrUniform(const MachineInstr &MI) const; 78 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 79 80 const RegisterBank *getArtifactRegBank( 81 Register Reg, const MachineRegisterInfo &MRI, 82 const TargetRegisterInfo &TRI) const; 83 84 /// tblgen-erated 'select' implementation. 85 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 86 87 MachineOperand getSubOperand64(MachineOperand &MO, 88 const TargetRegisterClass &SubRC, 89 unsigned SubIdx) const; 90 91 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const; 92 bool selectCOPY(MachineInstr &I) const; 93 bool selectPHI(MachineInstr &I) const; 94 bool selectG_TRUNC(MachineInstr &I) const; 95 bool selectG_SZA_EXT(MachineInstr &I) const; 96 bool selectG_CONSTANT(MachineInstr &I) const; 97 bool selectG_FNEG(MachineInstr &I) const; 98 bool selectG_FABS(MachineInstr &I) const; 99 bool selectG_AND_OR_XOR(MachineInstr &I) const; 100 bool selectG_ADD_SUB(MachineInstr &I) const; 101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const; 102 bool selectG_EXTRACT(MachineInstr &I) const; 103 bool selectG_MERGE_VALUES(MachineInstr &I) const; 104 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 105 bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const; 106 bool selectG_PTR_ADD(MachineInstr &I) const; 107 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 108 bool selectG_INSERT(MachineInstr &I) const; 109 110 bool selectInterpP1F16(MachineInstr &MI) const; 111 bool selectWritelane(MachineInstr &MI) const; 112 bool selectDivScale(MachineInstr &MI) const; 113 bool selectIntrinsicIcmp(MachineInstr &MI) const; 114 bool selectBallot(MachineInstr &I) const; 115 bool selectRelocConstant(MachineInstr &I) const; 116 bool selectGroupStaticSize(MachineInstr &I) const; 117 bool selectReturnAddress(MachineInstr &I) const; 118 bool selectG_INTRINSIC(MachineInstr &I) const; 119 120 bool selectEndCfIntrinsic(MachineInstr &MI) const; 121 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 122 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 123 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const; 124 bool selectSBarrier(MachineInstr &MI) const; 125 126 bool selectImageIntrinsic(MachineInstr &MI, 127 const AMDGPU::ImageDimIntrinsicInfo *Intr) const; 128 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; 129 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 130 bool selectG_ICMP(MachineInstr &I) const; 131 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 132 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 133 SmallVectorImpl<GEPInfo> &AddrInfo) const; 134 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; 135 136 void initM0(MachineInstr &I) const; 137 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const; 138 bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const; 139 bool selectG_SELECT(MachineInstr &I) const; 140 bool selectG_BRCOND(MachineInstr &I) const; 141 bool selectG_GLOBAL_VALUE(MachineInstr &I) const; 142 bool selectG_PTRMASK(MachineInstr &I) const; 143 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const; 144 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const; 145 bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const; 146 bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const; 147 bool selectGlobalAtomicFaddIntrinsic(MachineInstr &I) const; 148 bool selectBVHIntrinsic(MachineInstr &I) const; 149 150 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root, 151 bool AllowAbs = true) const; 152 153 InstructionSelector::ComplexRendererFns 154 selectVCSRC(MachineOperand &Root) const; 155 156 InstructionSelector::ComplexRendererFns 157 selectVSRC0(MachineOperand &Root) const; 158 159 InstructionSelector::ComplexRendererFns 160 selectVOP3Mods0(MachineOperand &Root) const; 161 InstructionSelector::ComplexRendererFns 162 selectVOP3BMods0(MachineOperand &Root) const; 163 InstructionSelector::ComplexRendererFns 164 selectVOP3OMods(MachineOperand &Root) const; 165 InstructionSelector::ComplexRendererFns 166 selectVOP3Mods(MachineOperand &Root) const; 167 InstructionSelector::ComplexRendererFns 168 selectVOP3BMods(MachineOperand &Root) const; 169 170 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const; 171 172 InstructionSelector::ComplexRendererFns 173 selectVOP3Mods_nnan(MachineOperand &Root) const; 174 175 std::pair<Register, unsigned> 176 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const; 177 178 InstructionSelector::ComplexRendererFns 179 selectVOP3PMods(MachineOperand &Root) const; 180 181 InstructionSelector::ComplexRendererFns 182 selectVOP3OpSelMods(MachineOperand &Root) const; 183 184 InstructionSelector::ComplexRendererFns 185 selectSmrdImm(MachineOperand &Root) const; 186 InstructionSelector::ComplexRendererFns 187 selectSmrdImm32(MachineOperand &Root) const; 188 InstructionSelector::ComplexRendererFns 189 selectSmrdSgpr(MachineOperand &Root) const; 190 191 template <bool Signed> 192 std::pair<Register, int> 193 selectFlatOffsetImpl(MachineOperand &Root) const; 194 195 InstructionSelector::ComplexRendererFns 196 selectFlatOffset(MachineOperand &Root) const; 197 InstructionSelector::ComplexRendererFns 198 selectFlatOffsetSigned(MachineOperand &Root) const; 199 200 InstructionSelector::ComplexRendererFns 201 selectGlobalSAddr(MachineOperand &Root) const; 202 203 InstructionSelector::ComplexRendererFns 204 selectScratchSAddr(MachineOperand &Root) const; 205 206 InstructionSelector::ComplexRendererFns 207 selectMUBUFScratchOffen(MachineOperand &Root) const; 208 InstructionSelector::ComplexRendererFns 209 selectMUBUFScratchOffset(MachineOperand &Root) const; 210 211 bool isDSOffsetLegal(Register Base, int64_t Offset) const; 212 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1, 213 unsigned Size) const; 214 215 std::pair<Register, unsigned> 216 selectDS1Addr1OffsetImpl(MachineOperand &Root) const; 217 InstructionSelector::ComplexRendererFns 218 selectDS1Addr1Offset(MachineOperand &Root) const; 219 220 InstructionSelector::ComplexRendererFns 221 selectDS64Bit4ByteAligned(MachineOperand &Root) const; 222 223 InstructionSelector::ComplexRendererFns 224 selectDS128Bit8ByteAligned(MachineOperand &Root) const; 225 226 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root, 227 unsigned size) const; 228 InstructionSelector::ComplexRendererFns 229 selectDSReadWrite2(MachineOperand &Root, unsigned size) const; 230 231 std::pair<Register, int64_t> 232 getPtrBaseWithConstantOffset(Register Root, 233 const MachineRegisterInfo &MRI) const; 234 235 // Parse out a chain of up to two g_ptr_add instructions. 236 // g_ptr_add (n0, _) 237 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3)) 238 struct MUBUFAddressData { 239 Register N0, N2, N3; 240 int64_t Offset = 0; 241 }; 242 243 bool shouldUseAddr64(MUBUFAddressData AddrData) const; 244 245 void splitIllegalMUBUFOffset(MachineIRBuilder &B, 246 Register &SOffset, int64_t &ImmOffset) const; 247 248 MUBUFAddressData parseMUBUFAddress(Register Src) const; 249 250 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr, 251 Register &RSrcReg, Register &SOffset, 252 int64_t &Offset) const; 253 254 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg, 255 Register &SOffset, int64_t &Offset) const; 256 257 InstructionSelector::ComplexRendererFns 258 selectMUBUFAddr64(MachineOperand &Root) const; 259 260 InstructionSelector::ComplexRendererFns 261 selectMUBUFOffset(MachineOperand &Root) const; 262 263 InstructionSelector::ComplexRendererFns 264 selectMUBUFOffsetAtomic(MachineOperand &Root) const; 265 266 InstructionSelector::ComplexRendererFns 267 selectMUBUFAddr64Atomic(MachineOperand &Root) const; 268 269 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const; 270 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const; 271 272 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, 273 int OpIdx = -1) const; 274 275 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 276 int OpIdx) const; 277 278 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 279 int OpIdx) const; 280 281 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 282 int OpIdx) const; 283 284 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 285 int OpIdx) const; 286 void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 287 int OpIdx) const; 288 void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 289 int OpIdx) const; 290 void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 291 int OpIdx) const; 292 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, 293 int OpIdx) const; 294 void renderExtractSCCB(MachineInstrBuilder &MIB, const MachineInstr &MI, 295 int OpIdx) const; 296 297 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI, 298 int OpIdx) const; 299 300 bool isInlineImmediate16(int64_t Imm) const; 301 bool isInlineImmediate32(int64_t Imm) const; 302 bool isInlineImmediate64(int64_t Imm) const; 303 bool isInlineImmediate(const APFloat &Imm) const; 304 305 const SIInstrInfo &TII; 306 const SIRegisterInfo &TRI; 307 const AMDGPURegisterBankInfo &RBI; 308 const AMDGPUTargetMachine &TM; 309 const GCNSubtarget &STI; 310 bool EnableLateStructurizeCFG; 311 #define GET_GLOBALISEL_PREDICATES_DECL 312 #define AMDGPUSubtarget GCNSubtarget 313 #include "AMDGPUGenGlobalISel.inc" 314 #undef GET_GLOBALISEL_PREDICATES_DECL 315 #undef AMDGPUSubtarget 316 317 #define GET_GLOBALISEL_TEMPORARIES_DECL 318 #include "AMDGPUGenGlobalISel.inc" 319 #undef GET_GLOBALISEL_TEMPORARIES_DECL 320 }; 321 322 } // End llvm namespace. 323 #endif 324