1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 namespace AMDGPU {
35 struct ImageDimIntrinsicInfo;
36 }
37 
38 class AMDGPUInstrInfo;
39 class AMDGPURegisterBankInfo;
40 class GCNSubtarget;
41 class MachineInstr;
42 class MachineIRBuilder;
43 class MachineOperand;
44 class MachineRegisterInfo;
45 class RegisterBank;
46 class SIInstrInfo;
47 class SIMachineFunctionInfo;
48 class SIRegisterInfo;
49 
50 class AMDGPUInstructionSelector final : public InstructionSelector {
51 private:
52   MachineRegisterInfo *MRI;
53   const GCNSubtarget *Subtarget;
54 
55 public:
56   AMDGPUInstructionSelector(const GCNSubtarget &STI,
57                             const AMDGPURegisterBankInfo &RBI,
58                             const AMDGPUTargetMachine &TM);
59 
60   bool select(MachineInstr &I) override;
61   static const char *getName();
62 
63   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
64                CodeGenCoverage &CoverageInfo) override;
65 
66 private:
67   struct GEPInfo {
68     const MachineInstr &GEP;
69     SmallVector<unsigned, 2> SgprParts;
70     SmallVector<unsigned, 2> VgprParts;
71     int64_t Imm;
72     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
73   };
74 
75   bool isInstrUniform(const MachineInstr &MI) const;
76   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 
78   const RegisterBank *getArtifactRegBank(
79     Register Reg, const MachineRegisterInfo &MRI,
80     const TargetRegisterInfo &TRI) const;
81 
82   /// tblgen-erated 'select' implementation.
83   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
84 
85   MachineOperand getSubOperand64(MachineOperand &MO,
86                                  const TargetRegisterClass &SubRC,
87                                  unsigned SubIdx) const;
88 
89   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
90   bool selectCOPY(MachineInstr &I) const;
91   bool selectPHI(MachineInstr &I) const;
92   bool selectG_TRUNC(MachineInstr &I) const;
93   bool selectG_SZA_EXT(MachineInstr &I) const;
94   bool selectG_CONSTANT(MachineInstr &I) const;
95   bool selectG_FNEG(MachineInstr &I) const;
96   bool selectG_FABS(MachineInstr &I) const;
97   bool selectG_AND_OR_XOR(MachineInstr &I) const;
98   bool selectG_ADD_SUB(MachineInstr &I) const;
99   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100   bool selectG_EXTRACT(MachineInstr &I) const;
101   bool selectG_MERGE_VALUES(MachineInstr &I) const;
102   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
103   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
104   bool selectG_PTR_ADD(MachineInstr &I) const;
105   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
106   bool selectG_INSERT(MachineInstr &I) const;
107 
108   bool selectInterpP1F16(MachineInstr &MI) const;
109   bool selectWritelane(MachineInstr &MI) const;
110   bool selectDivScale(MachineInstr &MI) const;
111   bool selectIntrinsicIcmp(MachineInstr &MI) const;
112   bool selectBallot(MachineInstr &I) const;
113   bool selectRelocConstant(MachineInstr &I) const;
114   bool selectGroupStaticSize(MachineInstr &I) const;
115   bool selectReturnAddress(MachineInstr &I) const;
116   bool selectG_INTRINSIC(MachineInstr &I) const;
117 
118   bool selectEndCfIntrinsic(MachineInstr &MI) const;
119   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
120   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
121   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
122   bool selectSBarrier(MachineInstr &MI) const;
123 
124   bool selectImageIntrinsic(MachineInstr &MI,
125                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
126   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
127   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
128   bool selectG_ICMP(MachineInstr &I) const;
129   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
130   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
131                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
132   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
133 
134   void initM0(MachineInstr &I) const;
135   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
136   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
137   bool selectG_SELECT(MachineInstr &I) const;
138   bool selectG_BRCOND(MachineInstr &I) const;
139   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
140   bool selectG_PTRMASK(MachineInstr &I) const;
141   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
142   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
143   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
144   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
145   bool selectGlobalAtomicFaddIntrinsic(MachineInstr &I) const;
146   bool selectBVHIntrinsic(MachineInstr &I) const;
147 
148   std::pair<Register, unsigned>
149   selectVOP3ModsImpl(MachineOperand &Root) const;
150 
151   InstructionSelector::ComplexRendererFns
152   selectVCSRC(MachineOperand &Root) const;
153 
154   InstructionSelector::ComplexRendererFns
155   selectVSRC0(MachineOperand &Root) const;
156 
157   InstructionSelector::ComplexRendererFns
158   selectVOP3Mods0(MachineOperand &Root) const;
159   InstructionSelector::ComplexRendererFns
160   selectVOP3OMods(MachineOperand &Root) const;
161   InstructionSelector::ComplexRendererFns
162   selectVOP3Mods(MachineOperand &Root) const;
163 
164   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
165 
166   InstructionSelector::ComplexRendererFns
167   selectVOP3Mods_nnan(MachineOperand &Root) const;
168 
169   std::pair<Register, unsigned>
170   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
171 
172   InstructionSelector::ComplexRendererFns
173   selectVOP3PMods(MachineOperand &Root) const;
174 
175   InstructionSelector::ComplexRendererFns
176   selectVOP3OpSelMods(MachineOperand &Root) const;
177 
178   InstructionSelector::ComplexRendererFns
179   selectSmrdImm(MachineOperand &Root) const;
180   InstructionSelector::ComplexRendererFns
181   selectSmrdImm32(MachineOperand &Root) const;
182   InstructionSelector::ComplexRendererFns
183   selectSmrdSgpr(MachineOperand &Root) const;
184 
185   template <bool Signed>
186   std::pair<Register, int>
187   selectFlatOffsetImpl(MachineOperand &Root) const;
188 
189   InstructionSelector::ComplexRendererFns
190   selectFlatOffset(MachineOperand &Root) const;
191   InstructionSelector::ComplexRendererFns
192   selectFlatOffsetSigned(MachineOperand &Root) const;
193 
194   InstructionSelector::ComplexRendererFns
195   selectGlobalSAddr(MachineOperand &Root) const;
196 
197   InstructionSelector::ComplexRendererFns
198   selectMUBUFScratchOffen(MachineOperand &Root) const;
199   InstructionSelector::ComplexRendererFns
200   selectMUBUFScratchOffset(MachineOperand &Root) const;
201 
202   bool isDSOffsetLegal(Register Base, int64_t Offset,
203                        unsigned OffsetBits) const;
204 
205   std::pair<Register, unsigned>
206   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
207   InstructionSelector::ComplexRendererFns
208   selectDS1Addr1Offset(MachineOperand &Root) const;
209 
210   InstructionSelector::ComplexRendererFns
211   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
212 
213   InstructionSelector::ComplexRendererFns
214   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
215 
216   std::pair<Register, unsigned>
217   selectDSReadWrite2Impl(MachineOperand &Root, bool IsDS128) const;
218   InstructionSelector::ComplexRendererFns
219   selectDSReadWrite2(MachineOperand &Root, bool IsDS128) const;
220 
221   std::pair<Register, int64_t>
222   getPtrBaseWithConstantOffset(Register Root,
223                                const MachineRegisterInfo &MRI) const;
224 
225   // Parse out a chain of up to two g_ptr_add instructions.
226   // g_ptr_add (n0, _)
227   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
228   struct MUBUFAddressData {
229     Register N0, N2, N3;
230     int64_t Offset = 0;
231   };
232 
233   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
234 
235   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
236                                Register &SOffset, int64_t &ImmOffset) const;
237 
238   MUBUFAddressData parseMUBUFAddress(Register Src) const;
239 
240   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
241                              Register &RSrcReg, Register &SOffset,
242                              int64_t &Offset) const;
243 
244   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
245                              Register &SOffset, int64_t &Offset) const;
246 
247   InstructionSelector::ComplexRendererFns
248   selectMUBUFAddr64(MachineOperand &Root) const;
249 
250   InstructionSelector::ComplexRendererFns
251   selectMUBUFOffset(MachineOperand &Root) const;
252 
253   InstructionSelector::ComplexRendererFns
254   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
255 
256   InstructionSelector::ComplexRendererFns
257   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
258 
259   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
260   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
261 
262   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
263                         int OpIdx = -1) const;
264 
265   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
266                        int OpIdx) const;
267 
268   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
269                         int OpIdx) const {
270     renderTruncTImm(MIB, MI, OpIdx);
271   }
272 
273   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
274                         int OpIdx) const {
275     renderTruncTImm(MIB, MI, OpIdx);
276   }
277 
278   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
279                         int OpIdx) const {
280     renderTruncTImm(MIB, MI, OpIdx);
281   }
282 
283   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
284                         int OpIdx) const {
285     renderTruncTImm(MIB, MI, OpIdx);
286   }
287 
288   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
289                        int OpIdx) const;
290 
291   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
292                         int OpIdx) const;
293 
294   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
295                        int OpIdx) const;
296   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
297                         int OpIdx) const;
298   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
299                         int OpIdx) const;
300   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
301                         int OpIdx) const;
302   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
303                         int OpIdx) const;
304   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
305                         int OpIdx) const;
306 
307   bool isInlineImmediate16(int64_t Imm) const;
308   bool isInlineImmediate32(int64_t Imm) const;
309   bool isInlineImmediate64(int64_t Imm) const;
310   bool isInlineImmediate(const APFloat &Imm) const;
311 
312   const SIInstrInfo &TII;
313   const SIRegisterInfo &TRI;
314   const AMDGPURegisterBankInfo &RBI;
315   const AMDGPUTargetMachine &TM;
316   const GCNSubtarget &STI;
317   bool EnableLateStructurizeCFG;
318 #define GET_GLOBALISEL_PREDICATES_DECL
319 #define AMDGPUSubtarget GCNSubtarget
320 #include "AMDGPUGenGlobalISel.inc"
321 #undef GET_GLOBALISEL_PREDICATES_DECL
322 #undef AMDGPUSubtarget
323 
324 #define GET_GLOBALISEL_TEMPORARIES_DECL
325 #include "AMDGPUGenGlobalISel.inc"
326 #undef GET_GLOBALISEL_TEMPORARIES_DECL
327 };
328 
329 } // End llvm namespace.
330 #endif
331