1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 namespace AMDGPU {
35 struct ImageDimIntrinsicInfo;
36 }
37 
38 class AMDGPUInstrInfo;
39 class AMDGPURegisterBankInfo;
40 class GCNSubtarget;
41 class MachineInstr;
42 class MachineIRBuilder;
43 class MachineOperand;
44 class MachineRegisterInfo;
45 class RegisterBank;
46 class SIInstrInfo;
47 class SIMachineFunctionInfo;
48 class SIRegisterInfo;
49 
50 class AMDGPUInstructionSelector final : public InstructionSelector {
51 private:
52   MachineRegisterInfo *MRI;
53   const GCNSubtarget *Subtarget;
54 
55 public:
56   AMDGPUInstructionSelector(const GCNSubtarget &STI,
57                             const AMDGPURegisterBankInfo &RBI,
58                             const AMDGPUTargetMachine &TM);
59 
60   bool select(MachineInstr &I) override;
61   static const char *getName();
62 
63   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
64                CodeGenCoverage &CoverageInfo) override;
65 
66 private:
67   struct GEPInfo {
68     const MachineInstr &GEP;
69     SmallVector<unsigned, 2> SgprParts;
70     SmallVector<unsigned, 2> VgprParts;
71     int64_t Imm;
72     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
73   };
74 
75   bool isSGPR(Register Reg) const;
76 
77   bool isInstrUniform(const MachineInstr &MI) const;
78   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
79 
80   const RegisterBank *getArtifactRegBank(
81     Register Reg, const MachineRegisterInfo &MRI,
82     const TargetRegisterInfo &TRI) const;
83 
84   /// tblgen-erated 'select' implementation.
85   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
86 
87   MachineOperand getSubOperand64(MachineOperand &MO,
88                                  const TargetRegisterClass &SubRC,
89                                  unsigned SubIdx) const;
90 
91   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
92   bool selectCOPY(MachineInstr &I) const;
93   bool selectPHI(MachineInstr &I) const;
94   bool selectG_TRUNC(MachineInstr &I) const;
95   bool selectG_SZA_EXT(MachineInstr &I) const;
96   bool selectG_CONSTANT(MachineInstr &I) const;
97   bool selectG_FNEG(MachineInstr &I) const;
98   bool selectG_FABS(MachineInstr &I) const;
99   bool selectG_AND_OR_XOR(MachineInstr &I) const;
100   bool selectG_ADD_SUB(MachineInstr &I) const;
101   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102   bool selectG_EXTRACT(MachineInstr &I) const;
103   bool selectG_MERGE_VALUES(MachineInstr &I) const;
104   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
106   bool selectG_PTR_ADD(MachineInstr &I) const;
107   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
108   bool selectG_INSERT(MachineInstr &I) const;
109 
110   bool selectInterpP1F16(MachineInstr &MI) const;
111   bool selectWritelane(MachineInstr &MI) const;
112   bool selectDivScale(MachineInstr &MI) const;
113   bool selectIntrinsicIcmp(MachineInstr &MI) const;
114   bool selectBallot(MachineInstr &I) const;
115   bool selectRelocConstant(MachineInstr &I) const;
116   bool selectGroupStaticSize(MachineInstr &I) const;
117   bool selectReturnAddress(MachineInstr &I) const;
118   bool selectG_INTRINSIC(MachineInstr &I) const;
119 
120   bool selectEndCfIntrinsic(MachineInstr &MI) const;
121   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
124   bool selectSBarrier(MachineInstr &MI) const;
125 
126   bool selectImageIntrinsic(MachineInstr &MI,
127                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
128   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
129   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
130   bool selectG_ICMP(MachineInstr &I) const;
131   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
132   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
133                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
134   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
135 
136   void initM0(MachineInstr &I) const;
137   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
138   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
139   bool selectG_SELECT(MachineInstr &I) const;
140   bool selectG_BRCOND(MachineInstr &I) const;
141   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
142   bool selectG_PTRMASK(MachineInstr &I) const;
143   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
144   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
145   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
146   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
147   bool selectGlobalAtomicFaddIntrinsic(MachineInstr &I) const;
148   bool selectBVHIntrinsic(MachineInstr &I) const;
149 
150   std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
151                                                    bool AllowAbs = true) const;
152 
153   InstructionSelector::ComplexRendererFns
154   selectVCSRC(MachineOperand &Root) const;
155 
156   InstructionSelector::ComplexRendererFns
157   selectVSRC0(MachineOperand &Root) const;
158 
159   InstructionSelector::ComplexRendererFns
160   selectVOP3Mods0(MachineOperand &Root) const;
161   InstructionSelector::ComplexRendererFns
162   selectVOP3BMods0(MachineOperand &Root) const;
163   InstructionSelector::ComplexRendererFns
164   selectVOP3OMods(MachineOperand &Root) const;
165   InstructionSelector::ComplexRendererFns
166   selectVOP3Mods(MachineOperand &Root) const;
167   InstructionSelector::ComplexRendererFns
168   selectVOP3BMods(MachineOperand &Root) const;
169 
170   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
171 
172   InstructionSelector::ComplexRendererFns
173   selectVOP3Mods_nnan(MachineOperand &Root) const;
174 
175   std::pair<Register, unsigned>
176   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
177 
178   InstructionSelector::ComplexRendererFns
179   selectVOP3PMods(MachineOperand &Root) const;
180 
181   InstructionSelector::ComplexRendererFns
182   selectVOP3OpSelMods(MachineOperand &Root) const;
183 
184   InstructionSelector::ComplexRendererFns
185   selectSmrdImm(MachineOperand &Root) const;
186   InstructionSelector::ComplexRendererFns
187   selectSmrdImm32(MachineOperand &Root) const;
188   InstructionSelector::ComplexRendererFns
189   selectSmrdSgpr(MachineOperand &Root) const;
190 
191   template <bool Signed>
192   std::pair<Register, int>
193   selectFlatOffsetImpl(MachineOperand &Root) const;
194 
195   InstructionSelector::ComplexRendererFns
196   selectFlatOffset(MachineOperand &Root) const;
197   InstructionSelector::ComplexRendererFns
198   selectFlatOffsetSigned(MachineOperand &Root) const;
199 
200   InstructionSelector::ComplexRendererFns
201   selectGlobalSAddr(MachineOperand &Root) const;
202 
203   InstructionSelector::ComplexRendererFns
204   selectMUBUFScratchOffen(MachineOperand &Root) const;
205   InstructionSelector::ComplexRendererFns
206   selectMUBUFScratchOffset(MachineOperand &Root) const;
207 
208   bool isDSOffsetLegal(Register Base, int64_t Offset) const;
209   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
210                         unsigned Size) const;
211 
212   std::pair<Register, unsigned>
213   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
214   InstructionSelector::ComplexRendererFns
215   selectDS1Addr1Offset(MachineOperand &Root) const;
216 
217   InstructionSelector::ComplexRendererFns
218   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
219 
220   InstructionSelector::ComplexRendererFns
221   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
222 
223   std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
224                                                        unsigned size) const;
225   InstructionSelector::ComplexRendererFns
226   selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
227 
228   std::pair<Register, int64_t>
229   getPtrBaseWithConstantOffset(Register Root,
230                                const MachineRegisterInfo &MRI) const;
231 
232   // Parse out a chain of up to two g_ptr_add instructions.
233   // g_ptr_add (n0, _)
234   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
235   struct MUBUFAddressData {
236     Register N0, N2, N3;
237     int64_t Offset = 0;
238   };
239 
240   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
241 
242   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
243                                Register &SOffset, int64_t &ImmOffset) const;
244 
245   MUBUFAddressData parseMUBUFAddress(Register Src) const;
246 
247   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
248                              Register &RSrcReg, Register &SOffset,
249                              int64_t &Offset) const;
250 
251   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
252                              Register &SOffset, int64_t &Offset) const;
253 
254   InstructionSelector::ComplexRendererFns
255   selectMUBUFAddr64(MachineOperand &Root) const;
256 
257   InstructionSelector::ComplexRendererFns
258   selectMUBUFOffset(MachineOperand &Root) const;
259 
260   InstructionSelector::ComplexRendererFns
261   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
262 
263   InstructionSelector::ComplexRendererFns
264   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
265 
266   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
267   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
268 
269   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
270                         int OpIdx = -1) const;
271 
272   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
273                        int OpIdx) const;
274 
275   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
276                         int OpIdx) const {
277     renderTruncTImm(MIB, MI, OpIdx);
278   }
279 
280   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
281                         int OpIdx) const {
282     renderTruncTImm(MIB, MI, OpIdx);
283   }
284 
285   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
286                         int OpIdx) const {
287     renderTruncTImm(MIB, MI, OpIdx);
288   }
289 
290   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
291                         int OpIdx) const {
292     renderTruncTImm(MIB, MI, OpIdx);
293   }
294 
295   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
296                        int OpIdx) const;
297 
298   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
299                         int OpIdx) const;
300 
301   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
302                        int OpIdx) const;
303   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
304                         int OpIdx) const;
305   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
306                         int OpIdx) const;
307   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
308                         int OpIdx) const;
309   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
310                         int OpIdx) const;
311   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
312                         int OpIdx) const;
313 
314   bool isInlineImmediate16(int64_t Imm) const;
315   bool isInlineImmediate32(int64_t Imm) const;
316   bool isInlineImmediate64(int64_t Imm) const;
317   bool isInlineImmediate(const APFloat &Imm) const;
318 
319   const SIInstrInfo &TII;
320   const SIRegisterInfo &TRI;
321   const AMDGPURegisterBankInfo &RBI;
322   const AMDGPUTargetMachine &TM;
323   const GCNSubtarget &STI;
324   bool EnableLateStructurizeCFG;
325 #define GET_GLOBALISEL_PREDICATES_DECL
326 #define AMDGPUSubtarget GCNSubtarget
327 #include "AMDGPUGenGlobalISel.inc"
328 #undef GET_GLOBALISEL_PREDICATES_DECL
329 #undef AMDGPUSubtarget
330 
331 #define GET_GLOBALISEL_TEMPORARIES_DECL
332 #include "AMDGPUGenGlobalISel.inc"
333 #undef GET_GLOBALISEL_TEMPORARIES_DECL
334 };
335 
336 } // End llvm namespace.
337 #endif
338