1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 namespace AMDGPU {
35 struct ImageDimIntrinsicInfo;
36 }
37 
38 class AMDGPUInstrInfo;
39 class AMDGPURegisterBankInfo;
40 class GCNSubtarget;
41 class MachineInstr;
42 class MachineIRBuilder;
43 class MachineOperand;
44 class MachineRegisterInfo;
45 class RegisterBank;
46 class SIInstrInfo;
47 class SIMachineFunctionInfo;
48 class SIRegisterInfo;
49 
50 class AMDGPUInstructionSelector final : public InstructionSelector {
51 private:
52   MachineRegisterInfo *MRI;
53 
54 public:
55   AMDGPUInstructionSelector(const GCNSubtarget &STI,
56                             const AMDGPURegisterBankInfo &RBI,
57                             const AMDGPUTargetMachine &TM);
58 
59   bool select(MachineInstr &I) override;
60   static const char *getName();
61 
62   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
63                CodeGenCoverage &CoverageInfo) override;
64 
65 private:
66   struct GEPInfo {
67     const MachineInstr &GEP;
68     SmallVector<unsigned, 2> SgprParts;
69     SmallVector<unsigned, 2> VgprParts;
70     int64_t Imm;
71     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
72   };
73 
74   bool isInstrUniform(const MachineInstr &MI) const;
75   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76 
77   const RegisterBank *getArtifactRegBank(
78     Register Reg, const MachineRegisterInfo &MRI,
79     const TargetRegisterInfo &TRI) const;
80 
81   /// tblgen-erated 'select' implementation.
82   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83 
84   MachineOperand getSubOperand64(MachineOperand &MO,
85                                  const TargetRegisterClass &SubRC,
86                                  unsigned SubIdx) const;
87 
88   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89   bool selectCOPY(MachineInstr &I) const;
90   bool selectPHI(MachineInstr &I) const;
91   bool selectG_TRUNC(MachineInstr &I) const;
92   bool selectG_SZA_EXT(MachineInstr &I) const;
93   bool selectG_CONSTANT(MachineInstr &I) const;
94   bool selectG_FNEG(MachineInstr &I) const;
95   bool selectG_FABS(MachineInstr &I) const;
96   bool selectG_AND_OR_XOR(MachineInstr &I) const;
97   bool selectG_ADD_SUB(MachineInstr &I) const;
98   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
99   bool selectG_EXTRACT(MachineInstr &I) const;
100   bool selectG_MERGE_VALUES(MachineInstr &I) const;
101   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
102   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
103   bool selectG_PTR_ADD(MachineInstr &I) const;
104   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
105   bool selectG_INSERT(MachineInstr &I) const;
106 
107   bool selectInterpP1F16(MachineInstr &MI) const;
108   bool selectWritelane(MachineInstr &MI) const;
109   bool selectDivScale(MachineInstr &MI) const;
110   bool selectIntrinsicIcmp(MachineInstr &MI) const;
111   bool selectBallot(MachineInstr &I) const;
112   bool selectRelocConstant(MachineInstr &I) const;
113   bool selectGroupStaticSize(MachineInstr &I) const;
114   bool selectReturnAddress(MachineInstr &I) const;
115   bool selectG_INTRINSIC(MachineInstr &I) const;
116 
117   bool selectEndCfIntrinsic(MachineInstr &MI) const;
118   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
119   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
120   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
121 
122   bool selectImageIntrinsic(MachineInstr &MI,
123                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
124   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
125   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
126   bool selectG_ICMP(MachineInstr &I) const;
127   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
128   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
129                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
130   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
131 
132   void initM0(MachineInstr &I) const;
133   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
134   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
135   bool selectG_SELECT(MachineInstr &I) const;
136   bool selectG_BRCOND(MachineInstr &I) const;
137   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
138   bool selectG_PTRMASK(MachineInstr &I) const;
139   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
140   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
141   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
142 
143   std::pair<Register, unsigned>
144   selectVOP3ModsImpl(MachineOperand &Root) const;
145 
146   InstructionSelector::ComplexRendererFns
147   selectVCSRC(MachineOperand &Root) const;
148 
149   InstructionSelector::ComplexRendererFns
150   selectVSRC0(MachineOperand &Root) const;
151 
152   InstructionSelector::ComplexRendererFns
153   selectVOP3Mods0(MachineOperand &Root) const;
154   InstructionSelector::ComplexRendererFns
155   selectVOP3OMods(MachineOperand &Root) const;
156   InstructionSelector::ComplexRendererFns
157   selectVOP3Mods(MachineOperand &Root) const;
158 
159   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
160 
161   InstructionSelector::ComplexRendererFns
162   selectVOP3Mods_nnan(MachineOperand &Root) const;
163 
164   std::pair<Register, unsigned>
165   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
166 
167   InstructionSelector::ComplexRendererFns
168   selectVOP3PMods(MachineOperand &Root) const;
169 
170   InstructionSelector::ComplexRendererFns
171   selectVOP3OpSelMods(MachineOperand &Root) const;
172 
173   InstructionSelector::ComplexRendererFns
174   selectSmrdImm(MachineOperand &Root) const;
175   InstructionSelector::ComplexRendererFns
176   selectSmrdImm32(MachineOperand &Root) const;
177   InstructionSelector::ComplexRendererFns
178   selectSmrdSgpr(MachineOperand &Root) const;
179 
180   template <bool Signed>
181   InstructionSelector::ComplexRendererFns
182   selectFlatOffsetImpl(MachineOperand &Root) const;
183   InstructionSelector::ComplexRendererFns
184   selectFlatOffset(MachineOperand &Root) const;
185 
186   InstructionSelector::ComplexRendererFns
187   selectFlatOffsetSigned(MachineOperand &Root) const;
188 
189   InstructionSelector::ComplexRendererFns
190   selectGlobalSAddr(MachineOperand &Root) const;
191 
192   InstructionSelector::ComplexRendererFns
193   selectMUBUFScratchOffen(MachineOperand &Root) const;
194   InstructionSelector::ComplexRendererFns
195   selectMUBUFScratchOffset(MachineOperand &Root) const;
196 
197   bool isDSOffsetLegal(Register Base, int64_t Offset,
198                        unsigned OffsetBits) const;
199 
200   std::pair<Register, unsigned>
201   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
202   InstructionSelector::ComplexRendererFns
203   selectDS1Addr1Offset(MachineOperand &Root) const;
204 
205   InstructionSelector::ComplexRendererFns
206   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
207 
208   InstructionSelector::ComplexRendererFns
209   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
210 
211   std::pair<Register, unsigned>
212   selectDSReadWrite2Impl(MachineOperand &Root, bool IsDS128) const;
213   InstructionSelector::ComplexRendererFns
214   selectDSReadWrite2(MachineOperand &Root, bool IsDS128) const;
215 
216   std::pair<Register, int64_t>
217   getPtrBaseWithConstantOffset(Register Root,
218                                const MachineRegisterInfo &MRI) const;
219 
220   // Parse out a chain of up to two g_ptr_add instructions.
221   // g_ptr_add (n0, _)
222   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
223   struct MUBUFAddressData {
224     Register N0, N2, N3;
225     int64_t Offset = 0;
226   };
227 
228   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
229 
230   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
231                                Register &SOffset, int64_t &ImmOffset) const;
232 
233   MUBUFAddressData parseMUBUFAddress(Register Src) const;
234 
235   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
236                              Register &RSrcReg, Register &SOffset,
237                              int64_t &Offset) const;
238 
239   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
240                              Register &SOffset, int64_t &Offset) const;
241 
242   InstructionSelector::ComplexRendererFns
243   selectMUBUFAddr64(MachineOperand &Root) const;
244 
245   InstructionSelector::ComplexRendererFns
246   selectMUBUFOffset(MachineOperand &Root) const;
247 
248   InstructionSelector::ComplexRendererFns
249   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
250 
251   InstructionSelector::ComplexRendererFns
252   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
253 
254   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
255   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
256 
257   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
258                         int OpIdx = -1) const;
259 
260   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
261                        int OpIdx) const;
262 
263   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
264                         int OpIdx) const {
265     renderTruncTImm(MIB, MI, OpIdx);
266   }
267 
268   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
269                         int OpIdx) const {
270     renderTruncTImm(MIB, MI, OpIdx);
271   }
272 
273   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
274                         int OpIdx) const {
275     renderTruncTImm(MIB, MI, OpIdx);
276   }
277 
278   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
279                         int OpIdx) const {
280     renderTruncTImm(MIB, MI, OpIdx);
281   }
282 
283   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
284                        int OpIdx) const;
285 
286   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
287                         int OpIdx) const;
288 
289   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
290                        int OpIdx) const;
291   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
292                         int OpIdx) const;
293   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
294                         int OpIdx) const;
295   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
296                         int OpIdx) const;
297   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
298                         int OpIdx) const;
299   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
300                         int OpIdx) const;
301 
302   bool isInlineImmediate16(int64_t Imm) const;
303   bool isInlineImmediate32(int64_t Imm) const;
304   bool isInlineImmediate64(int64_t Imm) const;
305   bool isInlineImmediate(const APFloat &Imm) const;
306 
307   const SIInstrInfo &TII;
308   const SIRegisterInfo &TRI;
309   const AMDGPURegisterBankInfo &RBI;
310   const AMDGPUTargetMachine &TM;
311   const GCNSubtarget &STI;
312   bool EnableLateStructurizeCFG;
313 #define GET_GLOBALISEL_PREDICATES_DECL
314 #define AMDGPUSubtarget GCNSubtarget
315 #include "AMDGPUGenGlobalISel.inc"
316 #undef GET_GLOBALISEL_PREDICATES_DECL
317 #undef AMDGPUSubtarget
318 
319 #define GET_GLOBALISEL_TEMPORARIES_DECL
320 #include "AMDGPUGenGlobalISel.inc"
321 #undef GET_GLOBALISEL_TEMPORARIES_DECL
322 };
323 
324 } // End llvm namespace.
325 #endif
326