1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 class AMDGPUInstrInfo;
35 class AMDGPURegisterBankInfo;
36 class GCNSubtarget;
37 class MachineInstr;
38 class MachineIRBuilder;
39 class MachineOperand;
40 class MachineRegisterInfo;
41 class RegisterBank;
42 class SIInstrInfo;
43 class SIMachineFunctionInfo;
44 class SIRegisterInfo;
45 
46 class AMDGPUInstructionSelector : public InstructionSelector {
47 private:
48   MachineRegisterInfo *MRI;
49 
50 public:
51   AMDGPUInstructionSelector(const GCNSubtarget &STI,
52                             const AMDGPURegisterBankInfo &RBI,
53                             const AMDGPUTargetMachine &TM);
54 
55   bool select(MachineInstr &I) override;
56   static const char *getName();
57 
58   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
59                CodeGenCoverage &CoverageInfo) override;
60 
61 private:
62   struct GEPInfo {
63     const MachineInstr &GEP;
64     SmallVector<unsigned, 2> SgprParts;
65     SmallVector<unsigned, 2> VgprParts;
66     int64_t Imm;
67     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
68   };
69 
70   bool isInstrUniform(const MachineInstr &MI) const;
71   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
72 
73   const RegisterBank *getArtifactRegBank(
74     Register Reg, const MachineRegisterInfo &MRI,
75     const TargetRegisterInfo &TRI) const;
76 
77   /// tblgen-erated 'select' implementation.
78   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
79 
80   MachineOperand getSubOperand64(MachineOperand &MO,
81                                  const TargetRegisterClass &SubRC,
82                                  unsigned SubIdx) const;
83 
84   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
85   bool selectCOPY(MachineInstr &I) const;
86   bool selectPHI(MachineInstr &I) const;
87   bool selectG_TRUNC(MachineInstr &I) const;
88   bool selectG_SZA_EXT(MachineInstr &I) const;
89   bool selectG_CONSTANT(MachineInstr &I) const;
90   bool selectG_FNEG(MachineInstr &I) const;
91   bool selectG_AND_OR_XOR(MachineInstr &I) const;
92   bool selectG_ADD_SUB(MachineInstr &I) const;
93   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
94   bool selectG_EXTRACT(MachineInstr &I) const;
95   bool selectG_MERGE_VALUES(MachineInstr &I) const;
96   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
97   bool selectG_PTR_ADD(MachineInstr &I) const;
98   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
99   bool selectG_INSERT(MachineInstr &I) const;
100 
101   bool selectInterpP1F16(MachineInstr &MI) const;
102   bool selectG_INTRINSIC(MachineInstr &I) const;
103 
104   bool selectEndCfIntrinsic(MachineInstr &MI) const;
105   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
106   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
107   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
108 
109   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
110   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
111   bool selectG_ICMP(MachineInstr &I) const;
112   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
113   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
114                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
115   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
116 
117   void initM0(MachineInstr &I) const;
118   bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
119   bool selectG_STORE(MachineInstr &I) const;
120   bool selectG_SELECT(MachineInstr &I) const;
121   bool selectG_BRCOND(MachineInstr &I) const;
122   bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const;
123   bool selectG_PTR_MASK(MachineInstr &I) const;
124   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
125   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
126 
127   std::pair<Register, unsigned>
128   selectVOP3ModsImpl(Register Src) const;
129 
130   InstructionSelector::ComplexRendererFns
131   selectVCSRC(MachineOperand &Root) const;
132 
133   InstructionSelector::ComplexRendererFns
134   selectVSRC0(MachineOperand &Root) const;
135 
136   InstructionSelector::ComplexRendererFns
137   selectVOP3Mods0(MachineOperand &Root) const;
138   InstructionSelector::ComplexRendererFns
139   selectVOP3OMods(MachineOperand &Root) const;
140   InstructionSelector::ComplexRendererFns
141   selectVOP3Mods(MachineOperand &Root) const;
142 
143   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
144 
145   InstructionSelector::ComplexRendererFns
146   selectVOP3Mods_nnan(MachineOperand &Root) const;
147 
148   InstructionSelector::ComplexRendererFns
149   selectVOP3OpSelMods0(MachineOperand &Root) const;
150   InstructionSelector::ComplexRendererFns
151   selectVOP3OpSelMods(MachineOperand &Root) const;
152 
153   InstructionSelector::ComplexRendererFns
154   selectSmrdImm(MachineOperand &Root) const;
155   InstructionSelector::ComplexRendererFns
156   selectSmrdImm32(MachineOperand &Root) const;
157   InstructionSelector::ComplexRendererFns
158   selectSmrdSgpr(MachineOperand &Root) const;
159 
160   template <bool Signed>
161   InstructionSelector::ComplexRendererFns
162   selectFlatOffsetImpl(MachineOperand &Root) const;
163   InstructionSelector::ComplexRendererFns
164   selectFlatOffset(MachineOperand &Root) const;
165 
166   InstructionSelector::ComplexRendererFns
167   selectFlatOffsetSigned(MachineOperand &Root) const;
168 
169   InstructionSelector::ComplexRendererFns
170   selectMUBUFScratchOffen(MachineOperand &Root) const;
171   InstructionSelector::ComplexRendererFns
172   selectMUBUFScratchOffset(MachineOperand &Root) const;
173 
174   bool isDSOffsetLegal(Register Base, int64_t Offset,
175                        unsigned OffsetBits) const;
176 
177   std::pair<Register, unsigned>
178   selectDS1Addr1OffsetImpl(MachineOperand &Src) const;
179 
180   InstructionSelector::ComplexRendererFns
181   selectDS1Addr1Offset(MachineOperand &Root) const;
182   InstructionSelector::ComplexRendererFns
183   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
184 
185   std::pair<Register, int64_t>
186   getPtrBaseWithConstantOffset(Register Root,
187                                const MachineRegisterInfo &MRI) const;
188 
189   // Parse out a chain of up to two g_ptr_add instructions.
190   // g_ptr_add (n0, _)
191   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
192   struct MUBUFAddressData {
193     Register N0, N2, N3;
194     int64_t Offset = 0;
195   };
196 
197   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
198 
199   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
200                                Register &SOffset, int64_t &ImmOffset) const;
201 
202   MUBUFAddressData parseMUBUFAddress(Register Src) const;
203 
204   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
205                              Register &RSrcReg, Register &SOffset,
206                              int64_t &Offset) const;
207 
208   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
209                              Register &SOffset, int64_t &Offset) const;
210 
211   InstructionSelector::ComplexRendererFns
212   selectMUBUFAddr64(MachineOperand &Root) const;
213 
214   InstructionSelector::ComplexRendererFns
215   selectMUBUFOffset(MachineOperand &Root) const;
216 
217   InstructionSelector::ComplexRendererFns
218   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
219 
220   InstructionSelector::ComplexRendererFns
221   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
222 
223   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
224                         int OpIdx = -1) const;
225 
226   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
227                        int OpIdx) const;
228 
229   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
230                         int OpIdx) const {
231     renderTruncTImm(MIB, MI, OpIdx);
232   }
233 
234   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
235                         int OpIdx) const {
236     renderTruncTImm(MIB, MI, OpIdx);
237   }
238 
239   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
240                         int OpIdx) const {
241     renderTruncTImm(MIB, MI, OpIdx);
242   }
243 
244   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
245                         int OpIdx) const {
246     renderTruncTImm(MIB, MI, OpIdx);
247   }
248 
249   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
250                        int OpIdx) const;
251 
252   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
253                         int OpIdx) const;
254 
255   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
256                        int OpIdx) const;
257   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
258                         int OpIdx) const;
259   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
260                         int OpIdx) const;
261   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
262                         int OpIdx) const;
263   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
264                         int OpIdx) const;
265 
266   bool isInlineImmediate16(int64_t Imm) const;
267   bool isInlineImmediate32(int64_t Imm) const;
268   bool isInlineImmediate64(int64_t Imm) const;
269   bool isInlineImmediate(const APFloat &Imm) const;
270 
271   const SIInstrInfo &TII;
272   const SIRegisterInfo &TRI;
273   const AMDGPURegisterBankInfo &RBI;
274   const AMDGPUTargetMachine &TM;
275   const GCNSubtarget &STI;
276   bool EnableLateStructurizeCFG;
277 #define GET_GLOBALISEL_PREDICATES_DECL
278 #define AMDGPUSubtarget GCNSubtarget
279 #include "AMDGPUGenGlobalISel.inc"
280 #undef GET_GLOBALISEL_PREDICATES_DECL
281 #undef AMDGPUSubtarget
282 
283 #define GET_GLOBALISEL_TEMPORARIES_DECL
284 #include "AMDGPUGenGlobalISel.inc"
285 #undef GET_GLOBALISEL_TEMPORARIES_DECL
286 };
287 
288 } // End llvm namespace.
289 #endif
290