1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 namespace AMDGPU {
35 struct ImageDimIntrinsicInfo;
36 }
37 
38 class AMDGPUInstrInfo;
39 class AMDGPURegisterBankInfo;
40 class GCNSubtarget;
41 class MachineInstr;
42 class MachineIRBuilder;
43 class MachineOperand;
44 class MachineRegisterInfo;
45 class RegisterBank;
46 class SIInstrInfo;
47 class SIMachineFunctionInfo;
48 class SIRegisterInfo;
49 
50 class AMDGPUInstructionSelector : public InstructionSelector {
51 private:
52   MachineRegisterInfo *MRI;
53 
54 public:
55   AMDGPUInstructionSelector(const GCNSubtarget &STI,
56                             const AMDGPURegisterBankInfo &RBI,
57                             const AMDGPUTargetMachine &TM);
58 
59   bool select(MachineInstr &I) override;
60   static const char *getName();
61 
62   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
63                CodeGenCoverage &CoverageInfo) override;
64 
65 private:
66   struct GEPInfo {
67     const MachineInstr &GEP;
68     SmallVector<unsigned, 2> SgprParts;
69     SmallVector<unsigned, 2> VgprParts;
70     int64_t Imm;
71     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
72   };
73 
74   bool isInstrUniform(const MachineInstr &MI) const;
75   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76 
77   const RegisterBank *getArtifactRegBank(
78     Register Reg, const MachineRegisterInfo &MRI,
79     const TargetRegisterInfo &TRI) const;
80 
81   /// tblgen-erated 'select' implementation.
82   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83 
84   MachineOperand getSubOperand64(MachineOperand &MO,
85                                  const TargetRegisterClass &SubRC,
86                                  unsigned SubIdx) const;
87 
88   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89   bool selectCOPY(MachineInstr &I) const;
90   bool selectPHI(MachineInstr &I) const;
91   bool selectG_TRUNC(MachineInstr &I) const;
92   bool selectG_SZA_EXT(MachineInstr &I) const;
93   bool selectG_CONSTANT(MachineInstr &I) const;
94   bool selectG_FNEG(MachineInstr &I) const;
95   bool selectG_AND_OR_XOR(MachineInstr &I) const;
96   bool selectG_ADD_SUB(MachineInstr &I) const;
97   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
98   bool selectG_EXTRACT(MachineInstr &I) const;
99   bool selectG_MERGE_VALUES(MachineInstr &I) const;
100   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
101   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
102   bool selectG_PTR_ADD(MachineInstr &I) const;
103   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
104   bool selectG_INSERT(MachineInstr &I) const;
105 
106   bool selectInterpP1F16(MachineInstr &MI) const;
107   bool selectDivScale(MachineInstr &MI) const;
108   bool selectG_INTRINSIC(MachineInstr &I) const;
109 
110   bool selectEndCfIntrinsic(MachineInstr &MI) const;
111   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
112   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
113   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
114 
115   bool selectImageIntrinsic(MachineInstr &MI,
116                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
117   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
118   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
119   bool selectG_ICMP(MachineInstr &I) const;
120   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
121   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
122                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
123   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
124 
125   void initM0(MachineInstr &I) const;
126   bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
127   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
128   bool selectG_STORE(MachineInstr &I) const;
129   bool selectG_SELECT(MachineInstr &I) const;
130   bool selectG_BRCOND(MachineInstr &I) const;
131   bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const;
132   bool selectG_PTR_MASK(MachineInstr &I) const;
133   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
134   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
135   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
136 
137   std::pair<Register, unsigned>
138   selectVOP3ModsImpl(MachineOperand &Root) const;
139 
140   InstructionSelector::ComplexRendererFns
141   selectVCSRC(MachineOperand &Root) const;
142 
143   InstructionSelector::ComplexRendererFns
144   selectVSRC0(MachineOperand &Root) const;
145 
146   InstructionSelector::ComplexRendererFns
147   selectVOP3Mods0(MachineOperand &Root) const;
148   InstructionSelector::ComplexRendererFns
149   selectVOP3OMods(MachineOperand &Root) const;
150   InstructionSelector::ComplexRendererFns
151   selectVOP3Mods(MachineOperand &Root) const;
152 
153   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
154 
155   InstructionSelector::ComplexRendererFns
156   selectVOP3Mods_nnan(MachineOperand &Root) const;
157 
158   std::pair<Register, unsigned>
159   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
160 
161   InstructionSelector::ComplexRendererFns
162   selectVOP3PMods(MachineOperand &Root) const;
163 
164   InstructionSelector::ComplexRendererFns
165   selectVOP3OpSelMods(MachineOperand &Root) const;
166 
167   InstructionSelector::ComplexRendererFns
168   selectSmrdImm(MachineOperand &Root) const;
169   InstructionSelector::ComplexRendererFns
170   selectSmrdImm32(MachineOperand &Root) const;
171   InstructionSelector::ComplexRendererFns
172   selectSmrdSgpr(MachineOperand &Root) const;
173 
174   template <bool Signed>
175   InstructionSelector::ComplexRendererFns
176   selectFlatOffsetImpl(MachineOperand &Root) const;
177   InstructionSelector::ComplexRendererFns
178   selectFlatOffset(MachineOperand &Root) const;
179 
180   InstructionSelector::ComplexRendererFns
181   selectFlatOffsetSigned(MachineOperand &Root) const;
182 
183   InstructionSelector::ComplexRendererFns
184   selectMUBUFScratchOffen(MachineOperand &Root) const;
185   InstructionSelector::ComplexRendererFns
186   selectMUBUFScratchOffset(MachineOperand &Root) const;
187 
188   bool isDSOffsetLegal(Register Base, int64_t Offset,
189                        unsigned OffsetBits) const;
190 
191   std::pair<Register, unsigned>
192   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
193   InstructionSelector::ComplexRendererFns
194   selectDS1Addr1Offset(MachineOperand &Root) const;
195 
196   std::pair<Register, unsigned>
197   selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const;
198   InstructionSelector::ComplexRendererFns
199   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
200 
201   std::pair<Register, int64_t>
202   getPtrBaseWithConstantOffset(Register Root,
203                                const MachineRegisterInfo &MRI) const;
204 
205   // Parse out a chain of up to two g_ptr_add instructions.
206   // g_ptr_add (n0, _)
207   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
208   struct MUBUFAddressData {
209     Register N0, N2, N3;
210     int64_t Offset = 0;
211   };
212 
213   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
214 
215   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
216                                Register &SOffset, int64_t &ImmOffset) const;
217 
218   MUBUFAddressData parseMUBUFAddress(Register Src) const;
219 
220   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
221                              Register &RSrcReg, Register &SOffset,
222                              int64_t &Offset) const;
223 
224   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
225                              Register &SOffset, int64_t &Offset) const;
226 
227   InstructionSelector::ComplexRendererFns
228   selectMUBUFAddr64(MachineOperand &Root) const;
229 
230   InstructionSelector::ComplexRendererFns
231   selectMUBUFOffset(MachineOperand &Root) const;
232 
233   InstructionSelector::ComplexRendererFns
234   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
235 
236   InstructionSelector::ComplexRendererFns
237   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
238 
239   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
240   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
241 
242   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
243                         int OpIdx = -1) const;
244 
245   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
246                        int OpIdx) const;
247 
248   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
249                         int OpIdx) const {
250     renderTruncTImm(MIB, MI, OpIdx);
251   }
252 
253   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
254                         int OpIdx) const {
255     renderTruncTImm(MIB, MI, OpIdx);
256   }
257 
258   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
259                         int OpIdx) const {
260     renderTruncTImm(MIB, MI, OpIdx);
261   }
262 
263   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
264                         int OpIdx) const {
265     renderTruncTImm(MIB, MI, OpIdx);
266   }
267 
268   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
269                        int OpIdx) const;
270 
271   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
272                         int OpIdx) const;
273 
274   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
275                        int OpIdx) const;
276   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
277                         int OpIdx) const;
278   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
279                         int OpIdx) const;
280   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
281                         int OpIdx) const;
282   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
283                         int OpIdx) const;
284 
285   bool isInlineImmediate16(int64_t Imm) const;
286   bool isInlineImmediate32(int64_t Imm) const;
287   bool isInlineImmediate64(int64_t Imm) const;
288   bool isInlineImmediate(const APFloat &Imm) const;
289 
290   const SIInstrInfo &TII;
291   const SIRegisterInfo &TRI;
292   const AMDGPURegisterBankInfo &RBI;
293   const AMDGPUTargetMachine &TM;
294   const GCNSubtarget &STI;
295   bool EnableLateStructurizeCFG;
296 #define GET_GLOBALISEL_PREDICATES_DECL
297 #define AMDGPUSubtarget GCNSubtarget
298 #include "AMDGPUGenGlobalISel.inc"
299 #undef GET_GLOBALISEL_PREDICATES_DECL
300 #undef AMDGPUSubtarget
301 
302 #define GET_GLOBALISEL_TEMPORARIES_DECL
303 #include "AMDGPUGenGlobalISel.inc"
304 #undef GET_GLOBALISEL_TEMPORARIES_DECL
305 };
306 
307 } // End llvm namespace.
308 #endif
309