1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPUInstrInfo;
34 class AMDGPURegisterBankInfo;
35 class AMDGPUTargetMachine;
36 class BlockFrequencyInfo;
37 class ProfileSummaryInfo;
38 class GCNSubtarget;
39 class MachineInstr;
40 class MachineIRBuilder;
41 class MachineOperand;
42 class MachineRegisterInfo;
43 class RegisterBank;
44 class SIInstrInfo;
45 class SIMachineFunctionInfo;
46 class SIRegisterInfo;
47 class TargetRegisterClass;
48 
49 class AMDGPUInstructionSelector final : public InstructionSelector {
50 private:
51   MachineRegisterInfo *MRI;
52   const GCNSubtarget *Subtarget;
53 
54 public:
55   AMDGPUInstructionSelector(const GCNSubtarget &STI,
56                             const AMDGPURegisterBankInfo &RBI,
57                             const AMDGPUTargetMachine &TM);
58 
59   bool select(MachineInstr &I) override;
60   static const char *getName();
61 
62   void setupMF(MachineFunction &MF, GISelKnownBits *KB,
63                CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
64                BlockFrequencyInfo *BFI) override;
65 
66 private:
67   struct GEPInfo {
68     const MachineInstr &GEP;
69     SmallVector<unsigned, 2> SgprParts;
70     SmallVector<unsigned, 2> VgprParts;
71     int64_t Imm;
72     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
73   };
74 
75   bool isSGPR(Register Reg) const;
76 
77   bool isInstrUniform(const MachineInstr &MI) const;
78   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
79 
80   const RegisterBank *getArtifactRegBank(
81     Register Reg, const MachineRegisterInfo &MRI,
82     const TargetRegisterInfo &TRI) const;
83 
84   /// tblgen-erated 'select' implementation.
85   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
86 
87   MachineOperand getSubOperand64(MachineOperand &MO,
88                                  const TargetRegisterClass &SubRC,
89                                  unsigned SubIdx) const;
90 
91   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
92   bool selectCOPY(MachineInstr &I) const;
93   bool selectPHI(MachineInstr &I) const;
94   bool selectG_TRUNC(MachineInstr &I) const;
95   bool selectG_SZA_EXT(MachineInstr &I) const;
96   bool selectG_CONSTANT(MachineInstr &I) const;
97   bool selectG_FNEG(MachineInstr &I) const;
98   bool selectG_FABS(MachineInstr &I) const;
99   bool selectG_AND_OR_XOR(MachineInstr &I) const;
100   bool selectG_ADD_SUB(MachineInstr &I) const;
101   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102   bool selectG_EXTRACT(MachineInstr &I) const;
103   bool selectG_MERGE_VALUES(MachineInstr &I) const;
104   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
106   bool selectG_PTR_ADD(MachineInstr &I) const;
107   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
108   bool selectG_INSERT(MachineInstr &I) const;
109   bool selectG_SBFX_UBFX(MachineInstr &I) const;
110 
111   bool selectInterpP1F16(MachineInstr &MI) const;
112   bool selectWritelane(MachineInstr &MI) const;
113   bool selectDivScale(MachineInstr &MI) const;
114   bool selectIntrinsicIcmp(MachineInstr &MI) const;
115   bool selectBallot(MachineInstr &I) const;
116   bool selectRelocConstant(MachineInstr &I) const;
117   bool selectGroupStaticSize(MachineInstr &I) const;
118   bool selectReturnAddress(MachineInstr &I) const;
119   bool selectG_INTRINSIC(MachineInstr &I) const;
120 
121   bool selectEndCfIntrinsic(MachineInstr &MI) const;
122   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
125   bool selectSBarrier(MachineInstr &MI) const;
126 
127   bool selectImageIntrinsic(MachineInstr &MI,
128                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
129   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
130   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
131   bool selectG_ICMP(MachineInstr &I) const;
132   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
133   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
134                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
135   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
136 
137   void initM0(MachineInstr &I) const;
138   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
139   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
140   bool selectG_SELECT(MachineInstr &I) const;
141   bool selectG_BRCOND(MachineInstr &I) const;
142   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143   bool selectG_PTRMASK(MachineInstr &I) const;
144   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
147   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
148   bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
149                               MachineOperand &DataOp) const;
150   bool selectBVHIntrinsic(MachineInstr &I) const;
151 
152   std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
153                                                    bool AllowAbs = true) const;
154 
155   InstructionSelector::ComplexRendererFns
156   selectVCSRC(MachineOperand &Root) const;
157 
158   InstructionSelector::ComplexRendererFns
159   selectVSRC0(MachineOperand &Root) const;
160 
161   InstructionSelector::ComplexRendererFns
162   selectVOP3Mods0(MachineOperand &Root) const;
163   InstructionSelector::ComplexRendererFns
164   selectVOP3BMods0(MachineOperand &Root) const;
165   InstructionSelector::ComplexRendererFns
166   selectVOP3OMods(MachineOperand &Root) const;
167   InstructionSelector::ComplexRendererFns
168   selectVOP3Mods(MachineOperand &Root) const;
169   InstructionSelector::ComplexRendererFns
170   selectVOP3BMods(MachineOperand &Root) const;
171 
172   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
173 
174   InstructionSelector::ComplexRendererFns
175   selectVOP3Mods_nnan(MachineOperand &Root) const;
176 
177   std::pair<Register, unsigned>
178   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
179 
180   InstructionSelector::ComplexRendererFns
181   selectVOP3PMods(MachineOperand &Root) const;
182 
183   InstructionSelector::ComplexRendererFns
184   selectVOP3OpSelMods(MachineOperand &Root) const;
185 
186   InstructionSelector::ComplexRendererFns
187   selectSmrdImm(MachineOperand &Root) const;
188   InstructionSelector::ComplexRendererFns
189   selectSmrdImm32(MachineOperand &Root) const;
190   InstructionSelector::ComplexRendererFns
191   selectSmrdSgpr(MachineOperand &Root) const;
192 
193   std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
194                                                 uint64_t FlatVariant) const;
195 
196   InstructionSelector::ComplexRendererFns
197   selectFlatOffset(MachineOperand &Root) const;
198   InstructionSelector::ComplexRendererFns
199   selectGlobalOffset(MachineOperand &Root) const;
200   InstructionSelector::ComplexRendererFns
201   selectScratchOffset(MachineOperand &Root) const;
202 
203   InstructionSelector::ComplexRendererFns
204   selectGlobalSAddr(MachineOperand &Root) const;
205 
206   InstructionSelector::ComplexRendererFns
207   selectScratchSAddr(MachineOperand &Root) const;
208 
209   InstructionSelector::ComplexRendererFns
210   selectMUBUFScratchOffen(MachineOperand &Root) const;
211   InstructionSelector::ComplexRendererFns
212   selectMUBUFScratchOffset(MachineOperand &Root) const;
213 
214   bool isDSOffsetLegal(Register Base, int64_t Offset) const;
215   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
216                         unsigned Size) const;
217 
218   std::pair<Register, unsigned>
219   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
220   InstructionSelector::ComplexRendererFns
221   selectDS1Addr1Offset(MachineOperand &Root) const;
222 
223   InstructionSelector::ComplexRendererFns
224   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
225 
226   InstructionSelector::ComplexRendererFns
227   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
228 
229   std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
230                                                        unsigned size) const;
231   InstructionSelector::ComplexRendererFns
232   selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
233 
234   std::pair<Register, int64_t>
235   getPtrBaseWithConstantOffset(Register Root,
236                                const MachineRegisterInfo &MRI) const;
237 
238   // Parse out a chain of up to two g_ptr_add instructions.
239   // g_ptr_add (n0, _)
240   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
241   struct MUBUFAddressData {
242     Register N0, N2, N3;
243     int64_t Offset = 0;
244   };
245 
246   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
247 
248   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
249                                Register &SOffset, int64_t &ImmOffset) const;
250 
251   MUBUFAddressData parseMUBUFAddress(Register Src) const;
252 
253   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
254                              Register &RSrcReg, Register &SOffset,
255                              int64_t &Offset) const;
256 
257   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
258                              Register &SOffset, int64_t &Offset) const;
259 
260   InstructionSelector::ComplexRendererFns
261   selectMUBUFAddr64(MachineOperand &Root) const;
262 
263   InstructionSelector::ComplexRendererFns
264   selectMUBUFOffset(MachineOperand &Root) const;
265 
266   InstructionSelector::ComplexRendererFns
267   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
268 
269   InstructionSelector::ComplexRendererFns
270   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
271 
272   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
273   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
274 
275   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
276                         int OpIdx = -1) const;
277 
278   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
279                        int OpIdx) const;
280 
281   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
282                        int OpIdx) const;
283 
284   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
285                         int OpIdx) const;
286 
287   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
288                        int OpIdx) const;
289   void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
290                          int OpIdx) const;
291   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
292                         int OpIdx) const;
293   void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
294                     int OpIdx) const;
295 
296   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
297                         int OpIdx) const;
298 
299   bool isInlineImmediate16(int64_t Imm) const;
300   bool isInlineImmediate32(int64_t Imm) const;
301   bool isInlineImmediate64(int64_t Imm) const;
302   bool isInlineImmediate(const APFloat &Imm) const;
303 
304   const SIInstrInfo &TII;
305   const SIRegisterInfo &TRI;
306   const AMDGPURegisterBankInfo &RBI;
307   const AMDGPUTargetMachine &TM;
308   const GCNSubtarget &STI;
309   bool EnableLateStructurizeCFG;
310 #define GET_GLOBALISEL_PREDICATES_DECL
311 #define AMDGPUSubtarget GCNSubtarget
312 #include "AMDGPUGenGlobalISel.inc"
313 #undef GET_GLOBALISEL_PREDICATES_DECL
314 #undef AMDGPUSubtarget
315 
316 #define GET_GLOBALISEL_TEMPORARIES_DECL
317 #include "AMDGPUGenGlobalISel.inc"
318 #undef GET_GLOBALISEL_TEMPORARIES_DECL
319 };
320 
321 } // End llvm namespace.
322 #endif
323