1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPURegisterBankInfo;
34 class AMDGPUTargetMachine;
35 class BlockFrequencyInfo;
36 class ProfileSummaryInfo;
37 class GCNSubtarget;
38 class MachineInstr;
39 class MachineIRBuilder;
40 class MachineOperand;
41 class MachineRegisterInfo;
42 class RegisterBank;
43 class SIInstrInfo;
44 class SIRegisterInfo;
45 class TargetRegisterClass;
46 
47 class AMDGPUInstructionSelector final : public InstructionSelector {
48 private:
49   MachineRegisterInfo *MRI;
50   const GCNSubtarget *Subtarget;
51 
52 public:
53   AMDGPUInstructionSelector(const GCNSubtarget &STI,
54                             const AMDGPURegisterBankInfo &RBI,
55                             const AMDGPUTargetMachine &TM);
56 
57   bool select(MachineInstr &I) override;
58   static const char *getName();
59 
60   void setupMF(MachineFunction &MF, GISelKnownBits *KB,
61                CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
62                BlockFrequencyInfo *BFI) override;
63 
64 private:
65   struct GEPInfo {
66     const MachineInstr &GEP;
67     SmallVector<unsigned, 2> SgprParts;
68     SmallVector<unsigned, 2> VgprParts;
69     int64_t Imm;
70     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
71   };
72 
73   bool isSGPR(Register Reg) const;
74 
75   bool isInstrUniform(const MachineInstr &MI) const;
76   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 
78   const RegisterBank *getArtifactRegBank(
79     Register Reg, const MachineRegisterInfo &MRI,
80     const TargetRegisterInfo &TRI) const;
81 
82   /// tblgen-erated 'select' implementation.
83   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
84 
85   MachineOperand getSubOperand64(MachineOperand &MO,
86                                  const TargetRegisterClass &SubRC,
87                                  unsigned SubIdx) const;
88 
89   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
90   bool selectCOPY(MachineInstr &I) const;
91   bool selectPHI(MachineInstr &I) const;
92   bool selectG_TRUNC(MachineInstr &I) const;
93   bool selectG_SZA_EXT(MachineInstr &I) const;
94   bool selectG_CONSTANT(MachineInstr &I) const;
95   bool selectG_FNEG(MachineInstr &I) const;
96   bool selectG_FABS(MachineInstr &I) const;
97   bool selectG_AND_OR_XOR(MachineInstr &I) const;
98   bool selectG_ADD_SUB(MachineInstr &I) const;
99   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100   bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
101   bool selectG_EXTRACT(MachineInstr &I) const;
102   bool selectG_MERGE_VALUES(MachineInstr &I) const;
103   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
104   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
105   bool selectG_PTR_ADD(MachineInstr &I) const;
106   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
107   bool selectG_INSERT(MachineInstr &I) const;
108   bool selectG_SBFX_UBFX(MachineInstr &I) const;
109 
110   bool selectInterpP1F16(MachineInstr &MI) const;
111   bool selectWritelane(MachineInstr &MI) const;
112   bool selectDivScale(MachineInstr &MI) const;
113   bool selectIntrinsicIcmp(MachineInstr &MI) const;
114   bool selectBallot(MachineInstr &I) const;
115   bool selectRelocConstant(MachineInstr &I) const;
116   bool selectGroupStaticSize(MachineInstr &I) const;
117   bool selectReturnAddress(MachineInstr &I) const;
118   bool selectG_INTRINSIC(MachineInstr &I) const;
119 
120   bool selectEndCfIntrinsic(MachineInstr &MI) const;
121   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
124   bool selectSBarrier(MachineInstr &MI) const;
125 
126   bool selectImageIntrinsic(MachineInstr &MI,
127                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
128   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
129   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
130   bool selectG_ICMP(MachineInstr &I) const;
131   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
132   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
133                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
134 
135   void initM0(MachineInstr &I) const;
136   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
137   bool selectG_SELECT(MachineInstr &I) const;
138   bool selectG_BRCOND(MachineInstr &I) const;
139   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
140   bool selectG_PTRMASK(MachineInstr &I) const;
141   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
142   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
143   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
144   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
145   bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
146                               MachineOperand &DataOp) const;
147   bool selectBufferLoadLds(MachineInstr &MI) const;
148   bool selectGlobalLoadLds(MachineInstr &MI) const;
149   bool selectBVHIntrinsic(MachineInstr &I) const;
150   bool selectSMFMACIntrin(MachineInstr &I) const;
151   bool selectWaveAddress(MachineInstr &I) const;
152 
153   std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
154                                                    bool AllowAbs = true) const;
155 
156   InstructionSelector::ComplexRendererFns
157   selectVCSRC(MachineOperand &Root) const;
158 
159   InstructionSelector::ComplexRendererFns
160   selectVSRC0(MachineOperand &Root) const;
161 
162   InstructionSelector::ComplexRendererFns
163   selectVOP3Mods0(MachineOperand &Root) const;
164   InstructionSelector::ComplexRendererFns
165   selectVOP3BMods0(MachineOperand &Root) const;
166   InstructionSelector::ComplexRendererFns
167   selectVOP3OMods(MachineOperand &Root) const;
168   InstructionSelector::ComplexRendererFns
169   selectVOP3Mods(MachineOperand &Root) const;
170   InstructionSelector::ComplexRendererFns
171   selectVOP3BMods(MachineOperand &Root) const;
172 
173   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
174 
175   InstructionSelector::ComplexRendererFns
176   selectVOP3Mods_nnan(MachineOperand &Root) const;
177 
178   std::pair<Register, unsigned>
179   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
180                       bool IsDOT = false) const;
181 
182   InstructionSelector::ComplexRendererFns
183   selectVOP3PMods(MachineOperand &Root) const;
184 
185   InstructionSelector::ComplexRendererFns
186   selectVOP3PModsDOT(MachineOperand &Root) const;
187 
188   InstructionSelector::ComplexRendererFns
189   selectDotIUVOP3PMods(MachineOperand &Root) const;
190 
191   InstructionSelector::ComplexRendererFns
192   selectVOP3OpSelMods(MachineOperand &Root) const;
193 
194   InstructionSelector::ComplexRendererFns
195   selectSmrdImm(MachineOperand &Root) const;
196   InstructionSelector::ComplexRendererFns
197   selectSmrdImm32(MachineOperand &Root) const;
198   InstructionSelector::ComplexRendererFns
199   selectSmrdSgpr(MachineOperand &Root) const;
200 
201   std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
202                                                 uint64_t FlatVariant) const;
203 
204   InstructionSelector::ComplexRendererFns
205   selectFlatOffset(MachineOperand &Root) const;
206   InstructionSelector::ComplexRendererFns
207   selectGlobalOffset(MachineOperand &Root) const;
208   InstructionSelector::ComplexRendererFns
209   selectScratchOffset(MachineOperand &Root) const;
210 
211   InstructionSelector::ComplexRendererFns
212   selectGlobalSAddr(MachineOperand &Root) const;
213 
214   InstructionSelector::ComplexRendererFns
215   selectScratchSAddr(MachineOperand &Root) const;
216   bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
217                                      uint64_t ImmOffset) const;
218   InstructionSelector::ComplexRendererFns
219   selectScratchSVAddr(MachineOperand &Root) const;
220 
221   InstructionSelector::ComplexRendererFns
222   selectMUBUFScratchOffen(MachineOperand &Root) const;
223   InstructionSelector::ComplexRendererFns
224   selectMUBUFScratchOffset(MachineOperand &Root) const;
225 
226   bool isDSOffsetLegal(Register Base, int64_t Offset) const;
227   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
228                         unsigned Size) const;
229 
230   std::pair<Register, unsigned>
231   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
232   InstructionSelector::ComplexRendererFns
233   selectDS1Addr1Offset(MachineOperand &Root) const;
234 
235   InstructionSelector::ComplexRendererFns
236   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
237 
238   InstructionSelector::ComplexRendererFns
239   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
240 
241   std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
242                                                        unsigned size) const;
243   InstructionSelector::ComplexRendererFns
244   selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
245 
246   std::pair<Register, int64_t>
247   getPtrBaseWithConstantOffset(Register Root,
248                                const MachineRegisterInfo &MRI) const;
249 
250   // Parse out a chain of up to two g_ptr_add instructions.
251   // g_ptr_add (n0, _)
252   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
253   struct MUBUFAddressData {
254     Register N0, N2, N3;
255     int64_t Offset = 0;
256   };
257 
258   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
259 
260   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
261                                Register &SOffset, int64_t &ImmOffset) const;
262 
263   MUBUFAddressData parseMUBUFAddress(Register Src) const;
264 
265   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
266                              Register &RSrcReg, Register &SOffset,
267                              int64_t &Offset) const;
268 
269   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
270                              Register &SOffset, int64_t &Offset) const;
271 
272   InstructionSelector::ComplexRendererFns
273   selectMUBUFAddr64(MachineOperand &Root) const;
274 
275   InstructionSelector::ComplexRendererFns
276   selectMUBUFOffset(MachineOperand &Root) const;
277 
278   InstructionSelector::ComplexRendererFns
279   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
280 
281   InstructionSelector::ComplexRendererFns
282   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
283 
284   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
285   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
286 
287   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
288                         int OpIdx = -1) const;
289 
290   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
291                        int OpIdx) const;
292 
293   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
294                        int OpIdx) const;
295 
296   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
297                         int OpIdx) const;
298 
299   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
300                        int OpIdx) const;
301   void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
302                          int OpIdx) const;
303   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
304                         int OpIdx) const;
305   void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
306                     int OpIdx) const;
307 
308   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
309                         int OpIdx) const;
310 
311   bool isInlineImmediate16(int64_t Imm) const;
312   bool isInlineImmediate32(int64_t Imm) const;
313   bool isInlineImmediate64(int64_t Imm) const;
314   bool isInlineImmediate(const APFloat &Imm) const;
315 
316   // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
317   // shift amount operand's `ShAmtBits` bits is unneeded.
318   bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
319 
320   const SIInstrInfo &TII;
321   const SIRegisterInfo &TRI;
322   const AMDGPURegisterBankInfo &RBI;
323   const AMDGPUTargetMachine &TM;
324   const GCNSubtarget &STI;
325   bool EnableLateStructurizeCFG;
326 #define GET_GLOBALISEL_PREDICATES_DECL
327 #define AMDGPUSubtarget GCNSubtarget
328 #include "AMDGPUGenGlobalISel.inc"
329 #undef GET_GLOBALISEL_PREDICATES_DECL
330 #undef AMDGPUSubtarget
331 
332 #define GET_GLOBALISEL_TEMPORARIES_DECL
333 #include "AMDGPUGenGlobalISel.inc"
334 #undef GET_GLOBALISEL_TEMPORARIES_DECL
335 };
336 
337 } // End llvm namespace.
338 #endif
339