1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "AMDGPU.h" 17 #include "AMDGPUArgumentUsageInfo.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/Register.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/IR/InstrTypes.h" 23 24 namespace { 25 #define GET_GLOBALISEL_PREDICATE_BITSET 26 #define AMDGPUSubtarget GCNSubtarget 27 #include "AMDGPUGenGlobalISel.inc" 28 #undef GET_GLOBALISEL_PREDICATE_BITSET 29 #undef AMDGPUSubtarget 30 } 31 32 namespace llvm { 33 34 class AMDGPUInstrInfo; 35 class AMDGPURegisterBankInfo; 36 class GCNSubtarget; 37 class MachineInstr; 38 class MachineOperand; 39 class MachineRegisterInfo; 40 class SIInstrInfo; 41 class SIMachineFunctionInfo; 42 class SIRegisterInfo; 43 44 class AMDGPUInstructionSelector : public InstructionSelector { 45 public: 46 AMDGPUInstructionSelector(const GCNSubtarget &STI, 47 const AMDGPURegisterBankInfo &RBI, 48 const AMDGPUTargetMachine &TM); 49 50 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override; 51 static const char *getName(); 52 53 private: 54 struct GEPInfo { 55 const MachineInstr &GEP; 56 SmallVector<unsigned, 2> SgprParts; 57 SmallVector<unsigned, 2> VgprParts; 58 int64_t Imm; 59 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } 60 }; 61 62 bool isInstrUniform(const MachineInstr &MI) const; 63 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 64 65 /// tblgen-erated 'select' implementation. 66 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 67 68 MachineOperand getSubOperand64(MachineOperand &MO, 69 const TargetRegisterClass &SubRC, 70 unsigned SubIdx) const; 71 bool selectCOPY(MachineInstr &I) const; 72 bool selectPHI(MachineInstr &I) const; 73 bool selectG_TRUNC(MachineInstr &I) const; 74 bool selectG_SZA_EXT(MachineInstr &I) const; 75 bool selectG_CONSTANT(MachineInstr &I) const; 76 bool selectG_AND_OR_XOR(MachineInstr &I) const; 77 bool selectG_ADD_SUB(MachineInstr &I) const; 78 bool selectG_EXTRACT(MachineInstr &I) const; 79 bool selectG_MERGE_VALUES(MachineInstr &I) const; 80 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 81 bool selectG_GEP(MachineInstr &I) const; 82 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 83 bool selectG_INSERT(MachineInstr &I) const; 84 bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 85 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I, 86 CodeGenCoverage &CoverageInfo) const; 87 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 88 bool selectG_ICMP(MachineInstr &I) const; 89 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 90 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 91 SmallVectorImpl<GEPInfo> &AddrInfo) const; 92 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; 93 94 void initM0(MachineInstr &I) const; 95 bool selectG_LOAD_ATOMICRMW(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 96 bool selectG_STORE(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 97 bool selectG_SELECT(MachineInstr &I) const; 98 bool selectG_BRCOND(MachineInstr &I) const; 99 bool selectG_FRAME_INDEX(MachineInstr &I) const; 100 101 std::pair<Register, unsigned> 102 selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const; 103 104 InstructionSelector::ComplexRendererFns 105 selectVCSRC(MachineOperand &Root) const; 106 107 InstructionSelector::ComplexRendererFns 108 selectVSRC0(MachineOperand &Root) const; 109 110 InstructionSelector::ComplexRendererFns 111 selectVOP3Mods0(MachineOperand &Root) const; 112 InstructionSelector::ComplexRendererFns 113 selectVOP3OMods(MachineOperand &Root) const; 114 InstructionSelector::ComplexRendererFns 115 selectVOP3Mods(MachineOperand &Root) const; 116 117 InstructionSelector::ComplexRendererFns 118 selectSmrdImm(MachineOperand &Root) const; 119 InstructionSelector::ComplexRendererFns 120 selectSmrdImm32(MachineOperand &Root) const; 121 InstructionSelector::ComplexRendererFns 122 selectSmrdSgpr(MachineOperand &Root) const; 123 124 template <bool Signed> 125 InstructionSelector::ComplexRendererFns 126 selectFlatOffsetImpl(MachineOperand &Root) const; 127 InstructionSelector::ComplexRendererFns 128 selectFlatOffset(MachineOperand &Root) const; 129 130 InstructionSelector::ComplexRendererFns 131 selectFlatOffsetSigned(MachineOperand &Root) const; 132 133 InstructionSelector::ComplexRendererFns 134 selectMUBUFScratchOffen(MachineOperand &Root) const; 135 InstructionSelector::ComplexRendererFns 136 selectMUBUFScratchOffset(MachineOperand &Root) const; 137 138 bool isDSOffsetLegal(const MachineRegisterInfo &MRI, 139 const MachineOperand &Base, 140 int64_t Offset, unsigned OffsetBits) const; 141 142 InstructionSelector::ComplexRendererFns 143 selectDS1Addr1Offset(MachineOperand &Root) const; 144 145 const SIInstrInfo &TII; 146 const SIRegisterInfo &TRI; 147 const AMDGPURegisterBankInfo &RBI; 148 const AMDGPUTargetMachine &TM; 149 const GCNSubtarget &STI; 150 bool EnableLateStructurizeCFG; 151 #define GET_GLOBALISEL_PREDICATES_DECL 152 #define AMDGPUSubtarget GCNSubtarget 153 #include "AMDGPUGenGlobalISel.inc" 154 #undef GET_GLOBALISEL_PREDICATES_DECL 155 #undef AMDGPUSubtarget 156 157 #define GET_GLOBALISEL_TEMPORARIES_DECL 158 #include "AMDGPUGenGlobalISel.inc" 159 #undef GET_GLOBALISEL_TEMPORARIES_DECL 160 }; 161 162 } // End llvm namespace. 163 #endif 164