1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the InstructionSelector class for
11 /// AMDGPU.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
16 
17 #include "AMDGPU.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21 
22 namespace {
23 #define GET_GLOBALISEL_PREDICATE_BITSET
24 #include "AMDGPUGenGlobalISel.inc"
25 #undef GET_GLOBALISEL_PREDICATE_BITSET
26 }
27 
28 namespace llvm {
29 
30 class AMDGPUInstrInfo;
31 class AMDGPURegisterBankInfo;
32 class AMDGPUSubtarget;
33 class MachineInstr;
34 class MachineOperand;
35 class MachineRegisterInfo;
36 class SIInstrInfo;
37 class SIRegisterInfo;
38 class SISubtarget;
39 
40 class AMDGPUInstructionSelector : public InstructionSelector {
41 public:
42   AMDGPUInstructionSelector(const SISubtarget &STI,
43                             const AMDGPURegisterBankInfo &RBI,
44                             const AMDGPUTargetMachine &TM);
45 
46   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
47   static const char *getName();
48 
49 private:
50   struct GEPInfo {
51     const MachineInstr &GEP;
52     SmallVector<unsigned, 2> SgprParts;
53     SmallVector<unsigned, 2> VgprParts;
54     int64_t Imm;
55     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
56   };
57 
58   /// tblgen-erated 'select' implementation.
59   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
60 
61   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
62   bool selectCOPY(MachineInstr &I) const;
63   bool selectG_CONSTANT(MachineInstr &I) const;
64   bool selectG_ADD(MachineInstr &I) const;
65   bool selectG_GEP(MachineInstr &I) const;
66   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
67   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
68                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
69   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
70   bool selectG_LOAD(MachineInstr &I) const;
71   bool selectG_STORE(MachineInstr &I) const;
72 
73   InstructionSelector::ComplexRendererFns
74   selectVSRC0(MachineOperand &Root) const;
75 
76   const SIInstrInfo &TII;
77   const SIRegisterInfo &TRI;
78   const AMDGPURegisterBankInfo &RBI;
79   const AMDGPUTargetMachine &TM;
80   const SISubtarget &STI;
81   bool EnableLateStructurizeCFG;
82 #define GET_GLOBALISEL_PREDICATES_DECL
83 #include "AMDGPUGenGlobalISel.inc"
84 #undef GET_GLOBALISEL_PREDICATES_DECL
85 
86 #define GET_GLOBALISEL_TEMPORARIES_DECL
87 #include "AMDGPUGenGlobalISel.inc"
88 #undef GET_GLOBALISEL_TEMPORARIES_DECL
89 
90 protected:
91   AMDGPUAS AMDGPUASI;
92 };
93 
94 } // End llvm namespace.
95 #endif
96