1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21 
22 namespace {
23 #define GET_GLOBALISEL_PREDICATE_BITSET
24 #define AMDGPUSubtarget GCNSubtarget
25 #include "AMDGPUGenGlobalISel.inc"
26 #undef GET_GLOBALISEL_PREDICATE_BITSET
27 #undef AMDGPUSubtarget
28 }
29 
30 namespace llvm {
31 
32 class AMDGPUInstrInfo;
33 class AMDGPURegisterBankInfo;
34 class GCNSubtarget;
35 class MachineInstr;
36 class MachineOperand;
37 class MachineRegisterInfo;
38 class SIInstrInfo;
39 class SIMachineFunctionInfo;
40 class SIRegisterInfo;
41 
42 class AMDGPUInstructionSelector : public InstructionSelector {
43 public:
44   AMDGPUInstructionSelector(const GCNSubtarget &STI,
45                             const AMDGPURegisterBankInfo &RBI,
46                             const AMDGPUTargetMachine &TM);
47 
48   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
49   static const char *getName();
50 
51 private:
52   struct GEPInfo {
53     const MachineInstr &GEP;
54     SmallVector<unsigned, 2> SgprParts;
55     SmallVector<unsigned, 2> VgprParts;
56     int64_t Imm;
57     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
58   };
59 
60   bool isInstrUniform(const MachineInstr &MI) const;
61   /// tblgen-erated 'select' implementation.
62   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
63 
64   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
65   bool selectCOPY(MachineInstr &I) const;
66   bool selectG_TRUNC(MachineInstr &I) const;
67   bool selectG_CONSTANT(MachineInstr &I) const;
68   bool selectG_ADD(MachineInstr &I) const;
69   bool selectG_EXTRACT(MachineInstr &I) const;
70   bool selectG_GEP(MachineInstr &I) const;
71   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
72   bool selectG_INSERT(MachineInstr &I) const;
73   bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
74   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
75                                         CodeGenCoverage &CoverageInfo) const;
76   bool selectG_ICMP(MachineInstr &I) const;
77   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
78   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
79                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
80   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
81   bool selectG_LOAD(MachineInstr &I) const;
82   bool selectG_SELECT(MachineInstr &I) const;
83   bool selectG_STORE(MachineInstr &I) const;
84 
85   InstructionSelector::ComplexRendererFns
86   selectVCSRC(MachineOperand &Root) const;
87 
88   InstructionSelector::ComplexRendererFns
89   selectVSRC0(MachineOperand &Root) const;
90 
91   InstructionSelector::ComplexRendererFns
92   selectVOP3Mods0(MachineOperand &Root) const;
93   InstructionSelector::ComplexRendererFns
94   selectVOP3OMods(MachineOperand &Root) const;
95   InstructionSelector::ComplexRendererFns
96   selectVOP3Mods(MachineOperand &Root) const;
97 
98   InstructionSelector::ComplexRendererFns
99   selectSmrdImm(MachineOperand &Root) const;
100   InstructionSelector::ComplexRendererFns
101   selectSmrdImm32(MachineOperand &Root) const;
102   InstructionSelector::ComplexRendererFns
103   selectSmrdSgpr(MachineOperand &Root) const;
104 
105   const SIInstrInfo &TII;
106   const SIRegisterInfo &TRI;
107   const AMDGPURegisterBankInfo &RBI;
108   const AMDGPUTargetMachine &TM;
109   const GCNSubtarget &STI;
110   bool EnableLateStructurizeCFG;
111 #define GET_GLOBALISEL_PREDICATES_DECL
112 #define AMDGPUSubtarget GCNSubtarget
113 #include "AMDGPUGenGlobalISel.inc"
114 #undef GET_GLOBALISEL_PREDICATES_DECL
115 #undef AMDGPUSubtarget
116 
117 #define GET_GLOBALISEL_TEMPORARIES_DECL
118 #include "AMDGPUGenGlobalISel.inc"
119 #undef GET_GLOBALISEL_TEMPORARIES_DECL
120 };
121 
122 } // End llvm namespace.
123 #endif
124