1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the InstructionSelector class for 10 /// AMDGPU. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H 15 16 #include "AMDGPU.h" 17 #include "AMDGPUArgumentUsageInfo.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/Register.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/IR/InstrTypes.h" 23 24 namespace { 25 #define GET_GLOBALISEL_PREDICATE_BITSET 26 #define AMDGPUSubtarget GCNSubtarget 27 #include "AMDGPUGenGlobalISel.inc" 28 #undef GET_GLOBALISEL_PREDICATE_BITSET 29 #undef AMDGPUSubtarget 30 } 31 32 namespace llvm { 33 34 namespace AMDGPU { 35 struct ImageDimIntrinsicInfo; 36 } 37 38 class AMDGPUInstrInfo; 39 class AMDGPURegisterBankInfo; 40 class GCNSubtarget; 41 class MachineInstr; 42 class MachineIRBuilder; 43 class MachineOperand; 44 class MachineRegisterInfo; 45 class RegisterBank; 46 class SIInstrInfo; 47 class SIMachineFunctionInfo; 48 class SIRegisterInfo; 49 50 class AMDGPUInstructionSelector final : public InstructionSelector { 51 private: 52 MachineRegisterInfo *MRI; 53 54 public: 55 AMDGPUInstructionSelector(const GCNSubtarget &STI, 56 const AMDGPURegisterBankInfo &RBI, 57 const AMDGPUTargetMachine &TM); 58 59 bool select(MachineInstr &I) override; 60 static const char *getName(); 61 62 void setupMF(MachineFunction &MF, GISelKnownBits &KB, 63 CodeGenCoverage &CoverageInfo) override; 64 65 private: 66 struct GEPInfo { 67 const MachineInstr &GEP; 68 SmallVector<unsigned, 2> SgprParts; 69 SmallVector<unsigned, 2> VgprParts; 70 int64_t Imm; 71 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } 72 }; 73 74 bool isInstrUniform(const MachineInstr &MI) const; 75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; 76 77 const RegisterBank *getArtifactRegBank( 78 Register Reg, const MachineRegisterInfo &MRI, 79 const TargetRegisterInfo &TRI) const; 80 81 /// tblgen-erated 'select' implementation. 82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; 83 84 MachineOperand getSubOperand64(MachineOperand &MO, 85 const TargetRegisterClass &SubRC, 86 unsigned SubIdx) const; 87 88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const; 89 bool selectCOPY(MachineInstr &I) const; 90 bool selectPHI(MachineInstr &I) const; 91 bool selectG_TRUNC(MachineInstr &I) const; 92 bool selectG_SZA_EXT(MachineInstr &I) const; 93 bool selectG_CONSTANT(MachineInstr &I) const; 94 bool selectG_FNEG(MachineInstr &I) const; 95 bool selectG_FABS(MachineInstr &I) const; 96 bool selectG_AND_OR_XOR(MachineInstr &I) const; 97 bool selectG_ADD_SUB(MachineInstr &I) const; 98 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const; 99 bool selectG_EXTRACT(MachineInstr &I) const; 100 bool selectG_MERGE_VALUES(MachineInstr &I) const; 101 bool selectG_UNMERGE_VALUES(MachineInstr &I) const; 102 bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const; 103 bool selectG_PTR_ADD(MachineInstr &I) const; 104 bool selectG_IMPLICIT_DEF(MachineInstr &I) const; 105 bool selectG_INSERT(MachineInstr &I) const; 106 107 bool selectInterpP1F16(MachineInstr &MI) const; 108 bool selectDivScale(MachineInstr &MI) const; 109 bool selectIntrinsicIcmp(MachineInstr &MI) const; 110 bool selectBallot(MachineInstr &I) const; 111 bool selectRelocConstant(MachineInstr &I) const; 112 bool selectG_INTRINSIC(MachineInstr &I) const; 113 114 bool selectEndCfIntrinsic(MachineInstr &MI) const; 115 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 116 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; 117 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const; 118 119 bool selectImageIntrinsic(MachineInstr &MI, 120 const AMDGPU::ImageDimIntrinsicInfo *Intr) const; 121 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const; 122 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; 123 bool selectG_ICMP(MachineInstr &I) const; 124 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; 125 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, 126 SmallVectorImpl<GEPInfo> &AddrInfo) const; 127 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; 128 129 void initM0(MachineInstr &I) const; 130 bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const; 131 bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const; 132 bool selectG_STORE(MachineInstr &I) const; 133 bool selectG_SELECT(MachineInstr &I) const; 134 bool selectG_BRCOND(MachineInstr &I) const; 135 bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const; 136 bool selectG_PTRMASK(MachineInstr &I) const; 137 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const; 138 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const; 139 bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const; 140 141 std::pair<Register, unsigned> 142 selectVOP3ModsImpl(MachineOperand &Root) const; 143 144 InstructionSelector::ComplexRendererFns 145 selectVCSRC(MachineOperand &Root) const; 146 147 InstructionSelector::ComplexRendererFns 148 selectVSRC0(MachineOperand &Root) const; 149 150 InstructionSelector::ComplexRendererFns 151 selectVOP3Mods0(MachineOperand &Root) const; 152 InstructionSelector::ComplexRendererFns 153 selectVOP3OMods(MachineOperand &Root) const; 154 InstructionSelector::ComplexRendererFns 155 selectVOP3Mods(MachineOperand &Root) const; 156 157 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const; 158 159 InstructionSelector::ComplexRendererFns 160 selectVOP3Mods_nnan(MachineOperand &Root) const; 161 162 std::pair<Register, unsigned> 163 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const; 164 165 InstructionSelector::ComplexRendererFns 166 selectVOP3PMods(MachineOperand &Root) const; 167 168 InstructionSelector::ComplexRendererFns 169 selectVOP3OpSelMods(MachineOperand &Root) const; 170 171 InstructionSelector::ComplexRendererFns 172 selectSmrdImm(MachineOperand &Root) const; 173 InstructionSelector::ComplexRendererFns 174 selectSmrdImm32(MachineOperand &Root) const; 175 InstructionSelector::ComplexRendererFns 176 selectSmrdSgpr(MachineOperand &Root) const; 177 178 template <bool Signed> 179 InstructionSelector::ComplexRendererFns 180 selectFlatOffsetImpl(MachineOperand &Root) const; 181 InstructionSelector::ComplexRendererFns 182 selectFlatOffset(MachineOperand &Root) const; 183 184 InstructionSelector::ComplexRendererFns 185 selectFlatOffsetSigned(MachineOperand &Root) const; 186 187 InstructionSelector::ComplexRendererFns 188 selectMUBUFScratchOffen(MachineOperand &Root) const; 189 InstructionSelector::ComplexRendererFns 190 selectMUBUFScratchOffset(MachineOperand &Root) const; 191 192 bool isDSOffsetLegal(Register Base, int64_t Offset, 193 unsigned OffsetBits) const; 194 195 std::pair<Register, unsigned> 196 selectDS1Addr1OffsetImpl(MachineOperand &Root) const; 197 InstructionSelector::ComplexRendererFns 198 selectDS1Addr1Offset(MachineOperand &Root) const; 199 200 std::pair<Register, unsigned> 201 selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const; 202 InstructionSelector::ComplexRendererFns 203 selectDS64Bit4ByteAligned(MachineOperand &Root) const; 204 205 std::pair<Register, int64_t> 206 getPtrBaseWithConstantOffset(Register Root, 207 const MachineRegisterInfo &MRI) const; 208 209 // Parse out a chain of up to two g_ptr_add instructions. 210 // g_ptr_add (n0, _) 211 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3)) 212 struct MUBUFAddressData { 213 Register N0, N2, N3; 214 int64_t Offset = 0; 215 }; 216 217 bool shouldUseAddr64(MUBUFAddressData AddrData) const; 218 219 void splitIllegalMUBUFOffset(MachineIRBuilder &B, 220 Register &SOffset, int64_t &ImmOffset) const; 221 222 MUBUFAddressData parseMUBUFAddress(Register Src) const; 223 224 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr, 225 Register &RSrcReg, Register &SOffset, 226 int64_t &Offset) const; 227 228 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg, 229 Register &SOffset, int64_t &Offset) const; 230 231 InstructionSelector::ComplexRendererFns 232 selectMUBUFAddr64(MachineOperand &Root) const; 233 234 InstructionSelector::ComplexRendererFns 235 selectMUBUFOffset(MachineOperand &Root) const; 236 237 InstructionSelector::ComplexRendererFns 238 selectMUBUFOffsetAtomic(MachineOperand &Root) const; 239 240 InstructionSelector::ComplexRendererFns 241 selectMUBUFAddr64Atomic(MachineOperand &Root) const; 242 243 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const; 244 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const; 245 246 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, 247 int OpIdx = -1) const; 248 249 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 250 int OpIdx) const; 251 252 void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI, 253 int OpIdx) const { 254 renderTruncTImm(MIB, MI, OpIdx); 255 } 256 257 void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI, 258 int OpIdx) const { 259 renderTruncTImm(MIB, MI, OpIdx); 260 } 261 262 void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI, 263 int OpIdx) const { 264 renderTruncTImm(MIB, MI, OpIdx); 265 } 266 267 void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, 268 int OpIdx) const { 269 renderTruncTImm(MIB, MI, OpIdx); 270 } 271 272 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 273 int OpIdx) const; 274 275 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 276 int OpIdx) const; 277 278 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, 279 int OpIdx) const; 280 void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 281 int OpIdx) const; 282 void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 283 int OpIdx) const; 284 void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI, 285 int OpIdx) const; 286 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI, 287 int OpIdx) const; 288 289 bool isInlineImmediate16(int64_t Imm) const; 290 bool isInlineImmediate32(int64_t Imm) const; 291 bool isInlineImmediate64(int64_t Imm) const; 292 bool isInlineImmediate(const APFloat &Imm) const; 293 294 const SIInstrInfo &TII; 295 const SIRegisterInfo &TRI; 296 const AMDGPURegisterBankInfo &RBI; 297 const AMDGPUTargetMachine &TM; 298 const GCNSubtarget &STI; 299 bool EnableLateStructurizeCFG; 300 #define GET_GLOBALISEL_PREDICATES_DECL 301 #define AMDGPUSubtarget GCNSubtarget 302 #include "AMDGPUGenGlobalISel.inc" 303 #undef GET_GLOBALISEL_PREDICATES_DECL 304 #undef AMDGPUSubtarget 305 306 #define GET_GLOBALISEL_TEMPORARIES_DECL 307 #include "AMDGPUGenGlobalISel.inc" 308 #undef GET_GLOBALISEL_TEMPORARIES_DECL 309 }; 310 311 } // End llvm namespace. 312 #endif 313