1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUArgumentUsageInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 class AMDGPUInstrInfo;
35 class AMDGPURegisterBankInfo;
36 class GCNSubtarget;
37 class MachineInstr;
38 class MachineIRBuilder;
39 class MachineOperand;
40 class MachineRegisterInfo;
41 class RegisterBank;
42 class SIInstrInfo;
43 class SIMachineFunctionInfo;
44 class SIRegisterInfo;
45 
46 class AMDGPUInstructionSelector : public InstructionSelector {
47 private:
48   MachineRegisterInfo *MRI;
49 
50 public:
51   AMDGPUInstructionSelector(const GCNSubtarget &STI,
52                             const AMDGPURegisterBankInfo &RBI,
53                             const AMDGPUTargetMachine &TM);
54 
55   bool select(MachineInstr &I) override;
56   static const char *getName();
57 
58   void setupMF(MachineFunction &MF, GISelKnownBits &KB,
59                CodeGenCoverage &CoverageInfo) override;
60 
61 private:
62   struct GEPInfo {
63     const MachineInstr &GEP;
64     SmallVector<unsigned, 2> SgprParts;
65     SmallVector<unsigned, 2> VgprParts;
66     int64_t Imm;
67     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
68   };
69 
70   bool isInstrUniform(const MachineInstr &MI) const;
71   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
72 
73   const RegisterBank *getArtifactRegBank(
74     Register Reg, const MachineRegisterInfo &MRI,
75     const TargetRegisterInfo &TRI) const;
76 
77   /// tblgen-erated 'select' implementation.
78   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
79 
80   MachineOperand getSubOperand64(MachineOperand &MO,
81                                  const TargetRegisterClass &SubRC,
82                                  unsigned SubIdx) const;
83 
84   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
85   bool selectCOPY(MachineInstr &I) const;
86   bool selectPHI(MachineInstr &I) const;
87   bool selectG_TRUNC(MachineInstr &I) const;
88   bool selectG_SZA_EXT(MachineInstr &I) const;
89   bool selectG_CONSTANT(MachineInstr &I) const;
90   bool selectG_FNEG(MachineInstr &I) const;
91   bool selectG_AND_OR_XOR(MachineInstr &I) const;
92   bool selectG_ADD_SUB(MachineInstr &I) const;
93   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
94   bool selectG_EXTRACT(MachineInstr &I) const;
95   bool selectG_MERGE_VALUES(MachineInstr &I) const;
96   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
97   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
98   bool selectG_PTR_ADD(MachineInstr &I) const;
99   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
100   bool selectG_INSERT(MachineInstr &I) const;
101 
102   bool selectInterpP1F16(MachineInstr &MI) const;
103   bool selectG_INTRINSIC(MachineInstr &I) const;
104 
105   bool selectEndCfIntrinsic(MachineInstr &MI) const;
106   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
107   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
108   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
109 
110   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
111   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
112   bool selectG_ICMP(MachineInstr &I) const;
113   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
114   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
115                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
116   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
117 
118   void initM0(MachineInstr &I) const;
119   bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
120   bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
121   bool selectG_STORE(MachineInstr &I) const;
122   bool selectG_SELECT(MachineInstr &I) const;
123   bool selectG_BRCOND(MachineInstr &I) const;
124   bool selectG_FRAME_INDEX_GLOBAL_VALUE(MachineInstr &I) const;
125   bool selectG_PTR_MASK(MachineInstr &I) const;
126   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
127   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
128   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
129 
130   std::pair<Register, unsigned>
131   selectVOP3ModsImpl(MachineOperand &Root) const;
132 
133   InstructionSelector::ComplexRendererFns
134   selectVCSRC(MachineOperand &Root) const;
135 
136   InstructionSelector::ComplexRendererFns
137   selectVSRC0(MachineOperand &Root) const;
138 
139   InstructionSelector::ComplexRendererFns
140   selectVOP3Mods0(MachineOperand &Root) const;
141   InstructionSelector::ComplexRendererFns
142   selectVOP3OMods(MachineOperand &Root) const;
143   InstructionSelector::ComplexRendererFns
144   selectVOP3Mods(MachineOperand &Root) const;
145 
146   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
147 
148   InstructionSelector::ComplexRendererFns
149   selectVOP3Mods_nnan(MachineOperand &Root) const;
150 
151   std::pair<Register, unsigned>
152   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
153 
154   InstructionSelector::ComplexRendererFns
155   selectVOP3PMods(MachineOperand &Root) const;
156 
157   InstructionSelector::ComplexRendererFns
158   selectVOP3OpSelMods(MachineOperand &Root) const;
159 
160   InstructionSelector::ComplexRendererFns
161   selectSmrdImm(MachineOperand &Root) const;
162   InstructionSelector::ComplexRendererFns
163   selectSmrdImm32(MachineOperand &Root) const;
164   InstructionSelector::ComplexRendererFns
165   selectSmrdSgpr(MachineOperand &Root) const;
166 
167   template <bool Signed>
168   InstructionSelector::ComplexRendererFns
169   selectFlatOffsetImpl(MachineOperand &Root) const;
170   InstructionSelector::ComplexRendererFns
171   selectFlatOffset(MachineOperand &Root) const;
172 
173   InstructionSelector::ComplexRendererFns
174   selectFlatOffsetSigned(MachineOperand &Root) const;
175 
176   InstructionSelector::ComplexRendererFns
177   selectMUBUFScratchOffen(MachineOperand &Root) const;
178   InstructionSelector::ComplexRendererFns
179   selectMUBUFScratchOffset(MachineOperand &Root) const;
180 
181   bool isDSOffsetLegal(Register Base, int64_t Offset,
182                        unsigned OffsetBits) const;
183 
184   std::pair<Register, unsigned>
185   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
186   InstructionSelector::ComplexRendererFns
187   selectDS1Addr1Offset(MachineOperand &Root) const;
188 
189   std::pair<Register, unsigned>
190   selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const;
191   InstructionSelector::ComplexRendererFns
192   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
193 
194   std::pair<Register, int64_t>
195   getPtrBaseWithConstantOffset(Register Root,
196                                const MachineRegisterInfo &MRI) const;
197 
198   // Parse out a chain of up to two g_ptr_add instructions.
199   // g_ptr_add (n0, _)
200   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
201   struct MUBUFAddressData {
202     Register N0, N2, N3;
203     int64_t Offset = 0;
204   };
205 
206   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
207 
208   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
209                                Register &SOffset, int64_t &ImmOffset) const;
210 
211   MUBUFAddressData parseMUBUFAddress(Register Src) const;
212 
213   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
214                              Register &RSrcReg, Register &SOffset,
215                              int64_t &Offset) const;
216 
217   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
218                              Register &SOffset, int64_t &Offset) const;
219 
220   InstructionSelector::ComplexRendererFns
221   selectMUBUFAddr64(MachineOperand &Root) const;
222 
223   InstructionSelector::ComplexRendererFns
224   selectMUBUFOffset(MachineOperand &Root) const;
225 
226   InstructionSelector::ComplexRendererFns
227   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
228 
229   InstructionSelector::ComplexRendererFns
230   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
231 
232   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
233   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
234 
235   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
236                         int OpIdx = -1) const;
237 
238   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
239                        int OpIdx) const;
240 
241   void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI,
242                         int OpIdx) const {
243     renderTruncTImm(MIB, MI, OpIdx);
244   }
245 
246   void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI,
247                         int OpIdx) const {
248     renderTruncTImm(MIB, MI, OpIdx);
249   }
250 
251   void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI,
252                         int OpIdx) const {
253     renderTruncTImm(MIB, MI, OpIdx);
254   }
255 
256   void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
257                         int OpIdx) const {
258     renderTruncTImm(MIB, MI, OpIdx);
259   }
260 
261   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
262                        int OpIdx) const;
263 
264   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
265                         int OpIdx) const;
266 
267   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
268                        int OpIdx) const;
269   void renderExtractGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
270                         int OpIdx) const;
271   void renderExtractSLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
272                         int OpIdx) const;
273   void renderExtractDLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
274                         int OpIdx) const;
275   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
276                         int OpIdx) const;
277 
278   bool isInlineImmediate16(int64_t Imm) const;
279   bool isInlineImmediate32(int64_t Imm) const;
280   bool isInlineImmediate64(int64_t Imm) const;
281   bool isInlineImmediate(const APFloat &Imm) const;
282 
283   const SIInstrInfo &TII;
284   const SIRegisterInfo &TRI;
285   const AMDGPURegisterBankInfo &RBI;
286   const AMDGPUTargetMachine &TM;
287   const GCNSubtarget &STI;
288   bool EnableLateStructurizeCFG;
289 #define GET_GLOBALISEL_PREDICATES_DECL
290 #define AMDGPUSubtarget GCNSubtarget
291 #include "AMDGPUGenGlobalISel.inc"
292 #undef GET_GLOBALISEL_PREDICATES_DECL
293 #undef AMDGPUSubtarget
294 
295 #define GET_GLOBALISEL_TEMPORARIES_DECL
296 #include "AMDGPUGenGlobalISel.inc"
297 #undef GET_GLOBALISEL_TEMPORARIES_DECL
298 };
299 
300 } // End llvm namespace.
301 #endif
302