1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPURegisterBankInfo;
34 class AMDGPUTargetMachine;
35 class BlockFrequencyInfo;
36 class ProfileSummaryInfo;
37 class GCNSubtarget;
38 class MachineInstr;
39 class MachineIRBuilder;
40 class MachineOperand;
41 class MachineRegisterInfo;
42 class RegisterBank;
43 class SIInstrInfo;
44 class SIRegisterInfo;
45 class TargetRegisterClass;
46 
47 class AMDGPUInstructionSelector final : public InstructionSelector {
48 private:
49   MachineRegisterInfo *MRI;
50   const GCNSubtarget *Subtarget;
51 
52 public:
53   AMDGPUInstructionSelector(const GCNSubtarget &STI,
54                             const AMDGPURegisterBankInfo &RBI,
55                             const AMDGPUTargetMachine &TM);
56 
57   bool select(MachineInstr &I) override;
58   static const char *getName();
59 
60   void setupMF(MachineFunction &MF, GISelKnownBits *KB,
61                CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
62                BlockFrequencyInfo *BFI) override;
63 
64 private:
65   struct GEPInfo {
66     const MachineInstr &GEP;
67     SmallVector<unsigned, 2> SgprParts;
68     SmallVector<unsigned, 2> VgprParts;
69     int64_t Imm;
70     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
71   };
72 
73   bool isSGPR(Register Reg) const;
74 
75   bool isInstrUniform(const MachineInstr &MI) const;
76   bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
77 
78   const RegisterBank *getArtifactRegBank(
79     Register Reg, const MachineRegisterInfo &MRI,
80     const TargetRegisterInfo &TRI) const;
81 
82   /// tblgen-erated 'select' implementation.
83   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
84 
85   MachineOperand getSubOperand64(MachineOperand &MO,
86                                  const TargetRegisterClass &SubRC,
87                                  unsigned SubIdx) const;
88 
89   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
90   bool selectCOPY(MachineInstr &I) const;
91   bool selectPHI(MachineInstr &I) const;
92   bool selectG_TRUNC(MachineInstr &I) const;
93   bool selectG_SZA_EXT(MachineInstr &I) const;
94   bool selectG_CONSTANT(MachineInstr &I) const;
95   bool selectG_FNEG(MachineInstr &I) const;
96   bool selectG_FABS(MachineInstr &I) const;
97   bool selectG_AND_OR_XOR(MachineInstr &I) const;
98   bool selectG_ADD_SUB(MachineInstr &I) const;
99   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100   bool selectG_EXTRACT(MachineInstr &I) const;
101   bool selectG_MERGE_VALUES(MachineInstr &I) const;
102   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
103   bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
104   bool selectG_PTR_ADD(MachineInstr &I) const;
105   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
106   bool selectG_INSERT(MachineInstr &I) const;
107   bool selectG_SBFX_UBFX(MachineInstr &I) const;
108 
109   bool selectInterpP1F16(MachineInstr &MI) const;
110   bool selectWritelane(MachineInstr &MI) const;
111   bool selectDivScale(MachineInstr &MI) const;
112   bool selectIntrinsicIcmp(MachineInstr &MI) const;
113   bool selectBallot(MachineInstr &I) const;
114   bool selectRelocConstant(MachineInstr &I) const;
115   bool selectGroupStaticSize(MachineInstr &I) const;
116   bool selectReturnAddress(MachineInstr &I) const;
117   bool selectG_INTRINSIC(MachineInstr &I) const;
118 
119   bool selectEndCfIntrinsic(MachineInstr &MI) const;
120   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
121   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
123   bool selectSBarrier(MachineInstr &MI) const;
124 
125   bool selectImageIntrinsic(MachineInstr &MI,
126                             const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
127   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
128   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
129   bool selectG_ICMP(MachineInstr &I) const;
130   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
131   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
132                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
133 
134   void initM0(MachineInstr &I) const;
135   bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
136   bool selectG_SELECT(MachineInstr &I) const;
137   bool selectG_BRCOND(MachineInstr &I) const;
138   bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
139   bool selectG_PTRMASK(MachineInstr &I) const;
140   bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
141   bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
142   bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
143   bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
144   bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
145                               MachineOperand &DataOp) const;
146   bool selectBVHIntrinsic(MachineInstr &I) const;
147   bool selectWaveAddress(MachineInstr &I) const;
148 
149   std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
150                                                    bool AllowAbs = true) const;
151 
152   InstructionSelector::ComplexRendererFns
153   selectVCSRC(MachineOperand &Root) const;
154 
155   InstructionSelector::ComplexRendererFns
156   selectVSRC0(MachineOperand &Root) const;
157 
158   InstructionSelector::ComplexRendererFns
159   selectVOP3Mods0(MachineOperand &Root) const;
160   InstructionSelector::ComplexRendererFns
161   selectVOP3BMods0(MachineOperand &Root) const;
162   InstructionSelector::ComplexRendererFns
163   selectVOP3OMods(MachineOperand &Root) const;
164   InstructionSelector::ComplexRendererFns
165   selectVOP3Mods(MachineOperand &Root) const;
166   InstructionSelector::ComplexRendererFns
167   selectVOP3BMods(MachineOperand &Root) const;
168 
169   ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
170 
171   InstructionSelector::ComplexRendererFns
172   selectVOP3Mods_nnan(MachineOperand &Root) const;
173 
174   std::pair<Register, unsigned>
175   selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
176                       bool IsDOT = false) const;
177 
178   InstructionSelector::ComplexRendererFns
179   selectVOP3PMods(MachineOperand &Root) const;
180 
181   InstructionSelector::ComplexRendererFns
182   selectVOP3PModsDOT(MachineOperand &Root) const;
183 
184   InstructionSelector::ComplexRendererFns
185   selectVOP3OpSelMods(MachineOperand &Root) const;
186 
187   InstructionSelector::ComplexRendererFns
188   selectSmrdImm(MachineOperand &Root) const;
189   InstructionSelector::ComplexRendererFns
190   selectSmrdImm32(MachineOperand &Root) const;
191   InstructionSelector::ComplexRendererFns
192   selectSmrdSgpr(MachineOperand &Root) const;
193 
194   std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
195                                                 uint64_t FlatVariant) const;
196 
197   InstructionSelector::ComplexRendererFns
198   selectFlatOffset(MachineOperand &Root) const;
199   InstructionSelector::ComplexRendererFns
200   selectGlobalOffset(MachineOperand &Root) const;
201   InstructionSelector::ComplexRendererFns
202   selectScratchOffset(MachineOperand &Root) const;
203 
204   InstructionSelector::ComplexRendererFns
205   selectGlobalSAddr(MachineOperand &Root) const;
206 
207   InstructionSelector::ComplexRendererFns
208   selectScratchSAddr(MachineOperand &Root) const;
209   InstructionSelector::ComplexRendererFns
210   selectScratchSVAddr(MachineOperand &Root) const;
211 
212   InstructionSelector::ComplexRendererFns
213   selectMUBUFScratchOffen(MachineOperand &Root) const;
214   InstructionSelector::ComplexRendererFns
215   selectMUBUFScratchOffset(MachineOperand &Root) const;
216 
217   bool isDSOffsetLegal(Register Base, int64_t Offset) const;
218   bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
219                         unsigned Size) const;
220 
221   std::pair<Register, unsigned>
222   selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
223   InstructionSelector::ComplexRendererFns
224   selectDS1Addr1Offset(MachineOperand &Root) const;
225 
226   InstructionSelector::ComplexRendererFns
227   selectDS64Bit4ByteAligned(MachineOperand &Root) const;
228 
229   InstructionSelector::ComplexRendererFns
230   selectDS128Bit8ByteAligned(MachineOperand &Root) const;
231 
232   std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
233                                                        unsigned size) const;
234   InstructionSelector::ComplexRendererFns
235   selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
236 
237   std::pair<Register, int64_t>
238   getPtrBaseWithConstantOffset(Register Root,
239                                const MachineRegisterInfo &MRI) const;
240 
241   // Parse out a chain of up to two g_ptr_add instructions.
242   // g_ptr_add (n0, _)
243   // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
244   struct MUBUFAddressData {
245     Register N0, N2, N3;
246     int64_t Offset = 0;
247   };
248 
249   bool shouldUseAddr64(MUBUFAddressData AddrData) const;
250 
251   void splitIllegalMUBUFOffset(MachineIRBuilder &B,
252                                Register &SOffset, int64_t &ImmOffset) const;
253 
254   MUBUFAddressData parseMUBUFAddress(Register Src) const;
255 
256   bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
257                              Register &RSrcReg, Register &SOffset,
258                              int64_t &Offset) const;
259 
260   bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
261                              Register &SOffset, int64_t &Offset) const;
262 
263   InstructionSelector::ComplexRendererFns
264   selectMUBUFAddr64(MachineOperand &Root) const;
265 
266   InstructionSelector::ComplexRendererFns
267   selectMUBUFOffset(MachineOperand &Root) const;
268 
269   InstructionSelector::ComplexRendererFns
270   selectMUBUFOffsetAtomic(MachineOperand &Root) const;
271 
272   InstructionSelector::ComplexRendererFns
273   selectMUBUFAddr64Atomic(MachineOperand &Root) const;
274 
275   ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
276   ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
277 
278   void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
279                         int OpIdx = -1) const;
280 
281   void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
282                        int OpIdx) const;
283 
284   void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
285                        int OpIdx) const;
286 
287   void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
288                         int OpIdx) const;
289 
290   void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
291                        int OpIdx) const;
292   void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
293                          int OpIdx) const;
294   void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
295                         int OpIdx) const;
296   void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
297                     int OpIdx) const;
298 
299   void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
300                         int OpIdx) const;
301 
302   bool isInlineImmediate16(int64_t Imm) const;
303   bool isInlineImmediate32(int64_t Imm) const;
304   bool isInlineImmediate64(int64_t Imm) const;
305   bool isInlineImmediate(const APFloat &Imm) const;
306 
307   // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
308   // shift amount operand's `ShAmtBits` bits is unneeded.
309   bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
310 
311   const SIInstrInfo &TII;
312   const SIRegisterInfo &TRI;
313   const AMDGPURegisterBankInfo &RBI;
314   const AMDGPUTargetMachine &TM;
315   const GCNSubtarget &STI;
316   bool EnableLateStructurizeCFG;
317 #define GET_GLOBALISEL_PREDICATES_DECL
318 #define AMDGPUSubtarget GCNSubtarget
319 #include "AMDGPUGenGlobalISel.inc"
320 #undef GET_GLOBALISEL_PREDICATES_DECL
321 #undef AMDGPUSubtarget
322 
323 #define GET_GLOBALISEL_TEMPORARIES_DECL
324 #include "AMDGPUGenGlobalISel.inc"
325 #undef GET_GLOBALISEL_TEMPORARIES_DECL
326 };
327 
328 } // End llvm namespace.
329 #endif
330