1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUInstructionSelector.h"
15 #include "AMDGPUInstrInfo.h"
16 #include "AMDGPURegisterBankInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 
34 #define DEBUG_TYPE "amdgpu-isel"
35 
36 using namespace llvm;
37 
38 #define GET_GLOBALISEL_IMPL
39 #define AMDGPUSubtarget GCNSubtarget
40 #include "AMDGPUGenGlobalISel.inc"
41 #undef GET_GLOBALISEL_IMPL
42 #undef AMDGPUSubtarget
43 
44 AMDGPUInstructionSelector::AMDGPUInstructionSelector(
45     const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI,
46     const AMDGPUTargetMachine &TM)
47     : InstructionSelector(), TII(*STI.getInstrInfo()),
48       TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
49       STI(STI),
50       EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
51 #define GET_GLOBALISEL_PREDICATES_INIT
52 #include "AMDGPUGenGlobalISel.inc"
53 #undef GET_GLOBALISEL_PREDICATES_INIT
54 #define GET_GLOBALISEL_TEMPORARIES_INIT
55 #include "AMDGPUGenGlobalISel.inc"
56 #undef GET_GLOBALISEL_TEMPORARIES_INIT
57 {
58 }
59 
60 const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
61 
62 bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
63   MachineBasicBlock *BB = I.getParent();
64   MachineFunction *MF = BB->getParent();
65   MachineRegisterInfo &MRI = MF->getRegInfo();
66   I.setDesc(TII.get(TargetOpcode::COPY));
67   for (const MachineOperand &MO : I.operands()) {
68     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
69       continue;
70 
71     const TargetRegisterClass *RC =
72             TRI.getConstrainedRegClassForOperand(MO, MRI);
73     if (!RC)
74       continue;
75     RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
76   }
77   return true;
78 }
79 
80 MachineOperand
81 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
82                                            unsigned SubIdx) const {
83 
84   MachineInstr *MI = MO.getParent();
85   MachineBasicBlock *BB = MO.getParent()->getParent();
86   MachineFunction *MF = BB->getParent();
87   MachineRegisterInfo &MRI = MF->getRegInfo();
88   unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
89 
90   if (MO.isReg()) {
91     unsigned ComposedSubIdx = TRI.composeSubRegIndices(MO.getSubReg(), SubIdx);
92     unsigned Reg = MO.getReg();
93     BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
94             .addReg(Reg, 0, ComposedSubIdx);
95 
96     return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
97                                      MO.isKill(), MO.isDead(), MO.isUndef(),
98                                      MO.isEarlyClobber(), 0, MO.isDebug(),
99                                      MO.isInternalRead());
100   }
101 
102   assert(MO.isImm());
103 
104   APInt Imm(64, MO.getImm());
105 
106   switch (SubIdx) {
107   default:
108     llvm_unreachable("do not know to split immediate with this sub index.");
109   case AMDGPU::sub0:
110     return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
111   case AMDGPU::sub1:
112     return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
113   }
114 }
115 
116 static int64_t getConstant(const MachineInstr *MI) {
117   return MI->getOperand(1).getCImm()->getSExtValue();
118 }
119 
120 bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
121   MachineBasicBlock *BB = I.getParent();
122   MachineFunction *MF = BB->getParent();
123   MachineRegisterInfo &MRI = MF->getRegInfo();
124   unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
125   unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
126   unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
127 
128   if (Size != 64)
129     return false;
130 
131   DebugLoc DL = I.getDebugLoc();
132 
133   MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
134   MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
135 
136   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
137           .add(Lo1)
138           .add(Lo2);
139 
140   MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
141   MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
142 
143   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
144           .add(Hi1)
145           .add(Hi2);
146 
147   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
148           .addReg(DstLo)
149           .addImm(AMDGPU::sub0)
150           .addReg(DstHi)
151           .addImm(AMDGPU::sub1);
152 
153   for (MachineOperand &MO : I.explicit_operands()) {
154     if (!MO.isReg() || TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
155       continue;
156     RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);
157   }
158 
159   I.eraseFromParent();
160   return true;
161 }
162 
163 bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
164   MachineBasicBlock *BB = I.getParent();
165   MachineFunction *MF = BB->getParent();
166   MachineRegisterInfo &MRI = MF->getRegInfo();
167   assert(I.getOperand(2).getImm() % 32 == 0);
168   unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(2).getImm() / 32);
169   const DebugLoc &DL = I.getDebugLoc();
170   MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
171                                I.getOperand(0).getReg())
172                                .addReg(I.getOperand(1).getReg(), 0, SubReg);
173 
174   for (const MachineOperand &MO : Copy->operands()) {
175     const TargetRegisterClass *RC =
176             TRI.getConstrainedRegClassForOperand(MO, MRI);
177     if (!RC)
178       continue;
179     RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
180   }
181   I.eraseFromParent();
182   return true;
183 }
184 
185 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
186   return selectG_ADD(I);
187 }
188 
189 bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
190   MachineBasicBlock *BB = I.getParent();
191   MachineFunction *MF = BB->getParent();
192   MachineRegisterInfo &MRI = MF->getRegInfo();
193   const MachineOperand &MO = I.getOperand(0);
194   const TargetRegisterClass *RC =
195       TRI.getConstrainedRegClassForOperand(MO, MRI);
196   if (RC)
197     RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
198   I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
199   return true;
200 }
201 
202 bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
203   MachineBasicBlock *BB = I.getParent();
204   MachineFunction *MF = BB->getParent();
205   MachineRegisterInfo &MRI = MF->getRegInfo();
206   unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32);
207   DebugLoc DL = I.getDebugLoc();
208   MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG))
209                                .addDef(I.getOperand(0).getReg())
210                                .addReg(I.getOperand(1).getReg())
211                                .addReg(I.getOperand(2).getReg())
212                                .addImm(SubReg);
213 
214   for (const MachineOperand &MO : Ins->operands()) {
215     if (!MO.isReg())
216       continue;
217     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
218       continue;
219 
220     const TargetRegisterClass *RC =
221             TRI.getConstrainedRegClassForOperand(MO, MRI);
222     if (!RC)
223       continue;
224     RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
225   }
226   I.eraseFromParent();
227   return true;
228 }
229 
230 bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
231                                           CodeGenCoverage &CoverageInfo) const {
232   unsigned IntrinsicID =  I.getOperand(1).getIntrinsicID();
233 
234   switch (IntrinsicID) {
235   default:
236     break;
237   case Intrinsic::maxnum:
238   case Intrinsic::minnum:
239   case Intrinsic::amdgcn_cvt_pkrtz:
240     return selectImpl(I, CoverageInfo);
241 
242   case Intrinsic::amdgcn_kernarg_segment_ptr: {
243     MachineFunction *MF = I.getParent()->getParent();
244     MachineRegisterInfo &MRI = MF->getRegInfo();
245     const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
246     const ArgDescriptor *InputPtrReg;
247     const TargetRegisterClass *RC;
248     const DebugLoc &DL = I.getDebugLoc();
249 
250     std::tie(InputPtrReg, RC)
251       = MFI->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
252     if (!InputPtrReg)
253       report_fatal_error("missing kernarg segment ptr");
254 
255     BuildMI(*I.getParent(), &I, DL, TII.get(AMDGPU::COPY))
256       .add(I.getOperand(0))
257       .addReg(MRI.getLiveInVirtReg(InputPtrReg->getRegister()));
258     I.eraseFromParent();
259     return true;
260   }
261   }
262   return false;
263 }
264 
265 static MachineInstr *
266 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
267          unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3,
268          unsigned VM, bool Compr, unsigned Enabled, bool Done) {
269   const DebugLoc &DL = Insert->getDebugLoc();
270   MachineBasicBlock &BB = *Insert->getParent();
271   unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP;
272   return BuildMI(BB, Insert, DL, TII.get(Opcode))
273           .addImm(Tgt)
274           .addReg(Reg0)
275           .addReg(Reg1)
276           .addReg(Reg2)
277           .addReg(Reg3)
278           .addImm(VM)
279           .addImm(Compr)
280           .addImm(Enabled);
281 }
282 
283 bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
284                                                  MachineInstr &I,
285 						 CodeGenCoverage &CoverageInfo) const {
286   MachineBasicBlock *BB = I.getParent();
287   MachineFunction *MF = BB->getParent();
288   MachineRegisterInfo &MRI = MF->getRegInfo();
289 
290   unsigned IntrinsicID = I.getOperand(0).getIntrinsicID();
291   switch (IntrinsicID) {
292   case Intrinsic::amdgcn_exp: {
293     int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg()));
294     int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg()));
295     int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(7).getReg()));
296     int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(8).getReg()));
297 
298     MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(),
299                                  I.getOperand(4).getReg(),
300                                  I.getOperand(5).getReg(),
301                                  I.getOperand(6).getReg(),
302                                  VM, false, Enabled, Done);
303 
304     I.eraseFromParent();
305     return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
306   }
307   case Intrinsic::amdgcn_exp_compr: {
308     const DebugLoc &DL = I.getDebugLoc();
309     int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg()));
310     int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg()));
311     unsigned Reg0 = I.getOperand(3).getReg();
312     unsigned Reg1 = I.getOperand(4).getReg();
313     unsigned Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
314     int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(5).getReg()));
315     int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(6).getReg()));
316 
317     BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);
318     MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM,
319                                  true,  Enabled, Done);
320 
321     I.eraseFromParent();
322     return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
323   }
324   }
325   return false;
326 }
327 
328 bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
329   MachineBasicBlock *BB = I.getParent();
330   MachineFunction *MF = BB->getParent();
331   MachineRegisterInfo &MRI = MF->getRegInfo();
332   DebugLoc DL = I.getDebugLoc();
333   unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
334   unsigned Opcode;
335 
336   // FIXME: Select store instruction based on address space
337   switch (StoreSize) {
338   default:
339     return false;
340   case 32:
341     Opcode = AMDGPU::FLAT_STORE_DWORD;
342     break;
343   case 64:
344     Opcode = AMDGPU::FLAT_STORE_DWORDX2;
345     break;
346   case 96:
347     Opcode = AMDGPU::FLAT_STORE_DWORDX3;
348     break;
349   case 128:
350     Opcode = AMDGPU::FLAT_STORE_DWORDX4;
351     break;
352   }
353 
354   MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
355           .add(I.getOperand(1))
356           .add(I.getOperand(0))
357           .addImm(0)  // offset
358           .addImm(0)  // glc
359           .addImm(0)  // slc
360           .addImm(0); // dlc
361 
362 
363   // Now that we selected an opcode, we need to constrain the register
364   // operands to use appropriate classes.
365   bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
366 
367   I.eraseFromParent();
368   return Ret;
369 }
370 
371 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
372   MachineBasicBlock *BB = I.getParent();
373   MachineFunction *MF = BB->getParent();
374   MachineRegisterInfo &MRI = MF->getRegInfo();
375   MachineOperand &ImmOp = I.getOperand(1);
376 
377   // The AMDGPU backend only supports Imm operands and not CImm or FPImm.
378   if (ImmOp.isFPImm()) {
379     const APInt &Imm = ImmOp.getFPImm()->getValueAPF().bitcastToAPInt();
380     ImmOp.ChangeToImmediate(Imm.getZExtValue());
381   } else if (ImmOp.isCImm()) {
382     ImmOp.ChangeToImmediate(ImmOp.getCImm()->getZExtValue());
383   }
384 
385   unsigned DstReg = I.getOperand(0).getReg();
386   unsigned Size;
387   bool IsSgpr;
388   const RegisterBank *RB = MRI.getRegBankOrNull(I.getOperand(0).getReg());
389   if (RB) {
390     IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;
391     Size = MRI.getType(DstReg).getSizeInBits();
392   } else {
393     const TargetRegisterClass *RC = TRI.getRegClassForReg(MRI, DstReg);
394     IsSgpr = TRI.isSGPRClass(RC);
395     Size = TRI.getRegSizeInBits(*RC);
396   }
397 
398   if (Size != 32 && Size != 64)
399     return false;
400 
401   unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
402   if (Size == 32) {
403     I.setDesc(TII.get(Opcode));
404     I.addImplicitDefUseOperands(*MF);
405     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
406   }
407 
408   DebugLoc DL = I.getDebugLoc();
409   const TargetRegisterClass *RC = IsSgpr ? &AMDGPU::SReg_32_XM0RegClass :
410                                            &AMDGPU::VGPR_32RegClass;
411   unsigned LoReg = MRI.createVirtualRegister(RC);
412   unsigned HiReg = MRI.createVirtualRegister(RC);
413   const APInt &Imm = APInt(Size, I.getOperand(1).getImm());
414 
415   BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
416           .addImm(Imm.trunc(32).getZExtValue());
417 
418   BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
419           .addImm(Imm.ashr(32).getZExtValue());
420 
421   const MachineInstr *RS =
422       BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
423               .addReg(LoReg)
424               .addImm(AMDGPU::sub0)
425               .addReg(HiReg)
426               .addImm(AMDGPU::sub1);
427 
428   // We can't call constrainSelectedInstRegOperands here, because it doesn't
429   // work for target independent opcodes
430   I.eraseFromParent();
431   const TargetRegisterClass *DstRC =
432       TRI.getConstrainedRegClassForOperand(RS->getOperand(0), MRI);
433   if (!DstRC)
434     return true;
435   return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
436 }
437 
438 static bool isConstant(const MachineInstr &MI) {
439   return MI.getOpcode() == TargetOpcode::G_CONSTANT;
440 }
441 
442 void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
443     const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
444 
445   const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
446 
447   assert(PtrMI);
448 
449   if (PtrMI->getOpcode() != TargetOpcode::G_GEP)
450     return;
451 
452   GEPInfo GEPInfo(*PtrMI);
453 
454   for (unsigned i = 1, e = 3; i < e; ++i) {
455     const MachineOperand &GEPOp = PtrMI->getOperand(i);
456     const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
457     assert(OpDef);
458     if (isConstant(*OpDef)) {
459       // FIXME: Is it possible to have multiple Imm parts?  Maybe if we
460       // are lacking other optimizations.
461       assert(GEPInfo.Imm == 0);
462       GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
463       continue;
464     }
465     const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
466     if (OpBank->getID() == AMDGPU::SGPRRegBankID)
467       GEPInfo.SgprParts.push_back(GEPOp.getReg());
468     else
469       GEPInfo.VgprParts.push_back(GEPOp.getReg());
470   }
471 
472   AddrInfo.push_back(GEPInfo);
473   getAddrModeInfo(*PtrMI, MRI, AddrInfo);
474 }
475 
476 bool AMDGPUInstructionSelector::isInstrUniform(const MachineInstr &MI) const {
477   if (!MI.hasOneMemOperand())
478     return false;
479 
480   const MachineMemOperand *MMO = *MI.memoperands_begin();
481   const Value *Ptr = MMO->getValue();
482 
483   // UndefValue means this is a load of a kernel input.  These are uniform.
484   // Sometimes LDS instructions have constant pointers.
485   // If Ptr is null, then that means this mem operand contains a
486   // PseudoSourceValue like GOT.
487   if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
488       isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
489     return true;
490 
491   if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
492     return true;
493 
494   const Instruction *I = dyn_cast<Instruction>(Ptr);
495   return I && I->getMetadata("amdgpu.uniform");
496 }
497 
498 bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
499   for (const GEPInfo &GEPInfo : AddrInfo) {
500     if (!GEPInfo.VgprParts.empty())
501       return true;
502   }
503   return false;
504 }
505 
506 bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
507   MachineBasicBlock *BB = I.getParent();
508   MachineFunction *MF = BB->getParent();
509   MachineRegisterInfo &MRI = MF->getRegInfo();
510   DebugLoc DL = I.getDebugLoc();
511   unsigned DstReg = I.getOperand(0).getReg();
512   unsigned PtrReg = I.getOperand(1).getReg();
513   unsigned LoadSize = RBI.getSizeInBits(DstReg, MRI, TRI);
514   unsigned Opcode;
515 
516   SmallVector<GEPInfo, 4> AddrInfo;
517 
518   getAddrModeInfo(I, MRI, AddrInfo);
519 
520   switch (LoadSize) {
521   default:
522     llvm_unreachable("Load size not supported\n");
523   case 32:
524     Opcode = AMDGPU::FLAT_LOAD_DWORD;
525     break;
526   case 64:
527     Opcode = AMDGPU::FLAT_LOAD_DWORDX2;
528     break;
529   }
530 
531   MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode))
532                                .add(I.getOperand(0))
533                                .addReg(PtrReg)
534                                .addImm(0)  // offset
535                                .addImm(0)  // glc
536                                .addImm(0)  // slc
537                                .addImm(0); // dlc
538 
539   bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
540   I.eraseFromParent();
541   return Ret;
542 }
543 
544 bool AMDGPUInstructionSelector::select(MachineInstr &I,
545                                        CodeGenCoverage &CoverageInfo) const {
546 
547   if (!isPreISelGenericOpcode(I.getOpcode())) {
548     if (I.isCopy())
549       return selectCOPY(I);
550     return true;
551   }
552 
553   switch (I.getOpcode()) {
554   default:
555     return selectImpl(I, CoverageInfo);
556   case TargetOpcode::G_ADD:
557     return selectG_ADD(I);
558   case TargetOpcode::G_INTTOPTR:
559   case TargetOpcode::G_BITCAST:
560     return selectCOPY(I);
561   case TargetOpcode::G_CONSTANT:
562   case TargetOpcode::G_FCONSTANT:
563     return selectG_CONSTANT(I);
564   case TargetOpcode::G_EXTRACT:
565     return selectG_EXTRACT(I);
566   case TargetOpcode::G_GEP:
567     return selectG_GEP(I);
568   case TargetOpcode::G_IMPLICIT_DEF:
569     return selectG_IMPLICIT_DEF(I);
570   case TargetOpcode::G_INSERT:
571     return selectG_INSERT(I);
572   case TargetOpcode::G_INTRINSIC:
573     return selectG_INTRINSIC(I, CoverageInfo);
574   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
575     return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo);
576   case TargetOpcode::G_LOAD:
577     if (selectImpl(I, CoverageInfo))
578       return true;
579     return selectG_LOAD(I);
580   case TargetOpcode::G_STORE:
581     return selectG_STORE(I);
582   }
583   return false;
584 }
585 
586 InstructionSelector::ComplexRendererFns
587 AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
588   return {{
589       [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
590   }};
591 
592 }
593 
594 ///
595 /// This will select either an SGPR or VGPR operand and will save us from
596 /// having to write an extra tablegen pattern.
597 InstructionSelector::ComplexRendererFns
598 AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const {
599   return {{
600       [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
601   }};
602 }
603 
604 InstructionSelector::ComplexRendererFns
605 AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
606   return {{
607       [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
608       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
609       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
610       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }  // omod
611   }};
612 }
613 InstructionSelector::ComplexRendererFns
614 AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const {
615   return {{
616       [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
617       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
618       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }  // omod
619   }};
620 }
621 
622 InstructionSelector::ComplexRendererFns
623 AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
624   return {{
625       [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
626       [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }  // src_mods
627   }};
628 }
629 
630 InstructionSelector::ComplexRendererFns
631 AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const {
632   MachineRegisterInfo &MRI =
633       Root.getParent()->getParent()->getParent()->getRegInfo();
634 
635   SmallVector<GEPInfo, 4> AddrInfo;
636   getAddrModeInfo(*Root.getParent(), MRI, AddrInfo);
637 
638   if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
639     return None;
640 
641   const GEPInfo &GEPInfo = AddrInfo[0];
642 
643   if (!AMDGPU::isLegalSMRDImmOffset(STI, GEPInfo.Imm))
644     return None;
645 
646   unsigned PtrReg = GEPInfo.SgprParts[0];
647   int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
648   return {{
649     [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
650     [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
651   }};
652 }
653 
654 InstructionSelector::ComplexRendererFns
655 AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const {
656   MachineRegisterInfo &MRI =
657       Root.getParent()->getParent()->getParent()->getRegInfo();
658 
659   SmallVector<GEPInfo, 4> AddrInfo;
660   getAddrModeInfo(*Root.getParent(), MRI, AddrInfo);
661 
662   if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
663     return None;
664 
665   const GEPInfo &GEPInfo = AddrInfo[0];
666   unsigned PtrReg = GEPInfo.SgprParts[0];
667   int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
668   if (!isUInt<32>(EncodedImm))
669     return None;
670 
671   return {{
672     [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
673     [=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
674   }};
675 }
676 
677 InstructionSelector::ComplexRendererFns
678 AMDGPUInstructionSelector::selectSmrdSgpr(MachineOperand &Root) const {
679   MachineInstr *MI = Root.getParent();
680   MachineBasicBlock *MBB = MI->getParent();
681   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
682 
683   SmallVector<GEPInfo, 4> AddrInfo;
684   getAddrModeInfo(*MI, MRI, AddrInfo);
685 
686   // FIXME: We should shrink the GEP if the offset is known to be <= 32-bits,
687   // then we can select all ptr + 32-bit offsets not just immediate offsets.
688   if (AddrInfo.empty() || AddrInfo[0].SgprParts.size() != 1)
689     return None;
690 
691   const GEPInfo &GEPInfo = AddrInfo[0];
692   if (!GEPInfo.Imm || !isUInt<32>(GEPInfo.Imm))
693     return None;
694 
695   // If we make it this far we have a load with an 32-bit immediate offset.
696   // It is OK to select this using a sgpr offset, because we have already
697   // failed trying to select this load into one of the _IMM variants since
698   // the _IMM Patterns are considered before the _SGPR patterns.
699   unsigned PtrReg = GEPInfo.SgprParts[0];
700   unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
701   BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
702           .addImm(GEPInfo.Imm);
703   return {{
704     [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
705     [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
706   }};
707 }
708