1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node definitions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
22  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
23>;
24
25def AMDGPULdExpOp : SDTypeProfile<1, 2,
26  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
27>;
28
29def AMDGPUFPClassOp : SDTypeProfile<1, 2,
30  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
31>;
32
33def AMDGPUFPPackOp : SDTypeProfile<1, 2,
34  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
35>;
36
37def AMDGPUIntPackOp : SDTypeProfile<1, 2,
38  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
39>;
40
41def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
42  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
43>;
44
45// float, float, float, vcc
46def AMDGPUFmasOp : SDTypeProfile<1, 4,
47  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
48>;
49
50def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
51
52def AMDGPUIfOp : SDTypeProfile<1, 2,
53  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
54>;
55
56def AMDGPUElseOp : SDTypeProfile<1, 2,
57  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
58>;
59
60def AMDGPULoopOp : SDTypeProfile<0, 2,
61  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
62>;
63
64def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
65  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
66>;
67
68//===----------------------------------------------------------------------===//
69// AMDGPU DAG Nodes
70//
71
72def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
73def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
74def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
75
76def callseq_start : SDNode<"ISD::CALLSEQ_START",
77  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
78  [SDNPHasChain, SDNPOutGlue]
79>;
80
81def callseq_end : SDNode<"ISD::CALLSEQ_END",
82 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
83  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
84>;
85
86def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
87  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
88  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
89  SDNPVariadic]
90>;
91
92def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
93  SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
94  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
95>;
96
97def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
98  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
99    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
100>;
101
102def AMDGPUconstdata_ptr : SDNode<
103  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
104                                                     SDTCisVT<0, iPTR>]>
105>;
106
107// This argument to this node is a dword address.
108def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
109
110// Force dependencies for vector trunc stores
111def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
112
113def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
114def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
115// out = a - floor(a)
116def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
117
118// out = 1.0 / a
119def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
120
121// out = 1.0 / sqrt(a)
122def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
123
124def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
125
126def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
127
128// out = 1.0 / sqrt(a) result clamped to +/- max_float.
129def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
130
131def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
132
133def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
134def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
135def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
136def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
137def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
138def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
139def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
140
141
142def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
143
144// out = max(a, b) a and b are floats, where a nan comparison fails.
145// This is not commutative because this gives the second operand:
146//   x < nan ? x : nan -> nan
147//   nan < x ? nan : x -> x
148def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
149  []
150>;
151
152def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
153  [SDNPCommutative, SDNPAssociative]
154>;
155
156// out = min(a, b) a and b are floats, where a nan comparison fails.
157def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
158  []
159>;
160
161// FIXME: TableGen doesn't like commutative instructions with more
162// than 2 operands.
163// out = max(a, b, c) a, b and c are floats
164def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
165  [/*SDNPCommutative, SDNPAssociative*/]
166>;
167
168// out = max(a, b, c) a, b, and c are signed ints
169def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
170  [/*SDNPCommutative, SDNPAssociative*/]
171>;
172
173// out = max(a, b, c) a, b and c are unsigned ints
174def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
175  [/*SDNPCommutative, SDNPAssociative*/]
176>;
177
178// out = min(a, b, c) a, b and c are floats
179def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
180  [/*SDNPCommutative, SDNPAssociative*/]
181>;
182
183// out = min(a, b, c) a, b and c are signed ints
184def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
185  [/*SDNPCommutative, SDNPAssociative*/]
186>;
187
188// out = min(a, b) a and b are unsigned ints
189def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
190  [/*SDNPCommutative, SDNPAssociative*/]
191>;
192
193// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
194def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
195
196// out = (src1 > src0) ? 1 : 0
197def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
198
199def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
200  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
201]>;
202
203def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
204
205def AMDGPUSetRegOp :  SDTypeProfile<0, 2, [
206  SDTCisInt<0>, SDTCisInt<1>
207]>;
208
209def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
210  SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
211
212def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
213   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
214
215def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
216  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
217
218def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
219  SDTIntToFPOp, []>;
220def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
221  SDTIntToFPOp, []>;
222def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
223  SDTIntToFPOp, []>;
224def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
225  SDTIntToFPOp, []>;
226
227
228// urecip - This operation is a helper for integer division, it returns the
229// result of 1 / a as a fractional unsigned integer.
230// out = (2^32 / a) + e
231// e is rounding error
232def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
233
234// Special case divide preop and flags.
235def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
236
237//  Special case divide FMA with scale and flags (src0 = Quotient,
238//  src1 = Denominator, src2 = Numerator).
239def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
240                            [SDNPOptInGlue]>;
241
242// Single or double precision division fixup.
243// Special case divide fixup and flags(src0 = Quotient, src1 =
244// Denominator, src2 = Numerator).
245def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
246
247def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
248
249// Look Up 2.0 / pi src0 with segment select src1[4:0]
250def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
251
252def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
253                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
254                          [SDNPHasChain, SDNPMayLoad]>;
255
256def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
257                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
258                           [SDNPHasChain, SDNPMayStore]>;
259
260// MSKOR instructions are atomic memory instructions used mainly for storing
261// 8-bit and 16-bit values.  The definition is:
262//
263// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
264//
265// src0: vec4(src, 0, 0, mask)
266// src1: dst - rat offset (aka pointer) in dwords
267def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
268                        SDTypeProfile<0, 2, []>,
269                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
270
271def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
272                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
273                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
274                             SDNPMemOperand]>;
275
276def AMDGPUround : SDNode<"ISD::FROUND",
277                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
278
279def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
280def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
281def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
282def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
283
284def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
285def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
286
287def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
288
289// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
290// when performing the multiply. The result is a 32-bit value.
291def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
292  [SDNPCommutative, SDNPAssociative]
293>;
294def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
295  [SDNPCommutative, SDNPAssociative]
296>;
297
298def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
299  [SDNPCommutative, SDNPAssociative]
300>;
301def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
302  [SDNPCommutative, SDNPAssociative]
303>;
304
305def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
306  []
307>;
308def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
309  []
310>;
311
312def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
313  []
314>;
315
316def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
317  []
318>;
319
320def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
321
322def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
323                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
324                                       SDTCisFP<0>, SDTCisVec<1>,
325                                       SDTCisInt<4>]>,
326                  []>;
327
328def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
329
330// SI+ export
331def AMDGPUExportOp : SDTypeProfile<0, 8, [
332  SDTCisInt<0>,       // i8 tgt
333  SDTCisInt<1>,       // i8 en
334                      // i32 or f32 src0
335  SDTCisSameAs<3, 2>, // f32 src1
336  SDTCisSameAs<4, 2>, // f32 src2
337  SDTCisSameAs<5, 2>, // f32 src3
338  SDTCisInt<6>,       // i1 compr
339  // skip done
340  SDTCisInt<1>        // i1 vm
341
342]>;
343
344
345def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
346
347def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
348  [SDNPHasChain, SDNPSideEffect]>;
349
350//===----------------------------------------------------------------------===//
351// Flow Control Profile Types
352//===----------------------------------------------------------------------===//
353// Branch instruction where second and third are basic blocks
354def SDTIL_BRCond : SDTypeProfile<0, 2, [
355    SDTCisVT<0, OtherVT>
356    ]>;
357
358//===----------------------------------------------------------------------===//
359// Flow Control DAG Nodes
360//===----------------------------------------------------------------------===//
361def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
362
363//===----------------------------------------------------------------------===//
364// Call/Return DAG Nodes
365//===----------------------------------------------------------------------===//
366def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
367    [SDNPHasChain, SDNPOptInGlue]>;
368
369def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
370    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
371
372def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
373  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
374>;
375
376
377//===----------------------------------------------------------------------===//
378// Intrinsic/Custom node compatibility PatFrags
379//===----------------------------------------------------------------------===//
380
381def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
382                                           (AMDGPUrcp_impl node:$src)]>;
383def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
384                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
385
386def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
387                                           (AMDGPUrsq_impl node:$src)]>;
388
389def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
390                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
391
392def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
393                                           (AMDGPUsin_impl node:$src)]>;
394def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
395                                           (AMDGPUcos_impl node:$src)]>;
396def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
397                                             (AMDGPUfract_impl node:$src)]>;
398
399def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
400  [(int_amdgcn_ldexp node:$src0, node:$src1),
401   (AMDGPUldexp_impl node:$src0, node:$src1)]>;
402
403def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
404  [(int_amdgcn_class node:$src0, node:$src1),
405  (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
406
407def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
408  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
409   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
410
411def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
412  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
413   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
414
415def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
416  [(int_amdgcn_sffbh node:$src),
417   (AMDGPUffbh_i32_impl node:$src)]>;
418
419def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
420  [(ctlz_zero_undef node:$src),
421   (AMDGPUffbh_u32_impl node:$src)]>;
422
423def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
424  [(cttz_zero_undef node:$src),
425   (AMDGPUffbl_b32_impl node:$src)]>;
426
427def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
428  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
429  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
430
431def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
432  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
433  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
434
435def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
436  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
437  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
438
439def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
440  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
441  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
442
443def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
444  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
445  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
446
447def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
448  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
449   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
450
451def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
452  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
453   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
454
455def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
456  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
457   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
458
459def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
460  [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
461   (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
462
463def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
464  [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
465   (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
466
467def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
468  [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
469   (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
470
471def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
472  [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
473   (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
474
475def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
476  [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
477   (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
478