1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
24>;
25
26def AMDGPULdExpOp : SDTypeProfile<1, 2,
27  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
28>;
29
30def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
32>;
33
34def AMDGPUFPPackOp : SDTypeProfile<1, 2,
35  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
36>;
37
38def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
39  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
40>;
41
42// float, float, float, vcc
43def AMDGPUFmasOp : SDTypeProfile<1, 4,
44  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
45>;
46
47def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
48
49def AMDGPUIfOp : SDTypeProfile<1, 2,
50  [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
51>;
52
53def AMDGPUElseOp : SDTypeProfile<1, 2,
54  [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, OtherVT>]
55>;
56
57def AMDGPULoopOp : SDTypeProfile<0, 2,
58  [SDTCisVT<0, i64>, SDTCisVT<1, OtherVT>]
59>;
60
61def AMDGPUBreakOp : SDTypeProfile<1, 1,
62  [SDTCisVT<0, i64>, SDTCisVT<1, i64>]
63>;
64
65def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
66  [SDTCisVT<0, i64>, SDTCisVT<1, i1>, SDTCisVT<2, i64>]
67>;
68
69def AMDGPUElseBreakOp : SDTypeProfile<1, 2,
70  [SDTCisVT<0, i64>, SDTCisVT<1, i64>, SDTCisVT<2, i64>]
71>;
72
73def AMDGPUAddeSubeOp : SDTypeProfile<2, 3,
74  [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, i32>, SDTCisVT<1, i1>, SDTCisVT<4, i1>]
75>;
76
77//===----------------------------------------------------------------------===//
78// AMDGPU DAG Nodes
79//
80
81def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
82def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
83def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
84
85def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
86  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
87    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
88>;
89
90def AMDGPUconstdata_ptr : SDNode<
91  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
92                                                     SDTCisVT<0, iPTR>]>
93>;
94
95// This argument to this node is a dword address.
96def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
97
98// Force dependencies for vector trunc stores
99def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
100
101def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
102def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
103
104// out = a - floor(a)
105def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
106
107// out = 1.0 / a
108def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
109
110// out = 1.0 / sqrt(a)
111def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
112
113// out = 1.0 / sqrt(a)
114def AMDGPUrcp_legacy : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
115def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
116
117// out = 1.0 / sqrt(a) result clamped to +/- max_float.
118def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
119
120def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
121
122def AMDGPUpkrtz_f16_f32 : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
123def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
124def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
125
126
127def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
128
129// out = max(a, b) a and b are floats, where a nan comparison fails.
130// This is not commutative because this gives the second operand:
131//   x < nan ? x : nan -> nan
132//   nan < x ? nan : x -> x
133def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
134  []
135>;
136
137def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
138  [SDNPCommutative, SDNPAssociative]
139>;
140
141def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPUnaryOp>;
142
143// out = min(a, b) a and b are floats, where a nan comparison fails.
144def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
145  []
146>;
147
148// FIXME: TableGen doesn't like commutative instructions with more
149// than 2 operands.
150// out = max(a, b, c) a, b and c are floats
151def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
152  [/*SDNPCommutative, SDNPAssociative*/]
153>;
154
155// out = max(a, b, c) a, b, and c are signed ints
156def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
157  [/*SDNPCommutative, SDNPAssociative*/]
158>;
159
160// out = max(a, b, c) a, b and c are unsigned ints
161def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
162  [/*SDNPCommutative, SDNPAssociative*/]
163>;
164
165// out = min(a, b, c) a, b and c are floats
166def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
167  [/*SDNPCommutative, SDNPAssociative*/]
168>;
169
170// out = min(a, b, c) a, b and c are signed ints
171def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
172  [/*SDNPCommutative, SDNPAssociative*/]
173>;
174
175// out = min(a, b) a and b are unsigned ints
176def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
177  [/*SDNPCommutative, SDNPAssociative*/]
178>;
179
180// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
181def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
182
183// out = (src1 > src0) ? 1 : 0
184def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
185
186// TODO: remove AMDGPUadde/AMDGPUsube when ADDCARRY/SUBCARRY get their own
187// nodes in TargetSelectionDAG.td.
188def AMDGPUadde : SDNode<"ISD::ADDCARRY", AMDGPUAddeSubeOp, []>;
189
190def AMDGPUsube : SDNode<"ISD::SUBCARRY", AMDGPUAddeSubeOp, []>;
191
192def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
193  SDTCisVT<0, i64>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
194]>;
195
196def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
197
198def AMDGPUSetRegOp :  SDTypeProfile<0, 2, [
199  SDTCisInt<0>, SDTCisInt<1>
200]>;
201
202def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
203  SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
204
205def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
206   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207
208def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
209  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
210
211def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
212  SDTIntToFPOp, []>;
213def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
214  SDTIntToFPOp, []>;
215def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
216  SDTIntToFPOp, []>;
217def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
218  SDTIntToFPOp, []>;
219
220
221// urecip - This operation is a helper for integer division, it returns the
222// result of 1 / a as a fractional unsigned integer.
223// out = (2^32 / a) + e
224// e is rounding error
225def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
226
227// Special case divide preop and flags.
228def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
229
230//  Special case divide FMA with scale and flags (src0 = Quotient,
231//  src1 = Denominator, src2 = Numerator).
232def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
233
234// Single or double precision division fixup.
235// Special case divide fixup and flags(src0 = Quotient, src1 =
236// Denominator, src2 = Numerator).
237def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
238
239def AMDGPUfmad_ftz : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
240
241// Look Up 2.0 / pi src0 with segment select src1[4:0]
242def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
243
244def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
245                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
246                          [SDNPHasChain, SDNPMayLoad]>;
247
248def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
249                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
250                           [SDNPHasChain, SDNPMayStore]>;
251
252// MSKOR instructions are atomic memory instructions used mainly for storing
253// 8-bit and 16-bit values.  The definition is:
254//
255// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
256//
257// src0: vec4(src, 0, 0, mask)
258// src1: dst - rat offset (aka pointer) in dwords
259def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
260                        SDTypeProfile<0, 2, []>,
261                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
262
263def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
264                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
265                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
266                             SDNPMemOperand]>;
267
268def AMDGPUround : SDNode<"ISD::FROUND",
269                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
270
271def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
272def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
273def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
274def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
275
276def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
277def AMDGPUffbh_i32 : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
278
279// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
280// when performing the mulitply. The result is a 32-bit value.
281def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
282  [SDNPCommutative, SDNPAssociative]
283>;
284def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
285  [SDNPCommutative, SDNPAssociative]
286>;
287
288def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
289  [SDNPCommutative, SDNPAssociative]
290>;
291def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
292  [SDNPCommutative, SDNPAssociative]
293>;
294
295def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
296  []
297>;
298def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
299  []
300>;
301
302def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
303  []
304>;
305
306def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
307  []
308>;
309
310def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
311
312def AMDGPUinit_exec : SDNode<"AMDGPUISD::INIT_EXEC",
313                      SDTypeProfile<0, 1, [SDTCisInt<0>]>,
314                      [SDNPHasChain, SDNPInGlue]>;
315
316def AMDGPUinit_exec_from_input : SDNode<"AMDGPUISD::INIT_EXEC_FROM_INPUT",
317                                 SDTypeProfile<0, 2,
318                                 [SDTCisInt<0>, SDTCisInt<1>]>,
319                                 [SDNPHasChain, SDNPInGlue]>;
320
321def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
322                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
323                    [SDNPHasChain, SDNPInGlue]>;
324
325def AMDGPUsendmsghalt : SDNode<"AMDGPUISD::SENDMSGHALT",
326                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
327                    [SDNPHasChain, SDNPInGlue]>;
328
329def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
330                        SDTypeProfile<1, 3, [SDTCisFP<0>]>,
331                        [SDNPInGlue]>;
332
333def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
334                      SDTypeProfile<1, 3, [SDTCisFP<0>]>,
335                      [SDNPInGlue, SDNPOutGlue]>;
336
337def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
338                      SDTypeProfile<1, 4, [SDTCisFP<0>]>,
339                      [SDNPInGlue]>;
340
341
342def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
343  [SDNPHasChain, SDNPSideEffect]>;
344
345// SI+ export
346def AMDGPUExportOp : SDTypeProfile<0, 8, [
347  SDTCisInt<0>,       // i8 tgt
348  SDTCisInt<1>,       // i8 en
349                      // i32 or f32 src0
350  SDTCisSameAs<3, 2>, // f32 src1
351  SDTCisSameAs<4, 2>, // f32 src2
352  SDTCisSameAs<5, 2>, // f32 src3
353  SDTCisInt<6>,       // i1 compr
354  // skip done
355  SDTCisInt<1>        // i1 vm
356
357]>;
358
359def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
360  [SDNPHasChain, SDNPMayStore]>;
361
362def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
363  [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
364
365
366def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
367
368def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
369  [SDNPHasChain, SDNPSideEffect]>;
370
371//===----------------------------------------------------------------------===//
372// Flow Control Profile Types
373//===----------------------------------------------------------------------===//
374// Branch instruction where second and third are basic blocks
375def SDTIL_BRCond : SDTypeProfile<0, 2, [
376    SDTCisVT<0, OtherVT>
377    ]>;
378
379//===----------------------------------------------------------------------===//
380// Flow Control DAG Nodes
381//===----------------------------------------------------------------------===//
382def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
383
384//===----------------------------------------------------------------------===//
385// Call/Return DAG Nodes
386//===----------------------------------------------------------------------===//
387def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
388    [SDNPHasChain, SDNPOptInGlue]>;
389
390def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
391    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
392
393def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
394  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
395>;
396