1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node defintions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
22  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
23>;
24
25def AMDGPULdExpOp : SDTypeProfile<1, 2,
26  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
27>;
28
29def AMDGPUFPClassOp : SDTypeProfile<1, 2,
30  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
31>;
32
33def AMDGPUFPPackOp : SDTypeProfile<1, 2,
34  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
35>;
36
37def AMDGPUIntPackOp : SDTypeProfile<1, 2,
38  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
39>;
40
41def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
42  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
43>;
44
45// float, float, float, vcc
46def AMDGPUFmasOp : SDTypeProfile<1, 4,
47  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
48>;
49
50def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
51
52def AMDGPUIfOp : SDTypeProfile<1, 2,
53  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
54>;
55
56def AMDGPUElseOp : SDTypeProfile<1, 2,
57  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
58>;
59
60def AMDGPULoopOp : SDTypeProfile<0, 2,
61  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
62>;
63
64def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
65  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
66>;
67
68//===----------------------------------------------------------------------===//
69// AMDGPU DAG Nodes
70//
71
72def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
73def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
74def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
75
76def callseq_start : SDNode<"ISD::CALLSEQ_START",
77  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
78  [SDNPHasChain, SDNPOutGlue]
79>;
80
81def callseq_end : SDNode<"ISD::CALLSEQ_END",
82 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
83  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
84>;
85
86def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
87  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
88  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
89  SDNPVariadic]
90>;
91
92def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
93  SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
94  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
95>;
96
97def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
98  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
99    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
100>;
101
102def AMDGPUconstdata_ptr : SDNode<
103  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
104                                                     SDTCisVT<0, iPTR>]>
105>;
106
107// This argument to this node is a dword address.
108def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
109
110// Force dependencies for vector trunc stores
111def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
112
113def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
114def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
115// out = a - floor(a)
116def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
117
118// out = 1.0 / a
119def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
120
121// out = 1.0 / sqrt(a)
122def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
123
124// out = 1.0 / sqrt(a)
125def AMDGPUrsq_legacy_impl : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
126def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
127
128def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
129
130// out = 1.0 / sqrt(a) result clamped to +/- max_float.
131def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
132
133def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
134
135def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
136def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
137def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
138def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
139def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
140def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
141def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
142
143
144def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
145
146// out = max(a, b) a and b are floats, where a nan comparison fails.
147// This is not commutative because this gives the second operand:
148//   x < nan ? x : nan -> nan
149//   nan < x ? nan : x -> x
150def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
151  []
152>;
153
154def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
155  [SDNPCommutative, SDNPAssociative]
156>;
157
158// out = min(a, b) a and b are floats, where a nan comparison fails.
159def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
160  []
161>;
162
163// FIXME: TableGen doesn't like commutative instructions with more
164// than 2 operands.
165// out = max(a, b, c) a, b and c are floats
166def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
167  [/*SDNPCommutative, SDNPAssociative*/]
168>;
169
170// out = max(a, b, c) a, b, and c are signed ints
171def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
172  [/*SDNPCommutative, SDNPAssociative*/]
173>;
174
175// out = max(a, b, c) a, b and c are unsigned ints
176def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
177  [/*SDNPCommutative, SDNPAssociative*/]
178>;
179
180// out = min(a, b, c) a, b and c are floats
181def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
182  [/*SDNPCommutative, SDNPAssociative*/]
183>;
184
185// out = min(a, b, c) a, b and c are signed ints
186def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
187  [/*SDNPCommutative, SDNPAssociative*/]
188>;
189
190// out = min(a, b) a and b are unsigned ints
191def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
192  [/*SDNPCommutative, SDNPAssociative*/]
193>;
194
195// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
196def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
197
198// out = (src1 > src0) ? 1 : 0
199def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
200
201def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
202  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
203]>;
204
205def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
206
207def AMDGPUSetRegOp :  SDTypeProfile<0, 2, [
208  SDTCisInt<0>, SDTCisInt<1>
209]>;
210
211def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
212  SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
213
214def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
215   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216
217def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
218  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219
220def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
221  SDTIntToFPOp, []>;
222def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
223  SDTIntToFPOp, []>;
224def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
225  SDTIntToFPOp, []>;
226def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
227  SDTIntToFPOp, []>;
228
229
230// urecip - This operation is a helper for integer division, it returns the
231// result of 1 / a as a fractional unsigned integer.
232// out = (2^32 / a) + e
233// e is rounding error
234def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
235
236// Special case divide preop and flags.
237def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
238
239//  Special case divide FMA with scale and flags (src0 = Quotient,
240//  src1 = Denominator, src2 = Numerator).
241def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
242                            [SDNPOptInGlue]>;
243
244// Single or double precision division fixup.
245// Special case divide fixup and flags(src0 = Quotient, src1 =
246// Denominator, src2 = Numerator).
247def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
248
249def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
250
251// Look Up 2.0 / pi src0 with segment select src1[4:0]
252def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
253
254def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
255                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
256                          [SDNPHasChain, SDNPMayLoad]>;
257
258def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
259                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
260                           [SDNPHasChain, SDNPMayStore]>;
261
262// MSKOR instructions are atomic memory instructions used mainly for storing
263// 8-bit and 16-bit values.  The definition is:
264//
265// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
266//
267// src0: vec4(src, 0, 0, mask)
268// src1: dst - rat offset (aka pointer) in dwords
269def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
270                        SDTypeProfile<0, 2, []>,
271                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
272
273def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
274                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
275                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
276                             SDNPMemOperand]>;
277
278def AMDGPUround : SDNode<"ISD::FROUND",
279                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
280
281def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
282def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
283def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
284def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
285
286def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
287def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
288
289def AMDGPUffbl_b32 : SDNode<"AMDGPUISD::FFBL_B32", SDTIntUnaryOp>;
290
291// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
292// when performing the mulitply. The result is a 32-bit value.
293def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
294  [SDNPCommutative, SDNPAssociative]
295>;
296def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
297  [SDNPCommutative, SDNPAssociative]
298>;
299
300def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
301  [SDNPCommutative, SDNPAssociative]
302>;
303def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
304  [SDNPCommutative, SDNPAssociative]
305>;
306
307def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
308  []
309>;
310def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
311  []
312>;
313
314def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
315  []
316>;
317
318def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
319  []
320>;
321
322def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
323
324def AMDGPUfdot2 : SDNode<"AMDGPUISD::FDOT2",
325                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
326                                       SDTCisFP<0>, SDTCisVec<1>,
327                                       SDTCisInt<4>]>,
328                  []>;
329
330def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
331
332def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
333  [SDNPHasChain, SDNPSideEffect]>;
334
335// SI+ export
336def AMDGPUExportOp : SDTypeProfile<0, 8, [
337  SDTCisInt<0>,       // i8 tgt
338  SDTCisInt<1>,       // i8 en
339                      // i32 or f32 src0
340  SDTCisSameAs<3, 2>, // f32 src1
341  SDTCisSameAs<4, 2>, // f32 src2
342  SDTCisSameAs<5, 2>, // f32 src3
343  SDTCisInt<6>,       // i1 compr
344  // skip done
345  SDTCisInt<1>        // i1 vm
346
347]>;
348
349
350def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
351
352def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
353  [SDNPHasChain, SDNPSideEffect]>;
354
355//===----------------------------------------------------------------------===//
356// Flow Control Profile Types
357//===----------------------------------------------------------------------===//
358// Branch instruction where second and third are basic blocks
359def SDTIL_BRCond : SDTypeProfile<0, 2, [
360    SDTCisVT<0, OtherVT>
361    ]>;
362
363//===----------------------------------------------------------------------===//
364// Flow Control DAG Nodes
365//===----------------------------------------------------------------------===//
366def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
367
368//===----------------------------------------------------------------------===//
369// Call/Return DAG Nodes
370//===----------------------------------------------------------------------===//
371def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
372    [SDNPHasChain, SDNPOptInGlue]>;
373
374def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
375    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
376
377def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
378  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
379>;
380
381
382//===----------------------------------------------------------------------===//
383// Intrinsic/Custom node compatability PatFrags
384//===----------------------------------------------------------------------===//
385
386def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
387                                           (AMDGPUrcp_impl node:$src)]>;
388def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
389                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
390
391def AMDGPUrsq_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rsq_legacy node:$src),
392                                                  (AMDGPUrsq_legacy_impl node:$src)]>;
393
394def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
395                                           (AMDGPUrsq_impl node:$src)]>;
396
397def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
398                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
399
400def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
401                                           (AMDGPUsin_impl node:$src)]>;
402def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
403                                           (AMDGPUcos_impl node:$src)]>;
404def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
405                                             (AMDGPUfract_impl node:$src)]>;
406
407def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
408  [(int_amdgcn_ldexp node:$src0, node:$src1),
409   (AMDGPUldexp_impl node:$src0, node:$src1)]>;
410
411def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
412  [(int_amdgcn_class node:$src0, node:$src1),
413  (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
414
415def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
416  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
417   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
418
419def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
420  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
421   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
422
423def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
424  [(int_amdgcn_sffbh node:$src),
425   (AMDGPUffbh_i32_impl node:$src)]>;
426
427def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
428  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
429  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
430
431def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
432  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
433  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
434
435def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
436  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
437  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
438
439def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
440  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
441  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
442
443def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
444  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
445  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
446
447def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
448  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
449   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
450
451def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
452  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
453   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
454
455def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
456  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
457   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
458