1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
24>;
25
26def AMDGPULdExpOp : SDTypeProfile<1, 2,
27  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
28>;
29
30def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
32>;
33
34def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
36>;
37
38// float, float, float, vcc
39def AMDGPUFmasOp : SDTypeProfile<1, 4,
40  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
41>;
42
43//===----------------------------------------------------------------------===//
44// AMDGPU DAG Nodes
45//
46
47// This argument to this node is a dword address.
48def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
49
50def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
51def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
52
53// out = a - floor(a)
54def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
55
56// out = 1.0 / a
57def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
58
59// out = 1.0 / sqrt(a)
60def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
61
62// out = 1.0 / sqrt(a)
63def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
64
65// out = 1.0 / sqrt(a) result clamped to +/- max_float.
66def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
67
68def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
69
70def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
71
72// out = max(a, b) a and b are floats, where a nan comparison fails.
73// This is not commutative because this gives the second operand:
74//   x < nan ? x : nan -> nan
75//   nan < x ? nan : x -> x
76def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
77  []
78>;
79
80def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
81
82// out = max(a, b) a and b are signed ints
83def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
84  [SDNPCommutative, SDNPAssociative]
85>;
86
87// out = max(a, b) a and b are unsigned ints
88def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
89  [SDNPCommutative, SDNPAssociative]
90>;
91
92// out = min(a, b) a and b are floats, where a nan comparison fails.
93def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
94  []
95>;
96
97// FIXME: TableGen doesn't like commutative instructions with more
98// than 2 operands.
99// out = max(a, b, c) a, b and c are floats
100def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
101  [/*SDNPCommutative, SDNPAssociative*/]
102>;
103
104// out = max(a, b, c) a, b, and c are signed ints
105def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
106  [/*SDNPCommutative, SDNPAssociative*/]
107>;
108
109// out = max(a, b, c) a, b and c are unsigned ints
110def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
111  [/*SDNPCommutative, SDNPAssociative*/]
112>;
113
114// out = min(a, b, c) a, b and c are floats
115def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
116  [/*SDNPCommutative, SDNPAssociative*/]
117>;
118
119// out = min(a, b, c) a, b and c are signed ints
120def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
121  [/*SDNPCommutative, SDNPAssociative*/]
122>;
123
124// out = min(a, b) a and b are unsigned ints
125def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
126  [/*SDNPCommutative, SDNPAssociative*/]
127>;
128
129// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
130def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
131
132// out = (src1 > src0) ? 1 : 0
133def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
134
135
136def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
137  SDTIntToFPOp, []>;
138def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
139  SDTIntToFPOp, []>;
140def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
141  SDTIntToFPOp, []>;
142def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
143  SDTIntToFPOp, []>;
144
145
146// urecip - This operation is a helper for integer division, it returns the
147// result of 1 / a as a fractional unsigned integer.
148// out = (2^32 / a) + e
149// e is rounding error
150def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
151
152// Special case divide preop and flags.
153def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
154
155//  Special case divide FMA with scale and flags (src0 = Quotient,
156//  src1 = Denominator, src2 = Numerator).
157def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
158
159// Single or double precision division fixup.
160// Special case divide fixup and flags(src0 = Quotient, src1 =
161// Denominator, src2 = Numerator).
162def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
163
164// Look Up 2.0 / pi src0 with segment select src1[4:0]
165def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
166
167def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
168                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
169                          [SDNPHasChain, SDNPMayLoad]>;
170
171def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
172                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
173                           [SDNPHasChain, SDNPMayStore]>;
174
175// MSKOR instructions are atomic memory instructions used mainly for storing
176// 8-bit and 16-bit values.  The definition is:
177//
178// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
179//
180// src0: vec4(src, 0, 0, mask)
181// src1: dst - rat offset (aka pointer) in dwords
182def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
183                        SDTypeProfile<0, 2, []>,
184                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
185
186def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
187                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
188                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
189                             SDNPMemOperand]>;
190
191def AMDGPUround : SDNode<"ISD::FROUND",
192                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
193
194def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
195def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
196def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
197def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
198
199def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
200
201// Signed and unsigned 24-bit mulitply.  The highest 8-bits are ignore when
202// performing the mulitply.  The result is a 32-bit value.
203def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
204  [SDNPCommutative]
205>;
206def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
207  [SDNPCommutative]
208>;
209
210def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
211  []
212>;
213def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
214  []
215>;
216
217def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
218  []
219>;
220
221def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
222  []
223>;
224
225def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
226
227def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
228                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
229                    [SDNPHasChain, SDNPInGlue]>;
230
231def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
232                        SDTypeProfile<1, 3, [SDTCisFP<0>]>,
233                        [SDNPInGlue]>;
234
235def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
236                      SDTypeProfile<1, 3, [SDTCisFP<0>]>,
237                      [SDNPInGlue, SDNPOutGlue]>;
238
239def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
240                      SDTypeProfile<1, 4, [SDTCisFP<0>]>,
241                      [SDNPInGlue]>;
242
243//===----------------------------------------------------------------------===//
244// Flow Control Profile Types
245//===----------------------------------------------------------------------===//
246// Branch instruction where second and third are basic blocks
247def SDTIL_BRCond : SDTypeProfile<0, 2, [
248    SDTCisVT<0, OtherVT>
249    ]>;
250
251//===----------------------------------------------------------------------===//
252// Flow Control DAG Nodes
253//===----------------------------------------------------------------------===//
254def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
255
256//===----------------------------------------------------------------------===//
257// Call/Return DAG Nodes
258//===----------------------------------------------------------------------===//
259def IL_retflag       : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
260    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
261