1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node definitions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPULdExpOp : SDTypeProfile<1, 2,
22  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
23>;
24
25def AMDGPUFPClassOp : SDTypeProfile<1, 2,
26  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
27>;
28
29def AMDGPUFPPackOp : SDTypeProfile<1, 2,
30  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
31>;
32
33def AMDGPUIntPackOp : SDTypeProfile<1, 2,
34  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
35>;
36
37def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
38  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
39>;
40
41// float, float, float, vcc
42def AMDGPUFmasOp : SDTypeProfile<1, 4,
43  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
44>;
45
46def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
47
48def AMDGPUIfOp : SDTypeProfile<1, 2,
49  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
50>;
51
52def AMDGPUElseOp : SDTypeProfile<1, 2,
53  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
54>;
55
56def AMDGPULoopOp : SDTypeProfile<0, 2,
57  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
58>;
59
60def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
61  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
62>;
63
64//===----------------------------------------------------------------------===//
65// AMDGPU DAG Nodes
66//
67
68def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
69def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
70def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
71
72def callseq_start : SDNode<"ISD::CALLSEQ_START",
73  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
74  [SDNPHasChain, SDNPOutGlue]
75>;
76
77def callseq_end : SDNode<"ISD::CALLSEQ_END",
78 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
79  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
80>;
81
82def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
83  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
84  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
85  SDNPVariadic]
86>;
87
88def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
89  SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
90  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
91>;
92
93def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
94  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
95    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
96>;
97
98def AMDGPUconstdata_ptr : SDNode<
99  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
100                                                     SDTCisVT<0, iPTR>]>
101>;
102
103// This argument to this node is a dword address.
104def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
105
106// Force dependencies for vector trunc stores
107def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
108
109def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
110def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
111// out = a - floor(a)
112def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
113
114// out = 1.0 / a
115def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
116
117// out = 1.0 / sqrt(a)
118def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
119
120def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
121
122def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
123
124// out = 1.0 / sqrt(a) result clamped to +/- max_float.
125def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
126
127def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
128
129def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
130def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
131def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
132def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
133def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
134def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
135def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
136
137
138def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
139
140// out = max(a, b) a and b are floats, where a nan comparison fails.
141// This is not commutative because this gives the second operand:
142//   x < nan ? x : nan -> nan
143//   nan < x ? nan : x -> x
144def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
145  []
146>;
147
148def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
149  [SDNPCommutative, SDNPAssociative]
150>;
151
152// out = min(a, b) a and b are floats, where a nan comparison fails.
153def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
154  []
155>;
156
157// FIXME: TableGen doesn't like commutative instructions with more
158// than 2 operands.
159// out = max(a, b, c) a, b and c are floats
160def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
161  [/*SDNPCommutative, SDNPAssociative*/]
162>;
163
164// out = max(a, b, c) a, b, and c are signed ints
165def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
166  [/*SDNPCommutative, SDNPAssociative*/]
167>;
168
169// out = max(a, b, c) a, b and c are unsigned ints
170def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
171  [/*SDNPCommutative, SDNPAssociative*/]
172>;
173
174// out = min(a, b, c) a, b and c are floats
175def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
176  [/*SDNPCommutative, SDNPAssociative*/]
177>;
178
179// out = min(a, b, c) a, b and c are signed ints
180def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
181  [/*SDNPCommutative, SDNPAssociative*/]
182>;
183
184// out = min(a, b) a and b are unsigned ints
185def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
186  [/*SDNPCommutative, SDNPAssociative*/]
187>;
188
189// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
190def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
191
192// out = (src1 > src0) ? 1 : 0
193def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
194
195def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
196  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
197]>;
198
199def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
200
201def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
202   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
203
204def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
205  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
206
207def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
208  SDTIntToFPOp, []>;
209def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
210  SDTIntToFPOp, []>;
211def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
212  SDTIntToFPOp, []>;
213def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
214  SDTIntToFPOp, []>;
215
216def AMDGPUcvt_pk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32",
217  AMDGPUIntPackOp, []>;
218
219// urecip - This operation is a helper for integer division, it returns the
220// result of 1 / a as a fractional unsigned integer.
221// out = (2^32 / a) + e
222// e is rounding error
223def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
224
225// Special case divide preop and flags.
226def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
227
228//  Special case divide FMA with scale and flags (src0 = Quotient,
229//  src1 = Denominator, src2 = Numerator).
230def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
231                            [SDNPOptInGlue]>;
232
233// Single or double precision division fixup.
234// Special case divide fixup and flags(src0 = Quotient, src1 =
235// Denominator, src2 = Numerator).
236def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
237
238def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
239
240def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
241                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
242                          [SDNPHasChain, SDNPMayLoad]>;
243
244def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
245                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
246                           [SDNPHasChain, SDNPMayStore]>;
247
248// MSKOR instructions are atomic memory instructions used mainly for storing
249// 8-bit and 16-bit values.  The definition is:
250//
251// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
252//
253// src0: vec4(src, 0, 0, mask)
254// src1: dst - rat offset (aka pointer) in dwords
255def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
256                        SDTypeProfile<0, 2, []>,
257                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
258
259def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
260                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
261                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
262                             SDNPMemOperand]>;
263
264def AMDGPUround : SDNode<"ISD::FROUND",
265                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
266
267def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
268def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
269def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
270def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
271
272def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
273def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
274
275def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
276
277// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
278// when performing the multiply. The result is a 32-bit value.
279def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
280  [SDNPCommutative, SDNPAssociative]
281>;
282def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
283  [SDNPCommutative, SDNPAssociative]
284>;
285
286def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
287  [SDNPCommutative, SDNPAssociative]
288>;
289def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
290  [SDNPCommutative, SDNPAssociative]
291>;
292
293def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
294  []
295>;
296def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
297  []
298>;
299
300def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
301  []
302>;
303
304def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
305  []
306>;
307
308def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
309
310def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
311                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
312                                       SDTCisFP<0>, SDTCisVec<1>,
313                                       SDTCisInt<4>]>,
314                  []>;
315
316def AMDGPUperm_impl : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
317
318// SI+ export
319def AMDGPUExportOp : SDTypeProfile<0, 8, [
320  SDTCisInt<0>,       // i8 tgt
321  SDTCisInt<1>,       // i8 en
322                      // i32 or f32 src0
323  SDTCisSameAs<3, 2>, // f32 src1
324  SDTCisSameAs<4, 2>, // f32 src2
325  SDTCisSameAs<5, 2>, // f32 src3
326  SDTCisInt<6>,       // i1 compr
327  // skip done
328  SDTCisInt<1>        // i1 vm
329
330]>;
331
332
333def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
334
335def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
336  [SDNPHasChain, SDNPSideEffect]>;
337
338//===----------------------------------------------------------------------===//
339// Flow Control Profile Types
340//===----------------------------------------------------------------------===//
341// Branch instruction where second and third are basic blocks
342def SDTIL_BRCond : SDTypeProfile<0, 2, [
343    SDTCisVT<0, OtherVT>
344    ]>;
345
346//===----------------------------------------------------------------------===//
347// Flow Control DAG Nodes
348//===----------------------------------------------------------------------===//
349def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
350
351//===----------------------------------------------------------------------===//
352// Call/Return DAG Nodes
353//===----------------------------------------------------------------------===//
354def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
355    [SDNPHasChain, SDNPOptInGlue]>;
356
357def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
358    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
359
360def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
361  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
362>;
363
364
365//===----------------------------------------------------------------------===//
366// Intrinsic/Custom node compatibility PatFrags
367//===----------------------------------------------------------------------===//
368
369def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
370                                           (AMDGPUrcp_impl node:$src)]>;
371def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
372                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
373
374def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
375                                           (AMDGPUrsq_impl node:$src)]>;
376
377def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
378                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
379
380def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
381                                           (AMDGPUsin_impl node:$src)]>;
382def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
383                                           (AMDGPUcos_impl node:$src)]>;
384def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
385                                             (AMDGPUfract_impl node:$src)]>;
386
387def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
388  [(int_amdgcn_ldexp node:$src0, node:$src1),
389   (AMDGPUldexp_impl node:$src0, node:$src1)]>;
390
391def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
392  [(int_amdgcn_class node:$src0, node:$src1),
393  (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
394
395def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
396  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
397   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
398
399def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
400  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
401   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
402
403def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
404  [(int_amdgcn_sffbh node:$src),
405   (AMDGPUffbh_i32_impl node:$src)]>;
406
407def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
408  [(ctlz_zero_undef node:$src),
409   (AMDGPUffbh_u32_impl node:$src)]>;
410
411def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
412  [(cttz_zero_undef node:$src),
413   (AMDGPUffbl_b32_impl node:$src)]>;
414
415def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
416  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
417  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
418
419def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
420  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
421  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
422
423def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
424  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
425  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
426
427def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
428  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
429  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
430
431def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
432  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
433  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
434
435def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
436  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
437   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
438
439def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
440  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
441   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
442
443def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
444  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
445   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
446
447def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
448  [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
449   (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
450
451def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
452  [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
453   (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
454
455def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
456  [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
457   (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
458
459def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
460  [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
461   (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
462
463def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
464  [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
465   (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
466
467def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
468  [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
469   (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;
470