1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
18 
19 #include "llvm/Target/TargetInstrInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #define GET_INSTRINFO_ENUM
23 #define GET_INSTRINFO_OPERAND_ENUM
24 #include "AMDGPUGenInstrInfo.inc"
25 
26 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
27 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
28 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
29 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
30 
31 namespace llvm {
32 
33 class AMDGPUSubtarget;
34 class MachineFunction;
35 class MachineInstr;
36 class MachineInstrBuilder;
37 
38 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
39 private:
40   const AMDGPUSubtarget &ST;
41 
42   virtual void anchor();
43 
44 public:
45   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
46 
47   /// \returns the smallest register index that will be accessed by an indirect
48   /// read or write or -1 if indirect addressing is not used by this program.
49   int getIndirectIndexBegin(const MachineFunction &MF) const;
50 
51   /// \returns the largest register index that will be accessed by an indirect
52   /// read or write or -1 if indirect addressing is not used by this program.
53   int getIndirectIndexEnd(const MachineFunction &MF) const;
54 
55   bool enableClusterLoads() const override;
56 
57   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
58                                int64_t Offset1, int64_t Offset2,
59                                unsigned NumLoads) const override;
60 
61   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
62   /// Return -1 if the target-specific opcode for the pseudo instruction does
63   /// not exist. If Opcode is not a pseudo instruction, this is identity.
64   int pseudoToMCOpcode(int Opcode) const;
65 
66 //===---------------------------------------------------------------------===//
67 // Pure virtual funtions to be implemented by sub-classes.
68 //===---------------------------------------------------------------------===//
69 
70   /// \returns The register class to be used for loading and storing values
71   /// from an "Indirect Address" .
72   virtual const TargetRegisterClass *getIndirectAddrRegClass() const {
73     llvm_unreachable("getIndirectAddrRegClass() not implemented");
74   }
75 
76   /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
77   /// equivalent opcode that writes \p Channels Channels.
78   int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
79 };
80 
81 namespace AMDGPU {
82   LLVM_READONLY
83   int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
84 }  // End namespace AMDGPU
85 
86 } // End llvm namespace
87 
88 #define AMDGPU_FLAG_REGISTER_LOAD  (UINT64_C(1) << 63)
89 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
90 
91 #endif
92