1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
18 
19 #include "AMDGPURegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #define GET_INSTRINFO_ENUM
24 #define GET_INSTRINFO_OPERAND_ENUM
25 #include "AMDGPUGenInstrInfo.inc"
26 
27 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
28 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
29 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
30 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
31 
32 namespace llvm {
33 
34 class AMDGPUSubtarget;
35 class MachineFunction;
36 class MachineInstr;
37 class MachineInstrBuilder;
38 
39 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
40 private:
41   const AMDGPURegisterInfo RI;
42   virtual void anchor();
43 protected:
44   const AMDGPUSubtarget &ST;
45 public:
46   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
47 
48   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
49 
50 public:
51   /// \returns the smallest register index that will be accessed by an indirect
52   /// read or write or -1 if indirect addressing is not used by this program.
53   int getIndirectIndexBegin(const MachineFunction &MF) const;
54 
55   /// \returns the largest register index that will be accessed by an indirect
56   /// read or write or -1 if indirect addressing is not used by this program.
57   int getIndirectIndexEnd(const MachineFunction &MF) const;
58 
59   bool enableClusterLoads() const override;
60 
61   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
62                                int64_t Offset1, int64_t Offset2,
63                                unsigned NumLoads) const override;
64 
65   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
66   /// Return -1 if the target-specific opcode for the pseudo instruction does
67   /// not exist. If Opcode is not a pseudo instruction, this is identity.
68   int pseudoToMCOpcode(int Opcode) const;
69 
70 //===---------------------------------------------------------------------===//
71 // Pure virtual funtions to be implemented by sub-classes.
72 //===---------------------------------------------------------------------===//
73 
74   /// \returns The register class to be used for loading and storing values
75   /// from an "Indirect Address" .
76   virtual const TargetRegisterClass *getIndirectAddrRegClass() const {
77     llvm_unreachable("getIndirectAddrRegClass() not implemented");
78   }
79 
80   /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
81   /// equivalent opcode that writes \p Channels Channels.
82   int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
83 
84 };
85 
86 namespace AMDGPU {
87   LLVM_READONLY
88   int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
89 }  // End namespace AMDGPU
90 
91 } // End llvm namespace
92 
93 #define AMDGPU_FLAG_REGISTER_LOAD  (UINT64_C(1) << 63)
94 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
95 
96 #endif
97