1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Contains the definition of a TargetInstrInfo class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 
18 #include "Utils/AMDGPUBaseInfo.h"
19 
20 namespace llvm {
21 
22 class GCNSubtarget;
23 class MachineMemOperand;
24 
25 class AMDGPUInstrInfo {
26 public:
27   explicit AMDGPUInstrInfo(const GCNSubtarget &st);
28 
29   static bool isUniformMMO(const MachineMemOperand *MMO);
30 };
31 
32 namespace AMDGPU {
33 
34 struct RsrcIntrinsic {
35   unsigned Intr;
36   uint8_t RsrcArg;
37   bool IsImage;
38 };
39 const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
40 
41 struct D16ImageDimIntrinsic {
42   unsigned Intr;
43   unsigned D16HelperIntr;
44 };
45 const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
46 
47 struct ImageDimIntrinsicInfo {
48   unsigned Intr;
49   unsigned BaseOpcode;
50   MIMGDim Dim;
51 
52   uint8_t NumGradients;
53   uint8_t NumDmask;
54   uint8_t NumData;
55   uint8_t NumVAddrs;
56   uint8_t NumArgs;
57 
58   uint8_t DMaskIndex;
59   uint8_t VAddrStart;
60   uint8_t GradientStart;
61   uint8_t CoordStart;
62   uint8_t LodIndex;
63   uint8_t MipIndex;
64   uint8_t VAddrEnd;
65   uint8_t RsrcIndex;
66   uint8_t SampIndex;
67   uint8_t UnormIndex;
68   uint8_t TexFailCtrlIndex;
69   uint8_t CachePolicyIndex;
70 
71   uint8_t GradientTyArg;
72   uint8_t CoordTyArg;
73 };
74 const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
75 
76 const ImageDimIntrinsicInfo *
77 getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim);
78 
79 } // end AMDGPU namespace
80 } // End llvm namespace
81 
82 #endif
83