1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUINSTRINFO_H
18 
19 #include "AMDGPURegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include <map>
22 
23 #define GET_INSTRINFO_HEADER
24 #define GET_INSTRINFO_ENUM
25 #define GET_INSTRINFO_OPERAND_ENUM
26 #include "AMDGPUGenInstrInfo.inc"
27 
28 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
29 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
30 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
31 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
32 
33 namespace llvm {
34 
35 class AMDGPUSubtarget;
36 class MachineFunction;
37 class MachineInstr;
38 class MachineInstrBuilder;
39 
40 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
41 private:
42   const AMDGPURegisterInfo RI;
43   virtual void anchor();
44 protected:
45   const AMDGPUSubtarget &ST;
46 public:
47   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
48 
49   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
50 
51 public:
52   /// \returns the smallest register index that will be accessed by an indirect
53   /// read or write or -1 if indirect addressing is not used by this program.
54   int getIndirectIndexBegin(const MachineFunction &MF) const;
55 
56   /// \returns the largest register index that will be accessed by an indirect
57   /// read or write or -1 if indirect addressing is not used by this program.
58   int getIndirectIndexEnd(const MachineFunction &MF) const;
59 
60   bool enableClusterLoads() const override;
61 
62   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
63                                int64_t Offset1, int64_t Offset2,
64                                unsigned NumLoads) const override;
65 
66 
67   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
68   /// Return -1 if the target-specific opcode for the pseudo instruction does
69   /// not exist. If Opcode is not a pseudo instruction, this is identity.
70   int pseudoToMCOpcode(int Opcode) const;
71 
72 //===---------------------------------------------------------------------===//
73 // Pure virtual funtions to be implemented by sub-classes.
74 //===---------------------------------------------------------------------===//
75 
76   /// \returns The register class to be used for loading and storing values
77   /// from an "Indirect Address" .
78   virtual const TargetRegisterClass *getIndirectAddrRegClass() const {
79     llvm_unreachable("getIndirectAddrRegClass() not implemented");
80   }
81 
82   /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
83   /// equivalent opcode that writes \p Channels Channels.
84   int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
85 
86 };
87 
88 namespace AMDGPU {
89   LLVM_READONLY
90   int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
91 }  // End namespace AMDGPU
92 
93 } // End llvm namespace
94 
95 #define AMDGPU_FLAG_REGISTER_LOAD  (UINT64_C(1) << 63)
96 #define AMDGPU_FLAG_REGISTER_STORE (UINT64_C(1) << 62)
97 
98 #endif
99