1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
18 
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #define GET_INSTRINFO_ENUM
24 #include "AMDGPUGenInstrInfo.inc"
25 
26 namespace llvm {
27 
28 class AMDGPUSubtarget;
29 class MachineFunction;
30 class MachineInstr;
31 class MachineInstrBuilder;
32 
33 class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
34 private:
35   const AMDGPUSubtarget &ST;
36 
37   virtual void anchor();
38 
39 public:
40   explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
41 
42   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
43                                int64_t Offset1, int64_t Offset2,
44                                unsigned NumLoads) const override;
45 
46   /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
47   /// Return -1 if the target-specific opcode for the pseudo instruction does
48   /// not exist. If Opcode is not a pseudo instruction, this is identity.
49   int pseudoToMCOpcode(int Opcode) const;
50 
51   /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
52   /// equivalent opcode that writes \p Channels Channels.
53   int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
54 };
55 } // End llvm namespace
56 
57 #endif
58