1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
12 /// AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 
23 using namespace llvm;
24 
25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRMAP_INFO
27 #include "AMDGPUGenInstrInfo.inc"
28 
29 // Pin the vtable to this file.
30 void AMDGPUInstrInfo::anchor() {}
31 
32 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &ST)
33   : AMDGPUGenInstrInfo(-1, -1), ST(ST) {}
34 
35 bool AMDGPUInstrInfo::enableClusterLoads() const {
36   return true;
37 }
38 
39 bool AMDGPUInstrInfo::enableClusterStores() const {
40   return true;
41 }
42 
43 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
44 // the first 16 loads will be interleaved with the stores, and the next 16 will
45 // be clustered as expected. It should really split into 2 16 store batches.
46 //
47 // Loads are clustered until this returns false, rather than trying to schedule
48 // groups of stores. This also means we have to deal with saying different
49 // address space loads should be clustered, and ones which might cause bank
50 // conflicts.
51 //
52 // This might be deprecated so it might not be worth that much effort to fix.
53 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
54                                               int64_t Offset0, int64_t Offset1,
55                                               unsigned NumLoads) const {
56   assert(Offset1 > Offset0 &&
57          "Second offset should be larger than first offset!");
58   // If we have less than 16 loads in a row, and the offsets are within 64
59   // bytes, then schedule together.
60 
61   // A cacheline is 64 bytes (for global memory).
62   return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
63 }
64 
65 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
66   switch (Channels) {
67   default: return Opcode;
68   case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
69   case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
70   case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
71   }
72 }
73 
74 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
75 enum SIEncodingFamily {
76   SI = 0,
77   VI = 1
78 };
79 
80 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
81 // header files, so we need to wrap it in a function that takes unsigned
82 // instead.
83 namespace llvm {
84 namespace AMDGPU {
85 static int getMCOpcode(uint16_t Opcode, unsigned Gen) {
86   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
87 }
88 }
89 }
90 
91 static SIEncodingFamily subtargetEncodingFamily(const AMDGPUSubtarget &ST) {
92   switch (ST.getGeneration()) {
93   case AMDGPUSubtarget::SOUTHERN_ISLANDS:
94   case AMDGPUSubtarget::SEA_ISLANDS:
95     return SIEncodingFamily::SI;
96   case AMDGPUSubtarget::VOLCANIC_ISLANDS:
97     return SIEncodingFamily::VI;
98 
99   // FIXME: This should never be called for r600 GPUs.
100   case AMDGPUSubtarget::R600:
101   case AMDGPUSubtarget::R700:
102   case AMDGPUSubtarget::EVERGREEN:
103   case AMDGPUSubtarget::NORTHERN_ISLANDS:
104     return SIEncodingFamily::SI;
105   }
106 
107   llvm_unreachable("Unknown subtarget generation!");
108 }
109 
110 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
111   int MCOp = AMDGPU::getMCOpcode(Opcode, subtargetEncodingFamily(ST));
112 
113   // -1 means that Opcode is already a native instruction.
114   if (MCOp == -1)
115     return Opcode;
116 
117   // (uint16_t)-1 means that Opcode is a pseudo instruction that has
118   // no encoding in the given subtarget generation.
119   if (MCOp == (uint16_t)-1)
120     return -1;
121 
122   return MCOp;
123 }
124